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/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
70 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ argument
72 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
78 #define imx_clk_pfd(name, parent_name, reg, idx) \ argument
79 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
81 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument
82 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
90 #define imx_clk_divider(name, parent, reg, shift, width) \ argument
91 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
[all …]
H A Dclk-busy.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
16 static int clk_busy_wait(void __iomem *reg, u8 shift) in clk_busy_wait() argument
20 while (readl_relaxed(reg) & (1 << shift)) in clk_busy_wait()
22 return -ETIMEDOUT; in clk_busy_wait()
30 void __iomem *reg; member
31 u8 shift; member
46 return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate); in clk_busy_divider_recalc_rate()
54 return busy->div_ops->round_rate(&busy->div.hw, rate, prate); in clk_busy_divider_round_rate()
63 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); in clk_busy_divider_set_rate()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
13 reg = <0x4>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
[all …]
H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
18 reg = <0x0d40>;
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
[all …]
H A Domap2430-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
13 reg = <0x78>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
27 reg = <0x78>;
[all …]
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <59000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <12000000>;
21 #clock-cells = <0>;
22 compatible = "ti,gate-clock";
24 ti,bit-shift = <8>;
[all …]
H A Domap34xx-omap36xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <1>;
17 #clock-cells = <0>;
18 compatible = "ti,omap3-interface-clock";
20 ti,bit-shift = <3>;
21 reg = <0x0a14>;
25 #clock-cells = <0>;
[all …]
H A Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
15 #clock-cells = <0>;
16 compatible = "ti,dra7-atl-clock";
21 #clock-cells = <0>;
22 compatible = "ti,dra7-atl-clock";
27 #clock-cells = <0>;
28 compatible = "ti,dra7-atl-clock";
33 #clock-cells = <0>;
[all …]
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <12000000>;
15 #clock-cells = <0>;
16 compatible = "ti,gate-clock";
18 ti,bit-shift = <8>;
19 reg = <0x0108>;
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
[all …]
H A Domap2420-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-no-wait-gate-clock";
13 ti,bit-shift = <15>;
14 reg = <0x0070>;
18 #clock-cells = <0>;
19 compatible = "ti,composite-mux-clock";
21 ti,bit-shift = <8>;
22 reg = <0x0070>;
26 #clock-cells = <0>;
[all …]
H A Domap3430es1-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,wait-gate-clock";
12 reg = <0x0b10>;
13 ti,bit-shift = <0>;
17 #clock-cells = <0>;
18 compatible = "ti,divider-clock";
20 ti,max-div = <7>;
21 reg = <0x0b40>;
22 ti,index-starts-at-one;
[all …]
/OK3568_Linux_fs/kernel/drivers/memory/tegra/
H A Dtegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/memory/tegra210-mc.h>
20 .reg = 0x228,
24 .reg = 0x2e8,
25 .shift = 0,
34 .reg = 0x228,
38 .reg = 0x2f4,
39 .shift = 0,
48 .reg = 0x228,
52 .reg = 0x2e8,
[all …]
H A Dtegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra30-mc.h>
44 .reg = 0x228,
48 .reg = 0x2e8,
49 .shift = 0,
58 .reg = 0x228,
62 .reg = 0x2f4,
63 .shift = 0,
72 .reg = 0x228,
76 .reg = 0x2e8,
[all …]
H A Dtegra114.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra114-mc.h>
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
51 .reg = 0x228,
55 .reg = 0x2e8,
[all …]
H A Dtegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra124-mc.h>
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
51 .reg = 0x228,
55 .reg = 0x2e8,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Domap3xxx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <16800000>;
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
21 reg = <0x0d40>;
25 #clock-cells = <0>;
26 compatible = "ti,divider-clock";
28 ti,bit-shift = <6>;
29 ti,max-div = <3>;
[all …]
H A Ddra7xx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "ti,dra7-atl-clock";
18 #clock-cells = <0>;
19 compatible = "ti,dra7-atl-clock";
24 #clock-cells = <0>;
25 compatible = "ti,dra7-atl-clock";
30 #clock-cells = <0>;
31 compatible = "ti,dra7-atl-clock";
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
[all …]
H A Domap34xx-omap36xx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "fixed-factor-clock";
15 clock-mult = <1>;
16 clock-div = <1>;
20 #clock-cells = <0>;
21 compatible = "ti,omap3-interface-clock";
23 ti,bit-shift = <3>;
24 reg = <0x0a14>;
28 #clock-cells = <0>;
29 compatible = "ti,omap3-interface-clock";
[all …]
H A Dam43xx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
15 ti,bit-shift = <31>;
16 reg = <0x0040>;
20 #clock-cells = <0>;
21 compatible = "ti,mux-clock";
23 ti,bit-shift = <29>;
24 reg = <0x0040>;
28 #clock-cells = <0>;
29 compatible = "ti,mux-clock";
[all …]
/OK3568_Linux_fs/kernel/drivers/bus/
H A Dda8xx-mstpri.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * some changes (as is the case for the LCD controller on da850-lcdk - the
54 int reg; member
55 int shift; member
61 .reg = DA8XX_MSTPRI0_OFFSET,
62 .shift = 0,
66 .reg = DA8XX_MSTPRI0_OFFSET,
67 .shift = 4,
71 .reg = DA8XX_MSTPRI0_OFFSET,
72 .shift = 16,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
21 u32 reg; in scg_src_get_rate() local
25 reg = readl(&scg1_regs->sosccsr); in scg_src_get_rate()
26 if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK)) in scg_src_get_rate()
31 reg = readl(&scg1_regs->firccsr); in scg_src_get_rate()
32 if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK)) in scg_src_get_rate()
37 reg = readl(&scg1_regs->sirccsr); in scg_src_get_rate()
38 if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK)) in scg_src_get_rate()
43 reg = readl(&scg1_regs->rtccsr); in scg_src_get_rate()
[all …]
/OK3568_Linux_fs/kernel/drivers/regulator/
H A Dmax8998.c1 // SPDX-License-Identifier: GPL-2.0+
3 // max8998.c - Voltage regulator driver for the Maxim 8998
5 // Copyright (C) 2009-2010 Samsung Electronics
23 #include <linux/mfd/max8998-private.h>
41 int *reg, int *shift) in max8998_get_enable_register() argument
47 *reg = MAX8998_REG_ONOFF1; in max8998_get_enable_register()
48 *shift = 3 - (ldo - MAX8998_LDO2); in max8998_get_enable_register()
51 *reg = MAX8998_REG_ONOFF2; in max8998_get_enable_register()
52 *shift = 7 - (ldo - MAX8998_LDO6); in max8998_get_enable_register()
55 *reg = MAX8998_REG_ONOFF3; in max8998_get_enable_register()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Dvp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 * struct omap_vp_ops - per-VP operations
36 * struct omap_vp_common - register data common to all VDDs
37 * @vpconfig_erroroffset_mask: ERROROFFSET bitmask in the PRM_VP*_CONFIG reg
38 * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
39 * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
40 * @vpconfig_timeouten: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
41 * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg
42 * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg
43 * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-axm5516.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/clk-axm5516.c
16 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/lsi,axm5516-clks.h>
22 * struct axxia_clk - Common struct to all Axxia clocks.
33 * struct axxia_pllclk - Axxia PLL generated clock.
35 * @reg: Offset into regmap for PLL control register
39 u32 reg; member
44 * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the
55 regmap_read(aclk->regmap, pll->reg, &control); in axxia_pllclk_recalc()
[all …]
/OK3568_Linux_fs/kernel/sound/soc/sprd/
H A Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
118 static void sprd_mcdt_update(struct sprd_mcdt_dev *mcdt, u32 reg, u32 val, in sprd_mcdt_update() argument
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
131 u32 reg = MCDT_DAC0_WTMK + channel * 4; in sprd_mcdt_dac_set_watermark() local
136 sprd_mcdt_update(mcdt, reg, water_mark, in sprd_mcdt_dac_set_watermark()
143 u32 reg = MCDT_ADC0_WTMK + channel * 4; in sprd_mcdt_adc_set_watermark() local
148 sprd_mcdt_update(mcdt, reg, water_mark, in sprd_mcdt_adc_set_watermark()
155 u32 shift = MCDT_DAC_DMA_SHIFT + channel; in sprd_mcdt_dac_dma_enable() local
[all …]

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