Lines Matching +full:reg +full:- +full:shift
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
21 u32 reg; in scg_src_get_rate() local
25 reg = readl(&scg1_regs->sosccsr); in scg_src_get_rate()
26 if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK)) in scg_src_get_rate()
31 reg = readl(&scg1_regs->firccsr); in scg_src_get_rate()
32 if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK)) in scg_src_get_rate()
37 reg = readl(&scg1_regs->sirccsr); in scg_src_get_rate()
38 if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK)) in scg_src_get_rate()
43 reg = readl(&scg1_regs->rtccsr); in scg_src_get_rate()
44 if (!(reg & SCG_ROSC_CSR_ROSCVLD_MASK)) in scg_src_get_rate()
57 u32 reg, val, rate; in scg_sircdiv_get_rate() local
58 u32 shift, mask; in scg_sircdiv_get_rate() local
63 shift = SCG_SIRCDIV_DIV1_SHIFT; in scg_sircdiv_get_rate()
67 shift = SCG_SIRCDIV_DIV2_SHIFT; in scg_sircdiv_get_rate()
71 shift = SCG_SIRCDIV_DIV3_SHIFT; in scg_sircdiv_get_rate()
77 reg = readl(&scg1_regs->sirccsr); in scg_sircdiv_get_rate()
78 if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK)) in scg_sircdiv_get_rate()
81 reg = readl(&scg1_regs->sircdiv); in scg_sircdiv_get_rate()
82 val = (reg & mask) >> shift; in scg_sircdiv_get_rate()
88 rate = rate / (1 << (val - 1)); in scg_sircdiv_get_rate()
95 u32 reg, val, rate; in scg_fircdiv_get_rate() local
96 u32 shift, mask; in scg_fircdiv_get_rate() local
101 shift = SCG_FIRCDIV_DIV1_SHIFT; in scg_fircdiv_get_rate()
105 shift = SCG_FIRCDIV_DIV2_SHIFT; in scg_fircdiv_get_rate()
109 shift = SCG_FIRCDIV_DIV3_SHIFT; in scg_fircdiv_get_rate()
115 reg = readl(&scg1_regs->firccsr); in scg_fircdiv_get_rate()
116 if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK)) in scg_fircdiv_get_rate()
119 reg = readl(&scg1_regs->fircdiv); in scg_fircdiv_get_rate()
120 val = (reg & mask) >> shift; in scg_fircdiv_get_rate()
126 rate = rate / (1 << (val - 1)); in scg_fircdiv_get_rate()
133 u32 reg, val, rate; in scg_soscdiv_get_rate() local
134 u32 shift, mask; in scg_soscdiv_get_rate() local
139 shift = SCG_SOSCDIV_DIV1_SHIFT; in scg_soscdiv_get_rate()
143 shift = SCG_SOSCDIV_DIV2_SHIFT; in scg_soscdiv_get_rate()
147 shift = SCG_SOSCDIV_DIV3_SHIFT; in scg_soscdiv_get_rate()
153 reg = readl(&scg1_regs->sosccsr); in scg_soscdiv_get_rate()
154 if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK)) in scg_soscdiv_get_rate()
157 reg = readl(&scg1_regs->soscdiv); in scg_soscdiv_get_rate()
158 val = (reg & mask) >> shift; in scg_soscdiv_get_rate()
164 rate = rate / (1 << (val - 1)); in scg_soscdiv_get_rate()
171 u32 reg, val, rate; in scg_apll_pfd_get_rate() local
172 u32 shift, mask, gate, valid; in scg_apll_pfd_get_rate() local
179 shift = SCG_PLL_PFD0_FRAC_SHIFT; in scg_apll_pfd_get_rate()
185 shift = SCG_PLL_PFD1_FRAC_SHIFT; in scg_apll_pfd_get_rate()
191 shift = SCG_PLL_PFD2_FRAC_SHIFT; in scg_apll_pfd_get_rate()
197 shift = SCG_PLL_PFD3_FRAC_SHIFT; in scg_apll_pfd_get_rate()
203 reg = readl(&scg1_regs->apllpfd); in scg_apll_pfd_get_rate()
204 if (reg & gate || !(reg & valid)) in scg_apll_pfd_get_rate()
207 clk_debug("scg_apll_pfd_get_rate reg 0x%x\n", reg); in scg_apll_pfd_get_rate()
209 val = (reg & mask) >> shift; in scg_apll_pfd_get_rate()
221 u32 reg, val, rate; in scg_spll_pfd_get_rate() local
222 u32 shift, mask, gate, valid; in scg_spll_pfd_get_rate() local
229 shift = SCG_PLL_PFD0_FRAC_SHIFT; in scg_spll_pfd_get_rate()
235 shift = SCG_PLL_PFD1_FRAC_SHIFT; in scg_spll_pfd_get_rate()
241 shift = SCG_PLL_PFD2_FRAC_SHIFT; in scg_spll_pfd_get_rate()
247 shift = SCG_PLL_PFD3_FRAC_SHIFT; in scg_spll_pfd_get_rate()
253 reg = readl(&scg1_regs->spllpfd); in scg_spll_pfd_get_rate()
254 if (reg & gate || !(reg & valid)) in scg_spll_pfd_get_rate()
257 clk_debug("scg_spll_pfd_get_rate reg 0x%x\n", reg); in scg_spll_pfd_get_rate()
259 val = (reg & mask) >> shift; in scg_spll_pfd_get_rate()
271 u32 reg, val, rate; in scg_apll_get_rate() local
273 reg = readl(&scg1_regs->apllcfg); in scg_apll_get_rate()
274 val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT; in scg_apll_get_rate()
280 val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >> in scg_apll_get_rate()
284 val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >> in scg_apll_get_rate()
289 val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >> in scg_apll_get_rate()
299 u32 reg, val, rate; in scg_spll_get_rate() local
301 reg = readl(&scg1_regs->spllcfg); in scg_spll_get_rate()
302 val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT; in scg_spll_get_rate()
304 clk_debug("scg_spll_get_rate reg 0x%x\n", reg); in scg_spll_get_rate()
310 val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >> in scg_spll_get_rate()
314 val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >> in scg_spll_get_rate()
322 val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >> in scg_spll_get_rate()
334 u32 reg, val, rate, div; in scg_ddr_get_rate() local
336 reg = readl(&scg1_regs->ddrccr); in scg_ddr_get_rate()
337 val = (reg & SCG_DDRCCR_DDRCS_MASK) >> SCG_DDRCCR_DDRCS_SHIFT; in scg_ddr_get_rate()
338 div = (reg & SCG_DDRCCR_DDRDIV_MASK) >> SCG_DDRCCR_DDRDIV_SHIFT; in scg_ddr_get_rate()
344 reg = readl(&scg1_regs->apllcfg); in scg_ddr_get_rate()
345 val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >> in scg_ddr_get_rate()
352 rate = rate / (1 << (div - 1)); in scg_ddr_get_rate()
358 u32 reg, val, rate; in scg_nic_get_rate() local
359 u32 shift, mask; in scg_nic_get_rate() local
361 reg = readl(&scg1_regs->niccsr); in scg_nic_get_rate()
362 val = (reg & SCG_NICCSR_NICCS_MASK) >> SCG_NICCSR_NICCS_SHIFT; in scg_nic_get_rate()
364 clk_debug("scg_nic_get_rate niccsr 0x%x\n", reg); in scg_nic_get_rate()
373 val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT; in scg_nic_get_rate()
384 shift = SCG_NICCSR_GPUDIV_SHIFT; in scg_nic_get_rate()
390 shift = SCG_NICCSR_NIC1DIV_SHIFT; in scg_nic_get_rate()
396 val = (reg & mask) >> shift; in scg_nic_get_rate()
407 shift = SCG_NICCSR_NIC1EXTDIV_SHIFT; in scg_nic_get_rate()
411 shift = SCG_NICCSR_NIC1BUSDIV_SHIFT; in scg_nic_get_rate()
417 val = (reg & mask) >> shift; in scg_nic_get_rate()
431 u32 reg, val, rate; in scg_sys_get_rate() local
436 reg = readl(&scg1_regs->csr); in scg_sys_get_rate()
437 val = (reg & SCG_CCR_SCS_MASK) >> SCG_CCR_SCS_SHIFT; in scg_sys_get_rate()
439 clk_debug("scg_sys_get_rate reg 0x%x\n", reg); in scg_sys_get_rate()
460 val = (reg & SCG_CCR_DIVCORE_MASK) >> SCG_CCR_DIVCORE_SHIFT; in scg_sys_get_rate()
465 val = (reg & SCG_CCR_DIVBUS_MASK) >> SCG_CCR_DIVBUS_SHIFT; in scg_sys_get_rate()
474 u32 reg, pre_div, infreq, mult; in decode_pll() local
483 reg = readl(&scg1_regs->spllcsr); in decode_pll()
485 if (!(reg & SCG_SPLL_CSR_SPLLVLD_MASK)) in decode_pll()
488 reg = readl(&scg1_regs->spllcfg); in decode_pll()
490 pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >> in decode_pll()
494 mult = (reg & SCG1_SPLL_CFG_MULT_MASK) >> in decode_pll()
497 infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >> in decode_pll()
504 num = readl(&scg1_regs->spllnum); in decode_pll()
505 denom = readl(&scg1_regs->splldenom); in decode_pll()
512 reg = readl(&scg1_regs->apllcsr); in decode_pll()
514 if (!(reg & SCG_APLL_CSR_APLLVLD_MASK)) in decode_pll()
517 reg = readl(&scg1_regs->apllcfg); in decode_pll()
519 pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >> in decode_pll()
523 mult = (reg & SCG_APLL_CFG_MULT_MASK) >> in decode_pll()
526 infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >> in decode_pll()
533 num = readl(&scg1_regs->apllnum); in decode_pll()
534 denom = readl(&scg1_regs->aplldenom); in decode_pll()
541 reg = readl(&scg1_regs->upllcsr); in decode_pll()
543 if (!(reg & SCG_UPLL_CSR_UPLLVLD_MASK)) in decode_pll()
620 u32 reg; in scg_enable_pll_pfd() local
621 u32 shift, mask, gate, valid; in scg_enable_pll_pfd() local
625 return -EINVAL; in scg_enable_pll_pfd()
633 shift = SCG_PLL_PFD0_FRAC_SHIFT; in scg_enable_pll_pfd()
636 addr = (u32)(&scg1_regs->spllpfd); in scg_enable_pll_pfd()
638 addr = (u32)(&scg1_regs->apllpfd); in scg_enable_pll_pfd()
645 shift = SCG_PLL_PFD1_FRAC_SHIFT; in scg_enable_pll_pfd()
648 addr = (u32)(&scg1_regs->spllpfd); in scg_enable_pll_pfd()
650 addr = (u32)(&scg1_regs->apllpfd); in scg_enable_pll_pfd()
657 shift = SCG_PLL_PFD2_FRAC_SHIFT; in scg_enable_pll_pfd()
660 addr = (u32)(&scg1_regs->spllpfd); in scg_enable_pll_pfd()
662 addr = (u32)(&scg1_regs->apllpfd); in scg_enable_pll_pfd()
669 shift = SCG_PLL_PFD3_FRAC_SHIFT; in scg_enable_pll_pfd()
672 addr = (u32)(&scg1_regs->spllpfd); in scg_enable_pll_pfd()
674 addr = (u32)(&scg1_regs->apllpfd); in scg_enable_pll_pfd()
677 return -EINVAL; in scg_enable_pll_pfd()
681 reg = readl(addr); in scg_enable_pll_pfd()
682 reg |= gate; in scg_enable_pll_pfd()
683 writel(reg, addr); in scg_enable_pll_pfd()
686 reg &= ~mask; in scg_enable_pll_pfd()
687 reg |= (frac << shift) & mask; in scg_enable_pll_pfd()
688 writel(reg, addr); in scg_enable_pll_pfd()
691 * Un-gate the PFD in scg_enable_pll_pfd()
692 * (Need un-gate before checking valid, not align with RM) in scg_enable_pll_pfd()
694 reg &= ~gate; in scg_enable_pll_pfd()
695 writel(reg, addr); in scg_enable_pll_pfd()
699 reg = readl(addr); in scg_enable_pll_pfd()
700 } while (!(reg & valid)); in scg_enable_pll_pfd()
710 u32 reg; in scg_enable_usb_pll() local
717 return -EPERM; in scg_enable_usb_pll()
719 reg = readl(SIM0_RBASE + 0x3C); in scg_enable_usb_pll()
721 reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK; in scg_enable_usb_pll()
723 reg |= SIM_MISC_CTRL0_USB_PLL_EN_MASK; in scg_enable_usb_pll()
724 writel(reg, SIM0_RBASE + 0x3C); in scg_enable_usb_pll()
726 if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) { in scg_enable_usb_pll()
727 writel(0x1c00000, &usbphy->usb1_pll_480_ctrl_clr); in scg_enable_usb_pll()
731 writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set); in scg_enable_usb_pll()
735 writel(0x800000, &usbphy->usb1_pll_480_ctrl_set); in scg_enable_usb_pll()
739 writel(0x1400000, &usbphy->usb1_pll_480_ctrl_set); in scg_enable_usb_pll()
743 writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set); in scg_enable_usb_pll()
749 &usbphy->usb1_pll_480_ctrl_set); in scg_enable_usb_pll()
755 writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set); in scg_enable_usb_pll()
758 while (timeout--) { in scg_enable_usb_pll()
759 if (readl(&usbphy->usb1_pll_480_ctrl) & in scg_enable_usb_pll()
767 &usbphy->usb1_pll_480_ctrl_clr); in scg_enable_usb_pll()
768 return -ETIME; in scg_enable_usb_pll()
773 writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr); in scg_enable_usb_pll()
777 &usbphy->usb1_pll_480_ctrl_set); in scg_enable_usb_pll()
780 while (timeout--) { in scg_enable_usb_pll()
781 if (readl(&scg1_regs->upllcsr) & in scg_enable_usb_pll()
787 reg = readl(SIM0_RBASE + 0x3C); in scg_enable_usb_pll()
788 reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK; in scg_enable_usb_pll()
789 writel(reg, SIM0_RBASE + 0x3C); in scg_enable_usb_pll()
790 return -ETIME; in scg_enable_usb_pll()
813 rccr_reg_val = readl(&scg1_regs->rccr); in scg_a7_rccr_init()
818 writel(rccr_reg_val, &scg1_regs->rccr); in scg_a7_rccr_init()
855 val = readl(&scg1_regs->spllcsr); in scg_a7_spll_init()
857 writel(val, &scg1_regs->spllcsr); in scg_a7_spll_init()
869 val = readl(&scg1_regs->spllpfd); in scg_a7_spll_init()
874 writel(val, &scg1_regs->spllpfd); in scg_a7_spll_init()
879 writel(SCG1_SPLL_CFG_NUM_24M_OSC, &scg1_regs->spllcfg); in scg_a7_spll_init()
882 val = readl(&scg1_regs->spllcsr); in scg_a7_spll_init()
884 writel(val, &scg1_regs->spllcsr); in scg_a7_spll_init()
887 while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK)) in scg_a7_spll_init()
891 val = readl(&scg1_regs->spllpfd); in scg_a7_spll_init()
894 writel(val, &scg1_regs->spllpfd); in scg_a7_spll_init()
896 /* Un-gate A7 SPLL PFD0 */ in scg_a7_spll_init()
897 val = readl(&scg1_regs->spllpfd); in scg_a7_spll_init()
899 writel(val, &scg1_regs->spllpfd); in scg_a7_spll_init()
902 while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK)) in scg_a7_spll_init()
920 writel(SCG1_DDRCCR_CFG_NUM, &scg1_regs->ddrccr); in scg_a7_ddrclk_init()
964 val = readl(&scg1_regs->apllcsr); in scg_a7_apll_init()
966 writel(val, &scg1_regs->apllcsr); in scg_a7_apll_init()
969 val = readl(&scg1_regs->apllpfd); in scg_a7_apll_init()
971 writel(val, &scg1_regs->apllpfd); in scg_a7_apll_init()
975 writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg); in scg_a7_apll_init()
978 val = readl(&scg1_regs->apllcsr); in scg_a7_apll_init()
980 writel(val, &scg1_regs->apllcsr); in scg_a7_apll_init()
983 while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK)) in scg_a7_apll_init()
987 val = readl(&scg1_regs->apllpfd); in scg_a7_apll_init()
990 writel(val, &scg1_regs->apllpfd); in scg_a7_apll_init()
992 /* Un-gate A7 APLL PFD0 */ in scg_a7_apll_init()
993 val = readl(&scg1_regs->apllpfd); in scg_a7_apll_init()
995 writel(val, &scg1_regs->apllpfd); in scg_a7_apll_init()
998 while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK)) in scg_a7_apll_init()
1013 while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK)) in scg_a7_firc_init()
1019 SCG1_FIRCDIV_DIV1_NUM), &scg1_regs->fircdiv); in scg_a7_firc_init()
1041 writel(SCG1_NICCCR_CFG_NUM, &scg1_regs->nicccr); in scg_a7_nicclk_init()
1055 while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK)) in scg_a7_soscdiv_init()
1060 SCG1_SOSCDIV_DIV1_NUM), &scg1_regs->soscdiv); in scg_a7_soscdiv_init()
1078 rccr_reg_val = readl(&scg1_regs->rccr); in scg_a7_sys_clk_sel()
1081 writel(rccr_reg_val, &scg1_regs->rccr); in scg_a7_sys_clk_sel()
1086 debug("SCG Version: 0x%x\n", readl(&scg1_regs->verid)); in scg_a7_info()
1087 debug("SCG Parameter: 0x%x\n", readl(&scg1_regs->param)); in scg_a7_info()
1088 debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr)); in scg_a7_info()
1089 debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr)); in scg_a7_info()