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/OK3568_Linux_fs/kernel/drivers/i2c/muxes/
H A Di2c-mux-reg.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/i2c-mux.h>
15 #include <linux/platform_data/i2c-mux-reg.h>
23 static int i2c_mux_reg_set(const struct regmux *mux, unsigned int chan_id) in i2c_mux_reg_set() argument
25 if (!mux->data.reg) in i2c_mux_reg_set()
26 return -EINVAL; in i2c_mux_reg_set()
34 switch (mux->data.reg_size) { in i2c_mux_reg_set()
36 if (mux->data.little_endian) in i2c_mux_reg_set()
37 iowrite32(chan_id, mux->data.reg); in i2c_mux_reg_set()
39 iowrite32be(chan_id, mux->data.reg); in i2c_mux_reg_set()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mux/
H A Dreg-mux.txt1 Generic register bitfield-based multiplexer controller bindings
7 - compatible : should be one of
8 "reg-mux" : if parent device of mux controller is not syscon device
9 "mmio-mux" : if parent device of mux controller is syscon device
10 - #mux-control-cells : <1>
11 - mux-reg-masks : an array of register offset and pre-shifted bitfield mask
12 pairs, each describing a single mux control.
13 * Standard mux-controller bindings as decribed in mux-controller.txt
16 - idle-states : if present, the state the muxes will have when idle. The
21 pair in the mux-reg-masks array.
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-mux.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
10 #include <linux/clk-provider.h>
20 * prepare - clk_prepare only ensures that parents are prepared
21 * enable - clk_enable only ensures that parents are enabled
22 * rate - rate is only affected by parent switching. No clk_set_rate support
23 * parent - parent is adjustable through clk_set_parent
26 static inline u32 clk_mux_readl(struct clk_mux *mux) in clk_mux_readl() argument
28 if (mux->flags & CLK_MUX_BIG_ENDIAN) in clk_mux_readl()
29 return ioread32be(mux->reg); in clk_mux_readl()
[all …]
/OK3568_Linux_fs/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3568.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include "pinctrl-rockchip.h"
15 …MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection …
16 …MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection …
17 …MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection …
18 …MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection …
19 …MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection …
20 …MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection …
21 …MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux sel…
22 …MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux sel…
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/ti/
H A Dmux.c6 * Tero Kristo <t-kristo@ti.com>
18 #include <linux/clk-provider.h>
31 struct clk_omap_mux *mux = to_clk_omap_mux(hw); in ti_clk_mux_get_parent() local
36 * FIXME need a mux-specific flag to determine if val is bitwise or in ti_clk_mux_get_parent()
42 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift; in ti_clk_mux_get_parent()
43 val &= mux->mask; in ti_clk_mux_get_parent()
45 if (mux->table) { in ti_clk_mux_get_parent()
49 if (mux->table[i] == val) in ti_clk_mux_get_parent()
51 return -EINVAL; in ti_clk_mux_get_parent()
54 if (val && (mux->flags & CLK_MUX_INDEX_BIT)) in ti_clk_mux_get_parent()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amlogic/
H A Dmeson-axg.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
[all …]
H A Dmeson-g12-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
H A Dmeson-gxl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
18 compatible = "amlogic,meson-gxl-usb-ctrl";
19 reg = <0x0 0xd0078080 0x0 0x20>;
21 #address-cells = <2>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dmdio-mux-multiplexer.txt3 This is a special case of MDIO mux when MDIO mux is defined as a consumer
4 of a mux producer device. The mux producer can be of any type like mmio mux
5 producer, gpio mux producer or generic register based mux producer.
9 - compatible : should be "mmio-mux-multiplexer"
10 - mux-controls : mux controller node to use for operating the mux
11 - mdio-parent-bus : phandle to the parent MDIO bus.
17 Documentation/devicetree/bindings/mux/mux-controller.txt
18 and Documentation/devicetree/bindings/net/mdio-mux.txt
21 In below example the Mux producer and consumer are separate nodes.
25 compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dmmp3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/marvell,mmp2.h>
7 #include <dt-bindings/power/marvell,mmp2.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 enable-method = "marvell,mmp3-smp";
22 next-level-cache = <&l2>;
[all …]
H A Dat91-natte.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * at91-natte.dts - Device Tree include file for the Natte board
11 mux: mux-controller { label
12 compatible = "gpio-mux";
13 #mux-control-cells = <0>;
15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
20 batntc-mux {
21 compatible = "io-channel-mux";
22 io-channels = <&adc 5>;
23 io-channel-names = "parent";
[all …]
H A Dmmp2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <1>;
26 compatible = "simple-bus";
27 interrupt-parent = <&intc>;
30 L2: l2-cache {
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-composite-8m.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
56 int ret = -EINVAL; in imx8m_clk_composite_compute_dividers()
63 int new_error = ((parent_rate / div1) / div2) - rate; in imx8m_clk_composite_compute_dividers()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-factors.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Adjustable factor-based clock implementation
8 #include <linux/clk-provider.h>
16 #include "clk-factors.h"
19 * DOC: basic adjustable factor-based clock
22 * prepare - clk_prepare only ensures that parents are prepared
23 * enable - clk_enable only ensures that parents are enabled
24 * rate - rate is adjustable.
25 * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
26 * parent - fixed parent. No clk_set_parent support
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sprd/
H A Dmux.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
12 #include "mux.h"
15 const struct sprd_mux_ssel *mux) in sprd_mux_helper_get_parent() argument
17 unsigned int reg; in sprd_mux_helper_get_parent() local
22 regmap_read(common->regmap, common->reg, &reg); in sprd_mux_helper_get_parent()
23 parent = reg >> mux->shift; in sprd_mux_helper_get_parent()
24 parent &= (1 << mux->width) - 1; in sprd_mux_helper_get_parent()
26 if (!mux->table) in sprd_mux_helper_get_parent()
29 num_parents = clk_hw_get_num_parents(&common->hw); in sprd_mux_helper_get_parent()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/x86/
H A Dclk-cgu.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
11 #include "clk-cgu.h"
13 #define GATE_HW_REG_STAT(reg) ((reg) + 0x0) argument
14 #define GATE_HW_REG_EN(reg) ((reg) + 0x4) argument
15 #define GATE_HW_REG_DIS(reg) ((reg) + 0x8) argument
29 if (list->div_flags & CLOCK_FLAG_VAL_INIT) { in lgm_clk_register_fixed()
30 spin_lock_irqsave(&ctx->lock, flags); in lgm_clk_register_fixed()
31 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
32 list->div_width, list->div_val); in lgm_clk_register_fixed()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-super.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
28 #define super_state_to_src_shift(m, s) ((m->width * s))
29 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
36 struct tegra_clk_super_mux *mux = to_clk_super_mux(hw); in clk_super_get_parent() local
40 val = readl_relaxed(mux->reg); in clk_super_get_parent()
47 super_state_to_src_shift(mux, SUPER_STATE_IDLE) : in clk_super_get_parent()
48 super_state_to_src_shift(mux, SUPER_STATE_RUN); in clk_super_get_parent()
50 source = (val >> shift) & super_state_to_src_mask(mux); in clk_super_get_parent()
56 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && in clk_super_get_parent()
[all …]
/OK3568_Linux_fs/kernel/drivers/mux/
H A Dmmio.c1 // SPDX-License-Identifier: GPL-2.0
3 * MMIO register bitfield-controlled multiplexer driver
12 #include <linux/mux/driver.h>
18 static int mux_mmio_set(struct mux_control *mux, int state) in mux_mmio_set() argument
20 struct regmap_field **fields = mux_chip_priv(mux->chip); in mux_mmio_set()
22 return regmap_field_write(fields[mux_control_get_index(mux)], state); in mux_mmio_set()
30 { .compatible = "mmio-mux", },
31 { .compatible = "reg-mux", },
38 struct device *dev = &pdev->dev; in mux_mmio_probe()
39 struct device_node *np = dev->of_node; in mux_mmio_probe()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-muxgrf.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 u32 reg; member
23 struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw); in rockchip_muxgrf_get_parent() local
24 unsigned int mask = GENMASK(mux->width - 1, 0); in rockchip_muxgrf_get_parent()
27 regmap_read(mux->regmap, mux->reg, &val); in rockchip_muxgrf_get_parent()
29 val >>= mux->shift; in rockchip_muxgrf_get_parent()
37 struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw); in rockchip_muxgrf_set_parent() local
38 unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); in rockchip_muxgrf_set_parent()
42 val <<= mux->shift; in rockchip_muxgrf_set_parent()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-regmap-mux.c4 * Base on code in drivers/clk/clk-mux.c.
5 * See clk-mux.c for further copyright information.
18 #include "clk-regmap.h"
24 struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); in clk_regmap_mux_get_parent() local
28 regmap_read(mux->regmap, mux->reg, &val); in clk_regmap_mux_get_parent()
30 index = val >> mux->shift; in clk_regmap_mux_get_parent()
31 index &= mux->mask; in clk_regmap_mux_get_parent()
38 struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); in clk_regmap_mux_set_parent() local
40 return regmap_write(mux->regmap, mux->reg, (index << mux->shift) | in clk_regmap_mux_set_parent()
41 (mux->mask << (mux->shift + 16))); in clk_regmap_mux_set_parent()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Ddra7xx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "ti,dra7-atl-clock";
18 #clock-cells = <0>;
19 compatible = "ti,dra7-atl-clock";
24 #clock-cells = <0>;
25 compatible = "ti,dra7-atl-clock";
30 #clock-cells = <0>;
31 compatible = "ti,dra7-atl-clock";
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
[all …]
H A Dmeson-gxbb.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "meson-gx.dtsi"
44 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
45 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
46 #include <dt-bindings/clock/gxbb-clkc.h>
47 #include <dt-bindings/clock/gxbb-aoclkc.h>
48 #include <dt-bindings/reset/gxbb-aoclkc.h>
51 compatible = "amlogic,meson-gxbb";
55 compatible = "amlogic,meson-gxbb-usb2-phy";
56 #phy-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/uniphier/
H A Dclk-uniphier-mux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
11 #include "clk-uniphier.h"
16 unsigned int reg; member
25 struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw); in uniphier_clk_mux_set_parent() local
27 return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index], in uniphier_clk_mux_set_parent()
28 mux->vals[index]); in uniphier_clk_mux_set_parent()
33 struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw); in uniphier_clk_mux_get_parent() local
39 ret = regmap_read(mux->regmap, mux->reg, &val); in uniphier_clk_mux_get_parent()
44 if ((mux->masks[i] & val) == mux->vals[i]) in uniphier_clk_mux_get_parent()
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dwm9713.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm9713.c -- ALSA Soc WM9713 codec support
5 * Copyright 2006-10 Wolfson Microelectronics PLC.
8 * Features:-
71 SOC_ENUM_SINGLE(AC97_VIDEO, 14, 4, wm9713_rec_mux), /* record mux hp 1 */
72 SOC_ENUM_SINGLE(AC97_VIDEO, 9, 4, wm9713_rec_mux), /* record mux mono 2 */
73 SOC_ENUM_SINGLE(AC97_VIDEO, 3, 8, wm9713_rec_src), /* record mux left 3 */
74 SOC_ENUM_SINGLE(AC97_VIDEO, 0, 8, wm9713_rec_src), /* record mux right 4*/
92 static const DECLARE_TLV_DB_SCALE(out_tlv, -4650, 150, 0);
93 static const DECLARE_TLV_DB_SCALE(main_tlv, -3450, 150, 0);
[all …]
H A Dtas5086.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * - implement DAPM and input muxing
9 * - implement modulation limit
10 * - implement non-default PWM start
13 * because the registers are of unequal size, and multi-byte registers
18 * it doesn't matter because the entire map can be accessed as 8-bit
21 * routines have to be open-coded.
71 #define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */
89 * Default TAS5086 power-up configuration
123 static int tas5086_register_size(struct device *dev, unsigned int reg) in tas5086_register_size() argument
[all …]

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