xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mux/reg-mux.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunGeneric register bitfield-based multiplexer controller bindings
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunDefine register bitfields to be used to control multiplexers. The parent
4*4882a593Smuzhiyundevice tree node must be a device node to provide register r/w access.
5*4882a593Smuzhiyun
6*4882a593SmuzhiyunRequired properties:
7*4882a593Smuzhiyun- compatible : should be one of
8*4882a593Smuzhiyun	"reg-mux" : if parent device of mux controller is not syscon device
9*4882a593Smuzhiyun	"mmio-mux" : if parent device of mux controller is syscon device
10*4882a593Smuzhiyun- #mux-control-cells : <1>
11*4882a593Smuzhiyun- mux-reg-masks : an array of register offset and pre-shifted bitfield mask
12*4882a593Smuzhiyun                  pairs, each describing a single mux control.
13*4882a593Smuzhiyun* Standard mux-controller bindings as decribed in mux-controller.txt
14*4882a593Smuzhiyun
15*4882a593SmuzhiyunOptional properties:
16*4882a593Smuzhiyun- idle-states : if present, the state the muxes will have when idle. The
17*4882a593Smuzhiyun		special state MUX_IDLE_AS_IS is the default.
18*4882a593Smuzhiyun
19*4882a593SmuzhiyunThe multiplexer state of each multiplexer is defined as the value of the
20*4882a593Smuzhiyunbitfield described by the corresponding register offset and bitfield mask
21*4882a593Smuzhiyunpair in the mux-reg-masks array.
22*4882a593Smuzhiyun
23*4882a593SmuzhiyunExample 1:
24*4882a593SmuzhiyunThe parent device of mux controller is not a syscon device.
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun&i2c0 {
27*4882a593Smuzhiyun	fpga@66 { // fpga connected to i2c
28*4882a593Smuzhiyun		compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
29*4882a593Smuzhiyun			     "simple-mfd";
30*4882a593Smuzhiyun		reg = <0x66>;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun		mux: mux-controller {
33*4882a593Smuzhiyun			compatible = "reg-mux";
34*4882a593Smuzhiyun			#mux-control-cells = <1>;
35*4882a593Smuzhiyun			mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
36*4882a593Smuzhiyun					<0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
37*4882a593Smuzhiyun		};
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyunmdio-mux-1 {
42*4882a593Smuzhiyun	compatible = "mdio-mux-multiplexer";
43*4882a593Smuzhiyun	mux-controls = <&mux 0>;
44*4882a593Smuzhiyun	mdio-parent-bus = <&emdio1>;
45*4882a593Smuzhiyun	#address-cells = <1>;
46*4882a593Smuzhiyun	#size-cells = <0>;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun	mdio@0 {
49*4882a593Smuzhiyun		reg = <0x0>;
50*4882a593Smuzhiyun		#address-cells = <1>;
51*4882a593Smuzhiyun		#size-cells = <0>;
52*4882a593Smuzhiyun	};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun	mdio@8 {
55*4882a593Smuzhiyun		reg = <0x8>;
56*4882a593Smuzhiyun		#address-cells = <1>;
57*4882a593Smuzhiyun		#size-cells = <0>;
58*4882a593Smuzhiyun	};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun	..
61*4882a593Smuzhiyun	..
62*4882a593Smuzhiyun};
63*4882a593Smuzhiyun
64*4882a593Smuzhiyunmdio-mux-2 {
65*4882a593Smuzhiyun	compatible = "mdio-mux-multiplexer";
66*4882a593Smuzhiyun	mux-controls = <&mux 1>;
67*4882a593Smuzhiyun	mdio-parent-bus = <&emdio2>;
68*4882a593Smuzhiyun	#address-cells = <1>;
69*4882a593Smuzhiyun	#size-cells = <0>;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	mdio@0 {
72*4882a593Smuzhiyun		reg = <0x0>;
73*4882a593Smuzhiyun		#address-cells = <1>;
74*4882a593Smuzhiyun		#size-cells = <0>;
75*4882a593Smuzhiyun	};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun	mdio@1 {
78*4882a593Smuzhiyun		reg = <0x1>;
79*4882a593Smuzhiyun		#address-cells = <1>;
80*4882a593Smuzhiyun		#size-cells = <0>;
81*4882a593Smuzhiyun	};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun	..
84*4882a593Smuzhiyun	..
85*4882a593Smuzhiyun};
86*4882a593Smuzhiyun
87*4882a593SmuzhiyunExample 2:
88*4882a593SmuzhiyunThe parent device of mux controller is syscon device.
89*4882a593Smuzhiyun
90*4882a593Smuzhiyunsyscon {
91*4882a593Smuzhiyun	compatible = "syscon";
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun	mux: mux-controller {
94*4882a593Smuzhiyun		compatible = "mmio-mux";
95*4882a593Smuzhiyun		#mux-control-cells = <1>;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun		mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
98*4882a593Smuzhiyun				<0x3 0x40>, /* 1: reg 0x3, bit 6 */
99*4882a593Smuzhiyun		idle-states = <MUX_IDLE_AS_IS>, <0>;
100*4882a593Smuzhiyun	};
101*4882a593Smuzhiyun};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyunvideo-mux {
104*4882a593Smuzhiyun	compatible = "video-mux";
105*4882a593Smuzhiyun	mux-controls = <&mux 0>;
106*4882a593Smuzhiyun	#address-cells = <1>;
107*4882a593Smuzhiyun	#size-cells = <0>;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun	ports {
110*4882a593Smuzhiyun		/* inputs 0..3 */
111*4882a593Smuzhiyun		port@0 {
112*4882a593Smuzhiyun			reg = <0>;
113*4882a593Smuzhiyun		};
114*4882a593Smuzhiyun		port@1 {
115*4882a593Smuzhiyun			reg = <1>;
116*4882a593Smuzhiyun		};
117*4882a593Smuzhiyun		port@2 {
118*4882a593Smuzhiyun			reg = <2>;
119*4882a593Smuzhiyun		};
120*4882a593Smuzhiyun		port@3 {
121*4882a593Smuzhiyun			reg = <3>;
122*4882a593Smuzhiyun		};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun		/* output */
125*4882a593Smuzhiyun		port@4 {
126*4882a593Smuzhiyun			reg = <4>;
127*4882a593Smuzhiyun		};
128*4882a593Smuzhiyun	};
129*4882a593Smuzhiyun};
130