1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * MMIO register bitfield-controlled multiplexer driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2017 Pengutronix, Philipp Zabel <kernel@pengutronix.de>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/bitops.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/mux/driver.h>
13*4882a593Smuzhiyun #include <linux/of_platform.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/property.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun
mux_mmio_set(struct mux_control * mux,int state)18*4882a593Smuzhiyun static int mux_mmio_set(struct mux_control *mux, int state)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun struct regmap_field **fields = mux_chip_priv(mux->chip);
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun return regmap_field_write(fields[mux_control_get_index(mux)], state);
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static const struct mux_control_ops mux_mmio_ops = {
26*4882a593Smuzhiyun .set = mux_mmio_set,
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static const struct of_device_id mux_mmio_dt_ids[] = {
30*4882a593Smuzhiyun { .compatible = "mmio-mux", },
31*4882a593Smuzhiyun { .compatible = "reg-mux", },
32*4882a593Smuzhiyun { /* sentinel */ }
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mux_mmio_dt_ids);
35*4882a593Smuzhiyun
mux_mmio_probe(struct platform_device * pdev)36*4882a593Smuzhiyun static int mux_mmio_probe(struct platform_device *pdev)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun struct device *dev = &pdev->dev;
39*4882a593Smuzhiyun struct device_node *np = dev->of_node;
40*4882a593Smuzhiyun struct regmap_field **fields;
41*4882a593Smuzhiyun struct mux_chip *mux_chip;
42*4882a593Smuzhiyun struct regmap *regmap;
43*4882a593Smuzhiyun int num_fields;
44*4882a593Smuzhiyun int ret;
45*4882a593Smuzhiyun int i;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun if (of_device_is_compatible(np, "mmio-mux"))
48*4882a593Smuzhiyun regmap = syscon_node_to_regmap(np->parent);
49*4882a593Smuzhiyun else
50*4882a593Smuzhiyun regmap = dev_get_regmap(dev->parent, NULL) ?: ERR_PTR(-ENODEV);
51*4882a593Smuzhiyun if (IS_ERR(regmap)) {
52*4882a593Smuzhiyun ret = PTR_ERR(regmap);
53*4882a593Smuzhiyun dev_err(dev, "failed to get regmap: %d\n", ret);
54*4882a593Smuzhiyun return ret;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun ret = of_property_count_u32_elems(np, "mux-reg-masks");
58*4882a593Smuzhiyun if (ret == 0 || ret % 2)
59*4882a593Smuzhiyun ret = -EINVAL;
60*4882a593Smuzhiyun if (ret < 0) {
61*4882a593Smuzhiyun dev_err(dev, "mux-reg-masks property missing or invalid: %d\n",
62*4882a593Smuzhiyun ret);
63*4882a593Smuzhiyun return ret;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun num_fields = ret / 2;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun mux_chip = devm_mux_chip_alloc(dev, num_fields, num_fields *
68*4882a593Smuzhiyun sizeof(*fields));
69*4882a593Smuzhiyun if (IS_ERR(mux_chip))
70*4882a593Smuzhiyun return PTR_ERR(mux_chip);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun fields = mux_chip_priv(mux_chip);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun for (i = 0; i < num_fields; i++) {
75*4882a593Smuzhiyun struct mux_control *mux = &mux_chip->mux[i];
76*4882a593Smuzhiyun struct reg_field field;
77*4882a593Smuzhiyun s32 idle_state = MUX_IDLE_AS_IS;
78*4882a593Smuzhiyun u32 reg, mask;
79*4882a593Smuzhiyun int bits;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun ret = of_property_read_u32_index(np, "mux-reg-masks",
82*4882a593Smuzhiyun 2 * i, ®);
83*4882a593Smuzhiyun if (!ret)
84*4882a593Smuzhiyun ret = of_property_read_u32_index(np, "mux-reg-masks",
85*4882a593Smuzhiyun 2 * i + 1, &mask);
86*4882a593Smuzhiyun if (ret < 0) {
87*4882a593Smuzhiyun dev_err(dev, "bitfield %d: failed to read mux-reg-masks property: %d\n",
88*4882a593Smuzhiyun i, ret);
89*4882a593Smuzhiyun return ret;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun field.reg = reg;
93*4882a593Smuzhiyun field.msb = fls(mask) - 1;
94*4882a593Smuzhiyun field.lsb = ffs(mask) - 1;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun if (mask != GENMASK(field.msb, field.lsb)) {
97*4882a593Smuzhiyun dev_err(dev, "bitfield %d: invalid mask 0x%x\n",
98*4882a593Smuzhiyun i, mask);
99*4882a593Smuzhiyun return -EINVAL;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun fields[i] = devm_regmap_field_alloc(dev, regmap, field);
103*4882a593Smuzhiyun if (IS_ERR(fields[i])) {
104*4882a593Smuzhiyun ret = PTR_ERR(fields[i]);
105*4882a593Smuzhiyun dev_err(dev, "bitfield %d: failed allocate: %d\n",
106*4882a593Smuzhiyun i, ret);
107*4882a593Smuzhiyun return ret;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun bits = 1 + field.msb - field.lsb;
111*4882a593Smuzhiyun mux->states = 1 << bits;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun of_property_read_u32_index(np, "idle-states", i,
114*4882a593Smuzhiyun (u32 *)&idle_state);
115*4882a593Smuzhiyun if (idle_state != MUX_IDLE_AS_IS) {
116*4882a593Smuzhiyun if (idle_state < 0 || idle_state >= mux->states) {
117*4882a593Smuzhiyun dev_err(dev, "bitfield: %d: out of range idle state %d\n",
118*4882a593Smuzhiyun i, idle_state);
119*4882a593Smuzhiyun return -EINVAL;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun mux->idle_state = idle_state;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun mux_chip->ops = &mux_mmio_ops;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun return devm_mux_chip_register(dev, mux_chip);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun static struct platform_driver mux_mmio_driver = {
132*4882a593Smuzhiyun .driver = {
133*4882a593Smuzhiyun .name = "mmio-mux",
134*4882a593Smuzhiyun .of_match_table = of_match_ptr(mux_mmio_dt_ids),
135*4882a593Smuzhiyun },
136*4882a593Smuzhiyun .probe = mux_mmio_probe,
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun module_platform_driver(mux_mmio_driver);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun MODULE_DESCRIPTION("MMIO register bitfield-controlled multiplexer driver");
141*4882a593Smuzhiyun MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
142*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
143