1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun #include <linux/slab.h>
4*4882a593Smuzhiyun #include <linux/bitops.h>
5*4882a593Smuzhiyun #include <linux/regmap.h>
6*4882a593Smuzhiyun #include <linux/clk.h>
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include "clk.h"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun struct rockchip_muxgrf_clock {
11*4882a593Smuzhiyun struct clk_hw hw;
12*4882a593Smuzhiyun struct regmap *regmap;
13*4882a593Smuzhiyun u32 reg;
14*4882a593Smuzhiyun u32 shift;
15*4882a593Smuzhiyun u32 width;
16*4882a593Smuzhiyun int flags;
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define to_muxgrf_clock(_hw) container_of(_hw, struct rockchip_muxgrf_clock, hw)
20*4882a593Smuzhiyun
rockchip_muxgrf_get_parent(struct clk_hw * hw)21*4882a593Smuzhiyun static u8 rockchip_muxgrf_get_parent(struct clk_hw *hw)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw);
24*4882a593Smuzhiyun unsigned int mask = GENMASK(mux->width - 1, 0);
25*4882a593Smuzhiyun unsigned int val;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun regmap_read(mux->regmap, mux->reg, &val);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun val >>= mux->shift;
30*4882a593Smuzhiyun val &= mask;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun return val;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
rockchip_muxgrf_set_parent(struct clk_hw * hw,u8 index)35*4882a593Smuzhiyun static int rockchip_muxgrf_set_parent(struct clk_hw *hw, u8 index)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw);
38*4882a593Smuzhiyun unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
39*4882a593Smuzhiyun unsigned int val;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun val = index;
42*4882a593Smuzhiyun val <<= mux->shift;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun if (mux->flags & CLK_MUX_HIWORD_MASK)
45*4882a593Smuzhiyun return regmap_write(mux->regmap, mux->reg, val | (mask << 16));
46*4882a593Smuzhiyun else
47*4882a593Smuzhiyun return regmap_update_bits(mux->regmap, mux->reg, mask, val);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static const struct clk_ops rockchip_muxgrf_clk_ops = {
51*4882a593Smuzhiyun .get_parent = rockchip_muxgrf_get_parent,
52*4882a593Smuzhiyun .set_parent = rockchip_muxgrf_set_parent,
53*4882a593Smuzhiyun .determine_rate = __clk_mux_determine_rate,
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
rockchip_clk_register_muxgrf(const char * name,const char * const * parent_names,u8 num_parents,int flags,struct regmap * regmap,int reg,int shift,int width,int mux_flags)56*4882a593Smuzhiyun struct clk *rockchip_clk_register_muxgrf(const char *name,
57*4882a593Smuzhiyun const char *const *parent_names, u8 num_parents,
58*4882a593Smuzhiyun int flags, struct regmap *regmap, int reg,
59*4882a593Smuzhiyun int shift, int width, int mux_flags)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun struct rockchip_muxgrf_clock *muxgrf_clock;
62*4882a593Smuzhiyun struct clk_init_data init;
63*4882a593Smuzhiyun struct clk *clk;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun if (IS_ERR(regmap)) {
66*4882a593Smuzhiyun pr_err("%s: regmap not available\n", __func__);
67*4882a593Smuzhiyun return ERR_PTR(-ENOTSUPP);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun muxgrf_clock = kmalloc(sizeof(*muxgrf_clock), GFP_KERNEL);
71*4882a593Smuzhiyun if (!muxgrf_clock)
72*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun init.name = name;
75*4882a593Smuzhiyun init.flags = flags;
76*4882a593Smuzhiyun init.num_parents = num_parents;
77*4882a593Smuzhiyun init.parent_names = parent_names;
78*4882a593Smuzhiyun init.ops = &rockchip_muxgrf_clk_ops;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun muxgrf_clock->hw.init = &init;
81*4882a593Smuzhiyun muxgrf_clock->regmap = regmap;
82*4882a593Smuzhiyun muxgrf_clock->reg = reg;
83*4882a593Smuzhiyun muxgrf_clock->shift = shift;
84*4882a593Smuzhiyun muxgrf_clock->width = width;
85*4882a593Smuzhiyun muxgrf_clock->flags = mux_flags;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun clk = clk_register(NULL, &muxgrf_clock->hw);
88*4882a593Smuzhiyun if (IS_ERR(clk))
89*4882a593Smuzhiyun kfree(muxgrf_clock);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return clk;
92*4882a593Smuzhiyun }
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