1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Spreadtrum multiplexer clock driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2017 Spreadtrum, Inc.
6*4882a593Smuzhiyun // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/clk.h>
9*4882a593Smuzhiyun #include <linux/clk-provider.h>
10*4882a593Smuzhiyun #include <linux/regmap.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "mux.h"
13*4882a593Smuzhiyun
sprd_mux_helper_get_parent(const struct sprd_clk_common * common,const struct sprd_mux_ssel * mux)14*4882a593Smuzhiyun u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,
15*4882a593Smuzhiyun const struct sprd_mux_ssel *mux)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun unsigned int reg;
18*4882a593Smuzhiyun u8 parent;
19*4882a593Smuzhiyun int num_parents;
20*4882a593Smuzhiyun int i;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun regmap_read(common->regmap, common->reg, ®);
23*4882a593Smuzhiyun parent = reg >> mux->shift;
24*4882a593Smuzhiyun parent &= (1 << mux->width) - 1;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun if (!mux->table)
27*4882a593Smuzhiyun return parent;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun num_parents = clk_hw_get_num_parents(&common->hw);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun for (i = 0; i < num_parents - 1; i++)
32*4882a593Smuzhiyun if (parent >= mux->table[i] && parent < mux->table[i + 1])
33*4882a593Smuzhiyun return i;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return num_parents - 1;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(sprd_mux_helper_get_parent);
38*4882a593Smuzhiyun
sprd_mux_get_parent(struct clk_hw * hw)39*4882a593Smuzhiyun static u8 sprd_mux_get_parent(struct clk_hw *hw)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun struct sprd_mux *cm = hw_to_sprd_mux(hw);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return sprd_mux_helper_get_parent(&cm->common, &cm->mux);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
sprd_mux_helper_set_parent(const struct sprd_clk_common * common,const struct sprd_mux_ssel * mux,u8 index)46*4882a593Smuzhiyun int sprd_mux_helper_set_parent(const struct sprd_clk_common *common,
47*4882a593Smuzhiyun const struct sprd_mux_ssel *mux,
48*4882a593Smuzhiyun u8 index)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun unsigned int reg;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun if (mux->table)
53*4882a593Smuzhiyun index = mux->table[index];
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun regmap_read(common->regmap, common->reg, ®);
56*4882a593Smuzhiyun reg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift);
57*4882a593Smuzhiyun regmap_write(common->regmap, common->reg,
58*4882a593Smuzhiyun reg | (index << mux->shift));
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun return 0;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(sprd_mux_helper_set_parent);
63*4882a593Smuzhiyun
sprd_mux_set_parent(struct clk_hw * hw,u8 index)64*4882a593Smuzhiyun static int sprd_mux_set_parent(struct clk_hw *hw, u8 index)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct sprd_mux *cm = hw_to_sprd_mux(hw);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return sprd_mux_helper_set_parent(&cm->common, &cm->mux, index);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun const struct clk_ops sprd_mux_ops = {
72*4882a593Smuzhiyun .get_parent = sprd_mux_get_parent,
73*4882a593Smuzhiyun .set_parent = sprd_mux_set_parent,
74*4882a593Smuzhiyun .determine_rate = __clk_mux_determine_rate,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(sprd_mux_ops);
77