Lines Matching +full:reg +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/marvell,mmp2.h>
7 #include <dt-bindings/power/marvell,mmp2.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 enable-method = "marvell,mmp3-smp";
22 next-level-cache = <&l2>;
23 reg = <0>;
29 next-level-cache = <&l2>;
30 reg = <1>;
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "simple-bus";
38 interrupt-parent = <&gic>;
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
45 reg = <0xd4200000 0x00200000>;
48 interrupt-controller@d4282000 {
49 compatible = "marvell,mmp3-intc";
50 interrupt-controller;
51 #interrupt-cells = <1>;
52 reg = <0xd4282000 0x1000>,
54 mrvl,intc-nr-irqs = <64>;
57 pmic_mux: interrupt-controller@d4282150 {
58 compatible = "mrvl,mmp2-mux-intc";
60 interrupt-controller;
61 #interrupt-cells = <1>;
62 reg = <0x150 0x4>, <0x168 0x4>;
63 reg-names = "mux status", "mux mask";
64 mrvl,intc-nr-irqs = <4>;
67 rtc_mux: interrupt-controller@d4282154 {
68 compatible = "mrvl,mmp2-mux-intc";
70 interrupt-controller;
71 #interrupt-cells = <1>;
72 reg = <0x154 0x4>, <0x16c 0x4>;
73 reg-names = "mux status", "mux mask";
74 mrvl,intc-nr-irqs = <2>;
77 hsi3_mux: interrupt-controller@d42821bc {
78 compatible = "mrvl,mmp2-mux-intc";
80 interrupt-controller;
81 #interrupt-cells = <1>;
82 reg = <0x1bc 0x4>, <0x1a4 0x4>;
83 reg-names = "mux status", "mux mask";
84 mrvl,intc-nr-irqs = <3>;
87 gpu_mux: interrupt-controller@d42821c0 {
88 compatible = "mrvl,mmp2-mux-intc";
90 interrupt-controller;
91 #interrupt-cells = <1>;
92 reg = <0x1c0 0x4>, <0x1a8 0x4>;
93 reg-names = "mux status", "mux mask";
94 mrvl,intc-nr-irqs = <3>;
97 twsi_mux: interrupt-controller@d4282158 {
98 compatible = "mrvl,mmp2-mux-intc";
100 interrupt-controller;
101 #interrupt-cells = <1>;
102 reg = <0x158 0x4>, <0x170 0x4>;
103 reg-names = "mux status", "mux mask";
104 mrvl,intc-nr-irqs = <5>;
107 hsi2_mux: interrupt-controller@d42821c4 {
108 compatible = "mrvl,mmp2-mux-intc";
110 interrupt-controller;
111 #interrupt-cells = <1>;
112 reg = <0x1c4 0x4>, <0x1ac 0x4>;
113 reg-names = "mux status", "mux mask";
114 mrvl,intc-nr-irqs = <2>;
117 dxo_mux: interrupt-controller@d42821c8 {
118 compatible = "mrvl,mmp2-mux-intc";
120 interrupt-controller;
121 #interrupt-cells = <1>;
122 reg = <0x1c8 0x4>, <0x1b0 0x4>;
123 reg-names = "mux status", "mux mask";
124 mrvl,intc-nr-irqs = <2>;
127 misc1_mux: interrupt-controller@d428215c {
128 compatible = "mrvl,mmp2-mux-intc";
130 interrupt-controller;
131 #interrupt-cells = <1>;
132 reg = <0x15c 0x4>, <0x174 0x4>;
133 reg-names = "mux status", "mux mask";
134 mrvl,intc-nr-irqs = <31>;
137 ci_mux: interrupt-controller@d42821cc {
138 compatible = "mrvl,mmp2-mux-intc";
140 interrupt-controller;
141 #interrupt-cells = <1>;
142 reg = <0x1cc 0x4>, <0x1b4 0x4>;
143 reg-names = "mux status", "mux mask";
144 mrvl,intc-nr-irqs = <2>;
147 ssp_mux: interrupt-controller@d4282160 {
148 compatible = "mrvl,mmp2-mux-intc";
150 interrupt-controller;
151 #interrupt-cells = <1>;
152 reg = <0x160 0x4>, <0x178 0x4>;
153 reg-names = "mux status", "mux mask";
154 mrvl,intc-nr-irqs = <2>;
157 hsi1_mux: interrupt-controller@d4282184 {
158 compatible = "mrvl,mmp2-mux-intc";
160 interrupt-controller;
161 #interrupt-cells = <1>;
162 reg = <0x184 0x4>, <0x17c 0x4>;
163 reg-names = "mux status", "mux mask";
164 mrvl,intc-nr-irqs = <4>;
167 misc2_mux: interrupt-controller@d4282188 {
168 compatible = "mrvl,mmp2-mux-intc";
170 interrupt-controller;
171 #interrupt-cells = <1>;
172 reg = <0x188 0x4>, <0x180 0x4>;
173 reg-names = "mux status", "mux mask";
174 mrvl,intc-nr-irqs = <20>;
177 hsi0_mux: interrupt-controller@d42821d0 {
178 compatible = "mrvl,mmp2-mux-intc";
180 interrupt-controller;
181 #interrupt-cells = <1>;
182 reg = <0x1d0 0x4>, <0x1b8 0x4>;
183 reg-names = "mux status", "mux mask";
184 mrvl,intc-nr-irqs = <5>;
187 usb_otg_phy0: usb-phy@d4207000 {
188 compatible = "marvell,mmp3-usb-phy";
189 reg = <0xd4207000 0x40>;
190 #phy-cells = <0>;
195 compatible = "marvell,pxau2o-ehci";
196 reg = <0xd4208000 0x200>;
199 clock-names = "USBCLK";
201 phy-names = "usb";
205 hsic_phy0: usb-phy@f0001800 {
206 compatible = "marvell,mmp3-hsic-phy";
207 reg = <0xf0001800 0x40>;
208 #phy-cells = <0>;
213 compatible = "marvell,pxau2o-ehci";
214 reg = <0xf0001000 0x200>;
217 clock-names = "USBCLK";
219 phy-names = "usb";
221 #address-cells = <0x01>;
222 #size-cells = <0x00>;
226 hsic_phy1: usb-phy@f0002800 {
227 compatible = "marvell,mmp3-hsic-phy";
228 reg = <0xf0002800 0x40>;
229 #phy-cells = <0>;
234 compatible = "marvell,pxau2o-ehci";
235 reg = <0xf0002000 0x200>;
238 clock-names = "USBCLK";
240 phy-names = "usb";
242 #address-cells = <0x01>;
243 #size-cells = <0x00>;
248 compatible = "mrvl,pxav3-mmc";
249 reg = <0xd4280000 0x120>;
251 clock-names = "io";
257 compatible = "mrvl,pxav3-mmc";
258 reg = <0xd4280800 0x120>;
260 clock-names = "io";
266 compatible = "mrvl,pxav3-mmc";
267 reg = <0xd4281000 0x120>;
269 clock-names = "io";
275 compatible = "mrvl,pxav3-mmc";
276 reg = <0xd4281800 0x120>;
278 clock-names = "io";
284 compatible = "mrvl,pxav3-mmc";
285 reg = <0xd4217000 0x120>;
287 clock-names = "io";
288 interrupt-parent = <&hsi1_mux>;
294 compatible = "marvell,mmp2-ccic";
295 reg = <0xd420a000 0x800>;
298 clock-names = "axi";
299 power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
300 #clock-cells = <0>;
301 clock-output-names = "mclk";
306 compatible = "marvell,mmp2-ccic";
307 reg = <0xd420a800 0x800>;
310 clock-names = "axi";
311 power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
312 #clock-cells = <0>;
313 clock-output-names = "mclk";
319 reg = <0xd420d000 0x2000>;
320 interrupt-parent = <&gpu_mux>;
325 clock-names = "core", "bus";
326 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
331 reg = <0xd420f000 0x2000>;
332 interrupt-parent = <&gpu_mux>;
337 clock-names = "core", "bus";
338 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
343 compatible = "simple-bus";
344 #address-cells = <1>;
345 #size-cells = <1>;
346 reg = <0xd4000000 0x00200000>;
350 compatible = "mrvl,mmp-timer";
351 reg = <0xd4014000 0x100>;
357 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
358 reg = <0xd4030000 0x1000>;
362 reg-shift = <2>;
367 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
368 reg = <0xd4017000 0x1000>;
372 reg-shift = <2>;
377 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
378 reg = <0xd4018000 0x1000>;
382 reg-shift = <2>;
387 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
388 reg = <0xd4016000 0x1000>;
392 reg-shift = <2>;
397 compatible = "marvell,mmp2-gpio";
398 #address-cells = <1>;
399 #size-cells = <1>;
400 reg = <0xd4019000 0x1000>;
401 gpio-controller;
402 #gpio-cells = <2>;
404 interrupt-names = "gpio_mux";
407 interrupt-controller;
408 #interrupt-cells = <2>;
412 reg = <0xd4019000 0x4>;
416 reg = <0xd4019004 0x4>;
420 reg = <0xd4019008 0x4>;
424 reg = <0xd4019100 0x4>;
428 reg = <0xd4019104 0x4>;
432 reg = <0xd4019108 0x4>;
437 compatible = "mrvl,mmp-twsi";
438 reg = <0xd4011000 0x70>;
442 #address-cells = <1>;
443 #size-cells = <0>;
444 mrvl,i2c-fast-mode;
449 compatible = "mrvl,mmp-twsi";
450 reg = <0xd4031000 0x70>;
451 interrupt-parent = <&twsi_mux>;
455 #address-cells = <1>;
456 #size-cells = <0>;
461 compatible = "mrvl,mmp-twsi";
462 reg = <0xd4032000 0x70>;
463 interrupt-parent = <&twsi_mux>;
467 #address-cells = <1>;
468 #size-cells = <0>;
473 compatible = "mrvl,mmp-twsi";
474 reg = <0xd4033000 0x70>;
475 interrupt-parent = <&twsi_mux>;
479 #address-cells = <1>;
480 #size-cells = <0>;
486 compatible = "mrvl,mmp-twsi";
487 reg = <0xd4033800 0x70>;
488 interrupt-parent = <&twsi_mux>;
492 #address-cells = <1>;
493 #size-cells = <0>;
498 compatible = "mrvl,mmp-twsi";
499 reg = <0xd4034000 0x70>;
500 interrupt-parent = <&twsi_mux>;
504 #address-cells = <1>;
505 #size-cells = <0>;
510 compatible = "mrvl,mmp-rtc";
511 reg = <0xd4010000 0x1000>;
513 interrupt-names = "rtc 1Hz", "rtc alarm";
514 interrupt-parent = <&rtc_mux>;
521 compatible = "marvell,mmp2-ssp";
522 reg = <0xd4035000 0x1000>;
525 #address-cells = <1>;
526 #size-cells = <0>;
531 compatible = "marvell,mmp2-ssp";
532 reg = <0xd4036000 0x1000>;
535 #address-cells = <1>;
536 #size-cells = <0>;
541 compatible = "marvell,mmp2-ssp";
542 reg = <0xd4037000 0x1000>;
545 #address-cells = <1>;
546 #size-cells = <0>;
551 compatible = "marvell,mmp2-ssp";
552 reg = <0xd4039000 0x1000>;
555 #address-cells = <1>;
556 #size-cells = <0>;
561 l2: cache-controller@d0020000 {
562 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
563 reg = <0xd0020000 0x1000>;
564 cache-unified;
565 cache-level = <2>;
569 compatible = "marvell,mmp3-clock";
570 reg = <0xd4050000 0x1000>,
573 reg-names = "mpmu", "apmu", "apbc";
574 #clock-cells = <1>;
575 #reset-cells = <1>;
576 #power-domain-cells = <1>;
579 snoop-control-unit@e0000000 {
580 compatible = "arm,arm11mp-scu";
581 reg = <0xe0000000 0x100>;
584 gic: interrupt-controller@e0001000 {
585 compatible = "arm,arm11mp-gic";
586 interrupt-controller;
587 #interrupt-cells = <3>;
588 reg = <0xe0001000 0x1000>,
592 local-timer@e0000600 {
593 compatible = "arm,arm11mp-twd-timer";
596 reg = <0xe0000600 0x20>;
600 compatible = "arm,arm11mp-twd-wdt";
601 reg = <0xe0000620 0x20>;