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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra30-cpu-opp-microvolt.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 opp@51000000,800 {
6 opp-microvolt = <800000 800000 1250000>;
9 opp@51000000,850 {
10 opp-microvolt = <850000 850000 1250000>;
13 opp@51000000,912 {
14 opp-microvolt = <912000 912000 1250000>;
17 opp@102000000,800 {
18 opp-microvolt = <800000 800000 1250000>;
21 opp@102000000,850 {
[all …]
H A Dtegra20-cpu-opp-microvolt.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 opp@216000000,750 {
6 opp-microvolt = <750000 750000 1125000>;
9 opp@216000000,800 {
10 opp-microvolt = <800000 800000 1125000>;
13 opp@312000000,750 {
14 opp-microvolt = <750000 750000 1125000>;
17 opp@312000000,800 {
18 opp-microvolt = <800000 800000 1125000>;
21 opp@456000000,750 {
[all …]
H A Dexynos5800.dtsi1 // SPDX-License-Identifier: GPL-2.0
20 compatible = "samsung,exynos5800-clock", "syscon";
24 opp-2000000000 {
25 opp-hz = /bits/ 64 <2000000000>;
26 opp-microvolt = <1312500 1312500 1500000>;
27 clock-latency-ns = <140000>;
29 opp-1900000000 {
30 opp-hz = /bits/ 64 <1900000000>;
31 opp-microvolt = <1262500 1262500 1500000>;
32 clock-latency-ns = <140000>;
[all …]
H A Drk3229-cpu-opp.dtsi4 * This file is dual-licensed: you can use it either under the terms
44 /delete-node/ opp-table0;
47 compatible = "operating-points-v2";
48 opp-shared;
51 rockchip,max-volt = <1350000>;
52 rockchip,leakage-voltage-sel = <
56 nvmem-cells = <&cpu_leakage>;
57 nvmem-cell-names = "cpu_leakage";
59 opp-408000000 {
60 opp-hz = /bits/ 64 <408000000>;
[all …]
H A Dexynos5422-odroid-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
23 stdout-path = "serial2:115200n8";
27 compatible = "samsung,secure-firmware";
31 fixed-rate-clocks {
[all …]
H A Drk3128.dtsi2 * This file is dual-licensed: you can use it either under the terms
47 compatible = "rockchip,cryptov1-rng";
50 clock-names = "clk_crypto", "hclk_crypto";
51 assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
52 assigned-clock-rates = <150000000>, <100000000>;
54 reset-names = "reset";
64 compatible = "rockchip,rk3128-inno-hdmi";
68 clock-names = "aclk", "pclk";
70 pinctrl-names = "default";
71 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
[all …]
H A Drk3288cg-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 rockchip,max-volt = <1400000>;
8 opp-1704000000 {
9 opp-hz = /bits/ 64 <1704000000>;
10 opp-microvolt = <1350000 1350000 1400000>;
11 opp-microvolt-L0 = <1350000 1350000 1400000>;
12 opp-microvolt-L1 = <1350000 1350000 1400000>;
13 opp-microvolt-L2 = <1350000 1350000 1400000>;
14 opp-microvolt-L3 = <1350000 1350000 1400000>;
15 clock-latency-ns = <40000>;
[all …]
H A Drk3229.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /delete-node/ opp-table0;
14 compatible = "operating-points-v2";
15 opp-shared;
17 opp-408000000 {
18 opp-hz = /bits/ 64 <408000000>;
19 opp-microvolt = <950000>;
20 clock-latency-ns = <40000>;
21 opp-suspend;
23 opp-600000000 {
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
6 #include "rk3399-sched-energy.dtsi"
9 cluster0_opp: opp-table0 {
10 compatible = "operating-points-v2";
11 opp-shared;
13 rockchip,temp-hysteresis = <5000>;
14 rockchip,low-temp = <10000>;
15 rockchip,low-temp-min-volt = <900000>;
17 nvmem-cells = <&cpul_leakage>, <&specification_serial_number>,
[all …]
H A Drk3399-op1-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
7 cluster0_opp: opp-table0 {
8 compatible = "operating-points-v2";
9 opp-shared;
12 opp-hz = /bits/ 64 <408000000>;
13 opp-microvolt = <800000>;
14 clock-latency-ns = <40000>;
17 opp-hz = /bits/ 64 <600000000>;
18 opp-microvolt = <825000>;
[all …]
H A Drk3562j.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 compatible = "rockchip,rk3562-can";
14 clock-names = "baudclk", "apb_pclk";
16 reset-names = "can", "can-apb";
21 compatible = "rockchip,rk3562-can";
25 clock-names = "baudclk", "apb_pclk";
27 reset-names = "can", "can-apb";
33 /delete-node/ mbist-vmin;
38 /delete-node/ opp-1416000000;
39 /delete-node/ opp-1608000000;
[all …]
H A Drk3399-early-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * NOTE: this file exists for the sake of early (pre-ES2) silicon. ES2 silicon
13 /delete-node/ opp-table0;
14 /delete-node/ opp-table1;
15 /delete-node/ opp-table2;
17 cluster0_opp: opp-table0 {
18 compatible = "operating-points-v2";
19 opp-shared;
21 opp-408000000 {
22 opp-hz = /bits/ 64 <408000000>;
[all …]
H A Dpx30.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/display/media-bus-format.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/power/px30-power.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/soc/rockchip-system-status.h>
[all …]
H A Drk3588s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rk3588-power.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #include <dt-bindings/soc/rockchip-system-status.h>
13 #include <dt-bindings/suspend/rockchip-rk3588.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Drk3528.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3528-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/power/rk3528-power.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/soc/rockchip-system-status.h>
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/opp/
H A Dqcom-nvmem-cpufreq.txt1 Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings
5 the CPU frequencies subset and voltage value of each OPP varies based on
8 defines the voltage and frequency value based on the msm-id in SMEM
10 The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
11 to provide the OPP framework with required information (existing HW bitmap).
12 This is used to determine the voltage and frequency value for each OPP of
13 operating-points-v2 table when it is parsed by the OPP framework.
16 --------------------
18 - operating-points-v2: Phandle to the operating-points-v2 table to use.
20 In 'operating-points-v2' table:
[all …]
H A Dallwinner,sun50i-h6-operating-points.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner H6 CPU OPP Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 OPP varies based on the silicon variant in use. Allwinner Process
18 sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
19 provide the OPP framework with required information.
[all …]
H A Dopp.txt1 Generic OPP (Operating Performance Points) Bindings
2 ----------------------------------------------------
4 Devices work at voltage-current-frequency combinations and some implementations
10 This document contain multiple versions of OPP binding and only one of them
13 Binding 1: operating-points
16 This binding only supports voltage-frequency pairs.
19 - operating-points: An array of 2-tuples items, and each item consists
20 of frequency and voltage like <freq-kHz vol-uV>.
22 vol: voltage in microvolt
27 compatible = "arm,cortex-a9";
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h6-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 cpu_opp_table: opp-table-cpu {
7 compatible = "allwinner,sun50i-h6-operating-points";
8 nvmem-cells = <&cpu_speed_grade>;
9 opp-shared;
11 opp@480000000 {
12 clock-latency-ns = <244144>; /* 8 32k periods */
13 opp-hz = /bits/ 64 <480000000>;
15 opp-microvolt-speed0 = <880000 880000 1200000>;
16 opp-microvolt-speed1 = <820000 820000 1200000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-a311d.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12b.dtsi"
10 cpu_opp_table_0: opp-table-0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-1000000000 {
15 opp-hz = /bits/ 64 <1000000000>;
16 opp-microvolt = <761000>;
19 opp-1200000000 {
20 opp-hz = /bits/ 64 <1200000000>;
[all …]
H A Dmeson-g12b-s922x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12b.dtsi"
10 cpu_opp_table_0: opp-table-0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-1000000000 {
15 opp-hz = /bits/ 64 <1000000000>;
16 opp-microvolt = <731000>;
19 opp-1200000000 {
20 opp-hz = /bits/ 64 <1200000000>;
[all …]
H A Dmeson-g12a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-g12.dtsi"
12 #address-cells = <0x2>;
13 #size-cells = <0x0>;
17 compatible = "arm,cortex-a53";
19 enable-method = "psci";
20 next-level-cache = <&l2>;
21 #cooling-cells = <2>;
26 compatible = "arm,cortex-a53";
28 enable-method = "psci";
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - #cooling-cells:
25 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
[all …]
H A Dcpufreq-st.txt5 from the SoC, then supplies the OPP framework with 'prop' and 'supported
9 For more information about the expected DT format [See: ../opp/opp.txt].
12 ----------------------
18 - operating-points : [See: ../power/opp.txt]
21 --------------
26 operating-points = <1500000 0
34 --------------------------------------------
40 - operating-points-v2 : [See ../power/opp.txt]
43 ----------------
47 operating-points-v2 = <&cpu0_opp_table>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/
H A Dmali-opp.txt1 # SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 # (C) COPYRIGHT 2017, 2019-2021 ARM Limited. All rights reserved.
17 # http://www.gnu.org/licenses/gpl-2.0.html.
22 * ARM Mali Midgard OPP
24 * OPP Table Node
30 - compatible: Allow OPPs to express their compatibility. It should be:
31 "operating-points-v2", "operating-points-v2-mali".
33 - OPP nodes: One or more OPP nodes describing voltage-current-frequency
35 reference an OPP.
37 * OPP Node
[all …]

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