1*4882a593SmuzhiyunQualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings 2*4882a593Smuzhiyun=================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunIn Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996, 5*4882a593Smuzhiyunthe CPU frequencies subset and voltage value of each OPP varies based on 6*4882a593Smuzhiyunthe silicon variant in use. 7*4882a593SmuzhiyunQualcomm Technologies, Inc. Process Voltage Scaling Tables 8*4882a593Smuzhiyundefines the voltage and frequency value based on the msm-id in SMEM 9*4882a593Smuzhiyunand speedbin blown in the efuse combination. 10*4882a593SmuzhiyunThe qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC 11*4882a593Smuzhiyunto provide the OPP framework with required information (existing HW bitmap). 12*4882a593SmuzhiyunThis is used to determine the voltage and frequency value for each OPP of 13*4882a593Smuzhiyunoperating-points-v2 table when it is parsed by the OPP framework. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunRequired properties: 16*4882a593Smuzhiyun-------------------- 17*4882a593SmuzhiyunIn 'cpu' nodes: 18*4882a593Smuzhiyun- operating-points-v2: Phandle to the operating-points-v2 table to use. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunIn 'operating-points-v2' table: 21*4882a593Smuzhiyun- compatible: Should be 22*4882a593Smuzhiyun - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974, 23*4882a593Smuzhiyun apq8064, ipq8064, msm8960 and ipq8074. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunOptional properties: 26*4882a593Smuzhiyun-------------------- 27*4882a593SmuzhiyunIn 'cpu' nodes: 28*4882a593Smuzhiyun- power-domains: A phandle pointing to the PM domain specifier which provides 29*4882a593Smuzhiyun the performance states available for active state management. 30*4882a593Smuzhiyun Please refer to the power-domains bindings 31*4882a593Smuzhiyun Documentation/devicetree/bindings/power/power_domain.txt 32*4882a593Smuzhiyun and also examples below. 33*4882a593Smuzhiyun- power-domain-names: Should be 34*4882a593Smuzhiyun - 'cpr' for qcs404. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunIn 'operating-points-v2' table: 37*4882a593Smuzhiyun- nvmem-cells: A phandle pointing to a nvmem-cells node representing the 38*4882a593Smuzhiyun efuse registers that has information about the 39*4882a593Smuzhiyun speedbin that is used to select the right frequency/voltage 40*4882a593Smuzhiyun value pair. 41*4882a593Smuzhiyun Please refer the for nvmem-cells 42*4882a593Smuzhiyun bindings Documentation/devicetree/bindings/nvmem/nvmem.txt 43*4882a593Smuzhiyun and also examples below. 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunIn every OPP node: 46*4882a593Smuzhiyun- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW. 47*4882a593Smuzhiyun Bitmap: 48*4882a593Smuzhiyun 0: MSM8996 V3, speedbin 0 49*4882a593Smuzhiyun 1: MSM8996 V3, speedbin 1 50*4882a593Smuzhiyun 2: MSM8996 V3, speedbin 2 51*4882a593Smuzhiyun 3: unused 52*4882a593Smuzhiyun 4: MSM8996 SG, speedbin 0 53*4882a593Smuzhiyun 5: MSM8996 SG, speedbin 1 54*4882a593Smuzhiyun 6: MSM8996 SG, speedbin 2 55*4882a593Smuzhiyun 7-31: unused 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunExample 1: 58*4882a593Smuzhiyun--------- 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun cpus { 61*4882a593Smuzhiyun #address-cells = <2>; 62*4882a593Smuzhiyun #size-cells = <0>; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun CPU0: cpu@0 { 65*4882a593Smuzhiyun device_type = "cpu"; 66*4882a593Smuzhiyun compatible = "qcom,kryo"; 67*4882a593Smuzhiyun reg = <0x0 0x0>; 68*4882a593Smuzhiyun enable-method = "psci"; 69*4882a593Smuzhiyun clocks = <&kryocc 0>; 70*4882a593Smuzhiyun cpu-supply = <&pm8994_s11_saw>; 71*4882a593Smuzhiyun operating-points-v2 = <&cluster0_opp>; 72*4882a593Smuzhiyun #cooling-cells = <2>; 73*4882a593Smuzhiyun next-level-cache = <&L2_0>; 74*4882a593Smuzhiyun L2_0: l2-cache { 75*4882a593Smuzhiyun compatible = "cache"; 76*4882a593Smuzhiyun cache-level = <2>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun CPU1: cpu@1 { 81*4882a593Smuzhiyun device_type = "cpu"; 82*4882a593Smuzhiyun compatible = "qcom,kryo"; 83*4882a593Smuzhiyun reg = <0x0 0x1>; 84*4882a593Smuzhiyun enable-method = "psci"; 85*4882a593Smuzhiyun clocks = <&kryocc 0>; 86*4882a593Smuzhiyun cpu-supply = <&pm8994_s11_saw>; 87*4882a593Smuzhiyun operating-points-v2 = <&cluster0_opp>; 88*4882a593Smuzhiyun #cooling-cells = <2>; 89*4882a593Smuzhiyun next-level-cache = <&L2_0>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun CPU2: cpu@100 { 93*4882a593Smuzhiyun device_type = "cpu"; 94*4882a593Smuzhiyun compatible = "qcom,kryo"; 95*4882a593Smuzhiyun reg = <0x0 0x100>; 96*4882a593Smuzhiyun enable-method = "psci"; 97*4882a593Smuzhiyun clocks = <&kryocc 1>; 98*4882a593Smuzhiyun cpu-supply = <&pm8994_s11_saw>; 99*4882a593Smuzhiyun operating-points-v2 = <&cluster1_opp>; 100*4882a593Smuzhiyun #cooling-cells = <2>; 101*4882a593Smuzhiyun next-level-cache = <&L2_1>; 102*4882a593Smuzhiyun L2_1: l2-cache { 103*4882a593Smuzhiyun compatible = "cache"; 104*4882a593Smuzhiyun cache-level = <2>; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun CPU3: cpu@101 { 109*4882a593Smuzhiyun device_type = "cpu"; 110*4882a593Smuzhiyun compatible = "qcom,kryo"; 111*4882a593Smuzhiyun reg = <0x0 0x101>; 112*4882a593Smuzhiyun enable-method = "psci"; 113*4882a593Smuzhiyun clocks = <&kryocc 1>; 114*4882a593Smuzhiyun cpu-supply = <&pm8994_s11_saw>; 115*4882a593Smuzhiyun operating-points-v2 = <&cluster1_opp>; 116*4882a593Smuzhiyun #cooling-cells = <2>; 117*4882a593Smuzhiyun next-level-cache = <&L2_1>; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun cpu-map { 121*4882a593Smuzhiyun cluster0 { 122*4882a593Smuzhiyun core0 { 123*4882a593Smuzhiyun cpu = <&CPU0>; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun core1 { 127*4882a593Smuzhiyun cpu = <&CPU1>; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun cluster1 { 132*4882a593Smuzhiyun core0 { 133*4882a593Smuzhiyun cpu = <&CPU2>; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun core1 { 137*4882a593Smuzhiyun cpu = <&CPU3>; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun cluster0_opp: opp_table0 { 144*4882a593Smuzhiyun compatible = "operating-points-v2-kryo-cpu"; 145*4882a593Smuzhiyun nvmem-cells = <&speedbin_efuse>; 146*4882a593Smuzhiyun opp-shared; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun opp-307200000 { 149*4882a593Smuzhiyun opp-hz = /bits/ 64 <307200000>; 150*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 151*4882a593Smuzhiyun opp-supported-hw = <0x77>; 152*4882a593Smuzhiyun clock-latency-ns = <200000>; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun opp-384000000 { 155*4882a593Smuzhiyun opp-hz = /bits/ 64 <384000000>; 156*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 157*4882a593Smuzhiyun opp-supported-hw = <0x70>; 158*4882a593Smuzhiyun clock-latency-ns = <200000>; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun opp-422400000 { 161*4882a593Smuzhiyun opp-hz = /bits/ 64 <422400000>; 162*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 163*4882a593Smuzhiyun opp-supported-hw = <0x7>; 164*4882a593Smuzhiyun clock-latency-ns = <200000>; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun opp-460800000 { 167*4882a593Smuzhiyun opp-hz = /bits/ 64 <460800000>; 168*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 169*4882a593Smuzhiyun opp-supported-hw = <0x70>; 170*4882a593Smuzhiyun clock-latency-ns = <200000>; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun opp-480000000 { 173*4882a593Smuzhiyun opp-hz = /bits/ 64 <480000000>; 174*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 175*4882a593Smuzhiyun opp-supported-hw = <0x7>; 176*4882a593Smuzhiyun clock-latency-ns = <200000>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun opp-537600000 { 179*4882a593Smuzhiyun opp-hz = /bits/ 64 <537600000>; 180*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 181*4882a593Smuzhiyun opp-supported-hw = <0x70>; 182*4882a593Smuzhiyun clock-latency-ns = <200000>; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun opp-556800000 { 185*4882a593Smuzhiyun opp-hz = /bits/ 64 <556800000>; 186*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 187*4882a593Smuzhiyun opp-supported-hw = <0x7>; 188*4882a593Smuzhiyun clock-latency-ns = <200000>; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun opp-614400000 { 191*4882a593Smuzhiyun opp-hz = /bits/ 64 <614400000>; 192*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 193*4882a593Smuzhiyun opp-supported-hw = <0x70>; 194*4882a593Smuzhiyun clock-latency-ns = <200000>; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun opp-652800000 { 197*4882a593Smuzhiyun opp-hz = /bits/ 64 <652800000>; 198*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 199*4882a593Smuzhiyun opp-supported-hw = <0x7>; 200*4882a593Smuzhiyun clock-latency-ns = <200000>; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun opp-691200000 { 203*4882a593Smuzhiyun opp-hz = /bits/ 64 <691200000>; 204*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 205*4882a593Smuzhiyun opp-supported-hw = <0x70>; 206*4882a593Smuzhiyun clock-latency-ns = <200000>; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun opp-729600000 { 209*4882a593Smuzhiyun opp-hz = /bits/ 64 <729600000>; 210*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 211*4882a593Smuzhiyun opp-supported-hw = <0x7>; 212*4882a593Smuzhiyun clock-latency-ns = <200000>; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun opp-768000000 { 215*4882a593Smuzhiyun opp-hz = /bits/ 64 <768000000>; 216*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 217*4882a593Smuzhiyun opp-supported-hw = <0x70>; 218*4882a593Smuzhiyun clock-latency-ns = <200000>; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun opp-844800000 { 221*4882a593Smuzhiyun opp-hz = /bits/ 64 <844800000>; 222*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 223*4882a593Smuzhiyun opp-supported-hw = <0x77>; 224*4882a593Smuzhiyun clock-latency-ns = <200000>; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun opp-902400000 { 227*4882a593Smuzhiyun opp-hz = /bits/ 64 <902400000>; 228*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 229*4882a593Smuzhiyun opp-supported-hw = <0x70>; 230*4882a593Smuzhiyun clock-latency-ns = <200000>; 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun opp-960000000 { 233*4882a593Smuzhiyun opp-hz = /bits/ 64 <960000000>; 234*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 235*4882a593Smuzhiyun opp-supported-hw = <0x7>; 236*4882a593Smuzhiyun clock-latency-ns = <200000>; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun opp-979200000 { 239*4882a593Smuzhiyun opp-hz = /bits/ 64 <979200000>; 240*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 241*4882a593Smuzhiyun opp-supported-hw = <0x70>; 242*4882a593Smuzhiyun clock-latency-ns = <200000>; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun opp-1036800000 { 245*4882a593Smuzhiyun opp-hz = /bits/ 64 <1036800000>; 246*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 247*4882a593Smuzhiyun opp-supported-hw = <0x7>; 248*4882a593Smuzhiyun clock-latency-ns = <200000>; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun opp-1056000000 { 251*4882a593Smuzhiyun opp-hz = /bits/ 64 <1056000000>; 252*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 253*4882a593Smuzhiyun opp-supported-hw = <0x70>; 254*4882a593Smuzhiyun clock-latency-ns = <200000>; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun opp-1113600000 { 257*4882a593Smuzhiyun opp-hz = /bits/ 64 <1113600000>; 258*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 259*4882a593Smuzhiyun opp-supported-hw = <0x7>; 260*4882a593Smuzhiyun clock-latency-ns = <200000>; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun opp-1132800000 { 263*4882a593Smuzhiyun opp-hz = /bits/ 64 <1132800000>; 264*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 265*4882a593Smuzhiyun opp-supported-hw = <0x70>; 266*4882a593Smuzhiyun clock-latency-ns = <200000>; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun opp-1190400000 { 269*4882a593Smuzhiyun opp-hz = /bits/ 64 <1190400000>; 270*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 271*4882a593Smuzhiyun opp-supported-hw = <0x7>; 272*4882a593Smuzhiyun clock-latency-ns = <200000>; 273*4882a593Smuzhiyun }; 274*4882a593Smuzhiyun opp-1209600000 { 275*4882a593Smuzhiyun opp-hz = /bits/ 64 <1209600000>; 276*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 277*4882a593Smuzhiyun opp-supported-hw = <0x70>; 278*4882a593Smuzhiyun clock-latency-ns = <200000>; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun opp-1228800000 { 281*4882a593Smuzhiyun opp-hz = /bits/ 64 <1228800000>; 282*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 283*4882a593Smuzhiyun opp-supported-hw = <0x7>; 284*4882a593Smuzhiyun clock-latency-ns = <200000>; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun opp-1286400000 { 287*4882a593Smuzhiyun opp-hz = /bits/ 64 <1286400000>; 288*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 289*4882a593Smuzhiyun opp-supported-hw = <0x70>; 290*4882a593Smuzhiyun clock-latency-ns = <200000>; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun opp-1324800000 { 293*4882a593Smuzhiyun opp-hz = /bits/ 64 <1324800000>; 294*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 295*4882a593Smuzhiyun opp-supported-hw = <0x5>; 296*4882a593Smuzhiyun clock-latency-ns = <200000>; 297*4882a593Smuzhiyun }; 298*4882a593Smuzhiyun opp-1363200000 { 299*4882a593Smuzhiyun opp-hz = /bits/ 64 <1363200000>; 300*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 301*4882a593Smuzhiyun opp-supported-hw = <0x72>; 302*4882a593Smuzhiyun clock-latency-ns = <200000>; 303*4882a593Smuzhiyun }; 304*4882a593Smuzhiyun opp-1401600000 { 305*4882a593Smuzhiyun opp-hz = /bits/ 64 <1401600000>; 306*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 307*4882a593Smuzhiyun opp-supported-hw = <0x5>; 308*4882a593Smuzhiyun clock-latency-ns = <200000>; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun opp-1440000000 { 311*4882a593Smuzhiyun opp-hz = /bits/ 64 <1440000000>; 312*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 313*4882a593Smuzhiyun opp-supported-hw = <0x70>; 314*4882a593Smuzhiyun clock-latency-ns = <200000>; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun opp-1478400000 { 317*4882a593Smuzhiyun opp-hz = /bits/ 64 <1478400000>; 318*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 319*4882a593Smuzhiyun opp-supported-hw = <0x1>; 320*4882a593Smuzhiyun clock-latency-ns = <200000>; 321*4882a593Smuzhiyun }; 322*4882a593Smuzhiyun opp-1497600000 { 323*4882a593Smuzhiyun opp-hz = /bits/ 64 <1497600000>; 324*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 325*4882a593Smuzhiyun opp-supported-hw = <0x4>; 326*4882a593Smuzhiyun clock-latency-ns = <200000>; 327*4882a593Smuzhiyun }; 328*4882a593Smuzhiyun opp-1516800000 { 329*4882a593Smuzhiyun opp-hz = /bits/ 64 <1516800000>; 330*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 331*4882a593Smuzhiyun opp-supported-hw = <0x70>; 332*4882a593Smuzhiyun clock-latency-ns = <200000>; 333*4882a593Smuzhiyun }; 334*4882a593Smuzhiyun opp-1593600000 { 335*4882a593Smuzhiyun opp-hz = /bits/ 64 <1593600000>; 336*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 337*4882a593Smuzhiyun opp-supported-hw = <0x71>; 338*4882a593Smuzhiyun clock-latency-ns = <200000>; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun opp-1996800000 { 341*4882a593Smuzhiyun opp-hz = /bits/ 64 <1996800000>; 342*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 343*4882a593Smuzhiyun opp-supported-hw = <0x20>; 344*4882a593Smuzhiyun clock-latency-ns = <200000>; 345*4882a593Smuzhiyun }; 346*4882a593Smuzhiyun opp-2188800000 { 347*4882a593Smuzhiyun opp-hz = /bits/ 64 <2188800000>; 348*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 349*4882a593Smuzhiyun opp-supported-hw = <0x10>; 350*4882a593Smuzhiyun clock-latency-ns = <200000>; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun cluster1_opp: opp_table1 { 355*4882a593Smuzhiyun compatible = "operating-points-v2-kryo-cpu"; 356*4882a593Smuzhiyun nvmem-cells = <&speedbin_efuse>; 357*4882a593Smuzhiyun opp-shared; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun opp-307200000 { 360*4882a593Smuzhiyun opp-hz = /bits/ 64 <307200000>; 361*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 362*4882a593Smuzhiyun opp-supported-hw = <0x77>; 363*4882a593Smuzhiyun clock-latency-ns = <200000>; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun opp-384000000 { 366*4882a593Smuzhiyun opp-hz = /bits/ 64 <384000000>; 367*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 368*4882a593Smuzhiyun opp-supported-hw = <0x70>; 369*4882a593Smuzhiyun clock-latency-ns = <200000>; 370*4882a593Smuzhiyun }; 371*4882a593Smuzhiyun opp-403200000 { 372*4882a593Smuzhiyun opp-hz = /bits/ 64 <403200000>; 373*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 374*4882a593Smuzhiyun opp-supported-hw = <0x7>; 375*4882a593Smuzhiyun clock-latency-ns = <200000>; 376*4882a593Smuzhiyun }; 377*4882a593Smuzhiyun opp-460800000 { 378*4882a593Smuzhiyun opp-hz = /bits/ 64 <460800000>; 379*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 380*4882a593Smuzhiyun opp-supported-hw = <0x70>; 381*4882a593Smuzhiyun clock-latency-ns = <200000>; 382*4882a593Smuzhiyun }; 383*4882a593Smuzhiyun opp-480000000 { 384*4882a593Smuzhiyun opp-hz = /bits/ 64 <480000000>; 385*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 386*4882a593Smuzhiyun opp-supported-hw = <0x7>; 387*4882a593Smuzhiyun clock-latency-ns = <200000>; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun opp-537600000 { 390*4882a593Smuzhiyun opp-hz = /bits/ 64 <537600000>; 391*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 392*4882a593Smuzhiyun opp-supported-hw = <0x70>; 393*4882a593Smuzhiyun clock-latency-ns = <200000>; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun opp-556800000 { 396*4882a593Smuzhiyun opp-hz = /bits/ 64 <556800000>; 397*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 398*4882a593Smuzhiyun opp-supported-hw = <0x7>; 399*4882a593Smuzhiyun clock-latency-ns = <200000>; 400*4882a593Smuzhiyun }; 401*4882a593Smuzhiyun opp-614400000 { 402*4882a593Smuzhiyun opp-hz = /bits/ 64 <614400000>; 403*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 404*4882a593Smuzhiyun opp-supported-hw = <0x70>; 405*4882a593Smuzhiyun clock-latency-ns = <200000>; 406*4882a593Smuzhiyun }; 407*4882a593Smuzhiyun opp-652800000 { 408*4882a593Smuzhiyun opp-hz = /bits/ 64 <652800000>; 409*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 410*4882a593Smuzhiyun opp-supported-hw = <0x7>; 411*4882a593Smuzhiyun clock-latency-ns = <200000>; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun opp-691200000 { 414*4882a593Smuzhiyun opp-hz = /bits/ 64 <691200000>; 415*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 416*4882a593Smuzhiyun opp-supported-hw = <0x70>; 417*4882a593Smuzhiyun clock-latency-ns = <200000>; 418*4882a593Smuzhiyun }; 419*4882a593Smuzhiyun opp-729600000 { 420*4882a593Smuzhiyun opp-hz = /bits/ 64 <729600000>; 421*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 422*4882a593Smuzhiyun opp-supported-hw = <0x7>; 423*4882a593Smuzhiyun clock-latency-ns = <200000>; 424*4882a593Smuzhiyun }; 425*4882a593Smuzhiyun opp-748800000 { 426*4882a593Smuzhiyun opp-hz = /bits/ 64 <748800000>; 427*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 428*4882a593Smuzhiyun opp-supported-hw = <0x70>; 429*4882a593Smuzhiyun clock-latency-ns = <200000>; 430*4882a593Smuzhiyun }; 431*4882a593Smuzhiyun opp-806400000 { 432*4882a593Smuzhiyun opp-hz = /bits/ 64 <806400000>; 433*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 434*4882a593Smuzhiyun opp-supported-hw = <0x7>; 435*4882a593Smuzhiyun clock-latency-ns = <200000>; 436*4882a593Smuzhiyun }; 437*4882a593Smuzhiyun opp-825600000 { 438*4882a593Smuzhiyun opp-hz = /bits/ 64 <825600000>; 439*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 440*4882a593Smuzhiyun opp-supported-hw = <0x70>; 441*4882a593Smuzhiyun clock-latency-ns = <200000>; 442*4882a593Smuzhiyun }; 443*4882a593Smuzhiyun opp-883200000 { 444*4882a593Smuzhiyun opp-hz = /bits/ 64 <883200000>; 445*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 446*4882a593Smuzhiyun opp-supported-hw = <0x7>; 447*4882a593Smuzhiyun clock-latency-ns = <200000>; 448*4882a593Smuzhiyun }; 449*4882a593Smuzhiyun opp-902400000 { 450*4882a593Smuzhiyun opp-hz = /bits/ 64 <902400000>; 451*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 452*4882a593Smuzhiyun opp-supported-hw = <0x70>; 453*4882a593Smuzhiyun clock-latency-ns = <200000>; 454*4882a593Smuzhiyun }; 455*4882a593Smuzhiyun opp-940800000 { 456*4882a593Smuzhiyun opp-hz = /bits/ 64 <940800000>; 457*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 458*4882a593Smuzhiyun opp-supported-hw = <0x7>; 459*4882a593Smuzhiyun clock-latency-ns = <200000>; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun opp-979200000 { 462*4882a593Smuzhiyun opp-hz = /bits/ 64 <979200000>; 463*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 464*4882a593Smuzhiyun opp-supported-hw = <0x70>; 465*4882a593Smuzhiyun clock-latency-ns = <200000>; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun opp-1036800000 { 468*4882a593Smuzhiyun opp-hz = /bits/ 64 <1036800000>; 469*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 470*4882a593Smuzhiyun opp-supported-hw = <0x7>; 471*4882a593Smuzhiyun clock-latency-ns = <200000>; 472*4882a593Smuzhiyun }; 473*4882a593Smuzhiyun opp-1056000000 { 474*4882a593Smuzhiyun opp-hz = /bits/ 64 <1056000000>; 475*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 476*4882a593Smuzhiyun opp-supported-hw = <0x70>; 477*4882a593Smuzhiyun clock-latency-ns = <200000>; 478*4882a593Smuzhiyun }; 479*4882a593Smuzhiyun opp-1113600000 { 480*4882a593Smuzhiyun opp-hz = /bits/ 64 <1113600000>; 481*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 482*4882a593Smuzhiyun opp-supported-hw = <0x7>; 483*4882a593Smuzhiyun clock-latency-ns = <200000>; 484*4882a593Smuzhiyun }; 485*4882a593Smuzhiyun opp-1132800000 { 486*4882a593Smuzhiyun opp-hz = /bits/ 64 <1132800000>; 487*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 488*4882a593Smuzhiyun opp-supported-hw = <0x70>; 489*4882a593Smuzhiyun clock-latency-ns = <200000>; 490*4882a593Smuzhiyun }; 491*4882a593Smuzhiyun opp-1190400000 { 492*4882a593Smuzhiyun opp-hz = /bits/ 64 <1190400000>; 493*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 494*4882a593Smuzhiyun opp-supported-hw = <0x7>; 495*4882a593Smuzhiyun clock-latency-ns = <200000>; 496*4882a593Smuzhiyun }; 497*4882a593Smuzhiyun opp-1209600000 { 498*4882a593Smuzhiyun opp-hz = /bits/ 64 <1209600000>; 499*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 500*4882a593Smuzhiyun opp-supported-hw = <0x70>; 501*4882a593Smuzhiyun clock-latency-ns = <200000>; 502*4882a593Smuzhiyun }; 503*4882a593Smuzhiyun opp-1248000000 { 504*4882a593Smuzhiyun opp-hz = /bits/ 64 <1248000000>; 505*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 506*4882a593Smuzhiyun opp-supported-hw = <0x7>; 507*4882a593Smuzhiyun clock-latency-ns = <200000>; 508*4882a593Smuzhiyun }; 509*4882a593Smuzhiyun opp-1286400000 { 510*4882a593Smuzhiyun opp-hz = /bits/ 64 <1286400000>; 511*4882a593Smuzhiyun opp-microvolt = <905000 905000 1140000>; 512*4882a593Smuzhiyun opp-supported-hw = <0x70>; 513*4882a593Smuzhiyun clock-latency-ns = <200000>; 514*4882a593Smuzhiyun }; 515*4882a593Smuzhiyun opp-1324800000 { 516*4882a593Smuzhiyun opp-hz = /bits/ 64 <1324800000>; 517*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 518*4882a593Smuzhiyun opp-supported-hw = <0x7>; 519*4882a593Smuzhiyun clock-latency-ns = <200000>; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun opp-1363200000 { 522*4882a593Smuzhiyun opp-hz = /bits/ 64 <1363200000>; 523*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 524*4882a593Smuzhiyun opp-supported-hw = <0x70>; 525*4882a593Smuzhiyun clock-latency-ns = <200000>; 526*4882a593Smuzhiyun }; 527*4882a593Smuzhiyun opp-1401600000 { 528*4882a593Smuzhiyun opp-hz = /bits/ 64 <1401600000>; 529*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 530*4882a593Smuzhiyun opp-supported-hw = <0x7>; 531*4882a593Smuzhiyun clock-latency-ns = <200000>; 532*4882a593Smuzhiyun }; 533*4882a593Smuzhiyun opp-1440000000 { 534*4882a593Smuzhiyun opp-hz = /bits/ 64 <1440000000>; 535*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 536*4882a593Smuzhiyun opp-supported-hw = <0x70>; 537*4882a593Smuzhiyun clock-latency-ns = <200000>; 538*4882a593Smuzhiyun }; 539*4882a593Smuzhiyun opp-1478400000 { 540*4882a593Smuzhiyun opp-hz = /bits/ 64 <1478400000>; 541*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 542*4882a593Smuzhiyun opp-supported-hw = <0x7>; 543*4882a593Smuzhiyun clock-latency-ns = <200000>; 544*4882a593Smuzhiyun }; 545*4882a593Smuzhiyun opp-1516800000 { 546*4882a593Smuzhiyun opp-hz = /bits/ 64 <1516800000>; 547*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 548*4882a593Smuzhiyun opp-supported-hw = <0x70>; 549*4882a593Smuzhiyun clock-latency-ns = <200000>; 550*4882a593Smuzhiyun }; 551*4882a593Smuzhiyun opp-1555200000 { 552*4882a593Smuzhiyun opp-hz = /bits/ 64 <1555200000>; 553*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 554*4882a593Smuzhiyun opp-supported-hw = <0x7>; 555*4882a593Smuzhiyun clock-latency-ns = <200000>; 556*4882a593Smuzhiyun }; 557*4882a593Smuzhiyun opp-1593600000 { 558*4882a593Smuzhiyun opp-hz = /bits/ 64 <1593600000>; 559*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 560*4882a593Smuzhiyun opp-supported-hw = <0x70>; 561*4882a593Smuzhiyun clock-latency-ns = <200000>; 562*4882a593Smuzhiyun }; 563*4882a593Smuzhiyun opp-1632000000 { 564*4882a593Smuzhiyun opp-hz = /bits/ 64 <1632000000>; 565*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 566*4882a593Smuzhiyun opp-supported-hw = <0x7>; 567*4882a593Smuzhiyun clock-latency-ns = <200000>; 568*4882a593Smuzhiyun }; 569*4882a593Smuzhiyun opp-1670400000 { 570*4882a593Smuzhiyun opp-hz = /bits/ 64 <1670400000>; 571*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 572*4882a593Smuzhiyun opp-supported-hw = <0x70>; 573*4882a593Smuzhiyun clock-latency-ns = <200000>; 574*4882a593Smuzhiyun }; 575*4882a593Smuzhiyun opp-1708800000 { 576*4882a593Smuzhiyun opp-hz = /bits/ 64 <1708800000>; 577*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 578*4882a593Smuzhiyun opp-supported-hw = <0x7>; 579*4882a593Smuzhiyun clock-latency-ns = <200000>; 580*4882a593Smuzhiyun }; 581*4882a593Smuzhiyun opp-1747200000 { 582*4882a593Smuzhiyun opp-hz = /bits/ 64 <1747200000>; 583*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 584*4882a593Smuzhiyun opp-supported-hw = <0x70>; 585*4882a593Smuzhiyun clock-latency-ns = <200000>; 586*4882a593Smuzhiyun }; 587*4882a593Smuzhiyun opp-1785600000 { 588*4882a593Smuzhiyun opp-hz = /bits/ 64 <1785600000>; 589*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 590*4882a593Smuzhiyun opp-supported-hw = <0x7>; 591*4882a593Smuzhiyun clock-latency-ns = <200000>; 592*4882a593Smuzhiyun }; 593*4882a593Smuzhiyun opp-1804800000 { 594*4882a593Smuzhiyun opp-hz = /bits/ 64 <1804800000>; 595*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 596*4882a593Smuzhiyun opp-supported-hw = <0x6>; 597*4882a593Smuzhiyun clock-latency-ns = <200000>; 598*4882a593Smuzhiyun }; 599*4882a593Smuzhiyun opp-1824000000 { 600*4882a593Smuzhiyun opp-hz = /bits/ 64 <1824000000>; 601*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 602*4882a593Smuzhiyun opp-supported-hw = <0x71>; 603*4882a593Smuzhiyun clock-latency-ns = <200000>; 604*4882a593Smuzhiyun }; 605*4882a593Smuzhiyun opp-1900800000 { 606*4882a593Smuzhiyun opp-hz = /bits/ 64 <1900800000>; 607*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 608*4882a593Smuzhiyun opp-supported-hw = <0x74>; 609*4882a593Smuzhiyun clock-latency-ns = <200000>; 610*4882a593Smuzhiyun }; 611*4882a593Smuzhiyun opp-1920000000 { 612*4882a593Smuzhiyun opp-hz = /bits/ 64 <1920000000>; 613*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 614*4882a593Smuzhiyun opp-supported-hw = <0x1>; 615*4882a593Smuzhiyun clock-latency-ns = <200000>; 616*4882a593Smuzhiyun }; 617*4882a593Smuzhiyun opp-1977600000 { 618*4882a593Smuzhiyun opp-hz = /bits/ 64 <1977600000>; 619*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 620*4882a593Smuzhiyun opp-supported-hw = <0x30>; 621*4882a593Smuzhiyun clock-latency-ns = <200000>; 622*4882a593Smuzhiyun }; 623*4882a593Smuzhiyun opp-1996800000 { 624*4882a593Smuzhiyun opp-hz = /bits/ 64 <1996800000>; 625*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 626*4882a593Smuzhiyun opp-supported-hw = <0x1>; 627*4882a593Smuzhiyun clock-latency-ns = <200000>; 628*4882a593Smuzhiyun }; 629*4882a593Smuzhiyun opp-2054400000 { 630*4882a593Smuzhiyun opp-hz = /bits/ 64 <2054400000>; 631*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 632*4882a593Smuzhiyun opp-supported-hw = <0x30>; 633*4882a593Smuzhiyun clock-latency-ns = <200000>; 634*4882a593Smuzhiyun }; 635*4882a593Smuzhiyun opp-2073600000 { 636*4882a593Smuzhiyun opp-hz = /bits/ 64 <2073600000>; 637*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 638*4882a593Smuzhiyun opp-supported-hw = <0x1>; 639*4882a593Smuzhiyun clock-latency-ns = <200000>; 640*4882a593Smuzhiyun }; 641*4882a593Smuzhiyun opp-2150400000 { 642*4882a593Smuzhiyun opp-hz = /bits/ 64 <2150400000>; 643*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 644*4882a593Smuzhiyun opp-supported-hw = <0x31>; 645*4882a593Smuzhiyun clock-latency-ns = <200000>; 646*4882a593Smuzhiyun }; 647*4882a593Smuzhiyun opp-2246400000 { 648*4882a593Smuzhiyun opp-hz = /bits/ 64 <2246400000>; 649*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 650*4882a593Smuzhiyun opp-supported-hw = <0x10>; 651*4882a593Smuzhiyun clock-latency-ns = <200000>; 652*4882a593Smuzhiyun }; 653*4882a593Smuzhiyun opp-2342400000 { 654*4882a593Smuzhiyun opp-hz = /bits/ 64 <2342400000>; 655*4882a593Smuzhiyun opp-microvolt = <1140000 905000 1140000>; 656*4882a593Smuzhiyun opp-supported-hw = <0x10>; 657*4882a593Smuzhiyun clock-latency-ns = <200000>; 658*4882a593Smuzhiyun }; 659*4882a593Smuzhiyun }; 660*4882a593Smuzhiyun 661*4882a593Smuzhiyun.... 662*4882a593Smuzhiyun 663*4882a593Smuzhiyunreserved-memory { 664*4882a593Smuzhiyun #address-cells = <2>; 665*4882a593Smuzhiyun #size-cells = <2>; 666*4882a593Smuzhiyun ranges; 667*4882a593Smuzhiyun.... 668*4882a593Smuzhiyun smem_mem: smem-mem@86000000 { 669*4882a593Smuzhiyun reg = <0x0 0x86000000 0x0 0x200000>; 670*4882a593Smuzhiyun no-map; 671*4882a593Smuzhiyun }; 672*4882a593Smuzhiyun.... 673*4882a593Smuzhiyun}; 674*4882a593Smuzhiyun 675*4882a593Smuzhiyunsmem { 676*4882a593Smuzhiyun compatible = "qcom,smem"; 677*4882a593Smuzhiyun memory-region = <&smem_mem>; 678*4882a593Smuzhiyun hwlocks = <&tcsr_mutex 3>; 679*4882a593Smuzhiyun}; 680*4882a593Smuzhiyun 681*4882a593Smuzhiyunsoc { 682*4882a593Smuzhiyun.... 683*4882a593Smuzhiyun qfprom: qfprom@74000 { 684*4882a593Smuzhiyun compatible = "qcom,qfprom"; 685*4882a593Smuzhiyun reg = <0x00074000 0x8ff>; 686*4882a593Smuzhiyun #address-cells = <1>; 687*4882a593Smuzhiyun #size-cells = <1>; 688*4882a593Smuzhiyun .... 689*4882a593Smuzhiyun speedbin_efuse: speedbin@133 { 690*4882a593Smuzhiyun reg = <0x133 0x1>; 691*4882a593Smuzhiyun bits = <5 3>; 692*4882a593Smuzhiyun }; 693*4882a593Smuzhiyun }; 694*4882a593Smuzhiyun}; 695*4882a593Smuzhiyun 696*4882a593SmuzhiyunExample 2: 697*4882a593Smuzhiyun--------- 698*4882a593Smuzhiyun 699*4882a593Smuzhiyun cpus { 700*4882a593Smuzhiyun #address-cells = <1>; 701*4882a593Smuzhiyun #size-cells = <0>; 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun CPU0: cpu@100 { 704*4882a593Smuzhiyun device_type = "cpu"; 705*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 706*4882a593Smuzhiyun reg = <0x100>; 707*4882a593Smuzhiyun .... 708*4882a593Smuzhiyun clocks = <&apcs_glb>; 709*4882a593Smuzhiyun operating-points-v2 = <&cpu_opp_table>; 710*4882a593Smuzhiyun power-domains = <&cpr>; 711*4882a593Smuzhiyun power-domain-names = "cpr"; 712*4882a593Smuzhiyun }; 713*4882a593Smuzhiyun 714*4882a593Smuzhiyun CPU1: cpu@101 { 715*4882a593Smuzhiyun device_type = "cpu"; 716*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 717*4882a593Smuzhiyun reg = <0x101>; 718*4882a593Smuzhiyun .... 719*4882a593Smuzhiyun clocks = <&apcs_glb>; 720*4882a593Smuzhiyun operating-points-v2 = <&cpu_opp_table>; 721*4882a593Smuzhiyun power-domains = <&cpr>; 722*4882a593Smuzhiyun power-domain-names = "cpr"; 723*4882a593Smuzhiyun }; 724*4882a593Smuzhiyun 725*4882a593Smuzhiyun CPU2: cpu@102 { 726*4882a593Smuzhiyun device_type = "cpu"; 727*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 728*4882a593Smuzhiyun reg = <0x102>; 729*4882a593Smuzhiyun .... 730*4882a593Smuzhiyun clocks = <&apcs_glb>; 731*4882a593Smuzhiyun operating-points-v2 = <&cpu_opp_table>; 732*4882a593Smuzhiyun power-domains = <&cpr>; 733*4882a593Smuzhiyun power-domain-names = "cpr"; 734*4882a593Smuzhiyun }; 735*4882a593Smuzhiyun 736*4882a593Smuzhiyun CPU3: cpu@103 { 737*4882a593Smuzhiyun device_type = "cpu"; 738*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 739*4882a593Smuzhiyun reg = <0x103>; 740*4882a593Smuzhiyun .... 741*4882a593Smuzhiyun clocks = <&apcs_glb>; 742*4882a593Smuzhiyun operating-points-v2 = <&cpu_opp_table>; 743*4882a593Smuzhiyun power-domains = <&cpr>; 744*4882a593Smuzhiyun power-domain-names = "cpr"; 745*4882a593Smuzhiyun }; 746*4882a593Smuzhiyun }; 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun cpu_opp_table: cpu-opp-table { 749*4882a593Smuzhiyun compatible = "operating-points-v2-kryo-cpu"; 750*4882a593Smuzhiyun opp-shared; 751*4882a593Smuzhiyun 752*4882a593Smuzhiyun opp-1094400000 { 753*4882a593Smuzhiyun opp-hz = /bits/ 64 <1094400000>; 754*4882a593Smuzhiyun required-opps = <&cpr_opp1>; 755*4882a593Smuzhiyun }; 756*4882a593Smuzhiyun opp-1248000000 { 757*4882a593Smuzhiyun opp-hz = /bits/ 64 <1248000000>; 758*4882a593Smuzhiyun required-opps = <&cpr_opp2>; 759*4882a593Smuzhiyun }; 760*4882a593Smuzhiyun opp-1401600000 { 761*4882a593Smuzhiyun opp-hz = /bits/ 64 <1401600000>; 762*4882a593Smuzhiyun required-opps = <&cpr_opp3>; 763*4882a593Smuzhiyun }; 764*4882a593Smuzhiyun }; 765*4882a593Smuzhiyun 766*4882a593Smuzhiyun cpr_opp_table: cpr-opp-table { 767*4882a593Smuzhiyun compatible = "operating-points-v2-qcom-level"; 768*4882a593Smuzhiyun 769*4882a593Smuzhiyun cpr_opp1: opp1 { 770*4882a593Smuzhiyun opp-level = <1>; 771*4882a593Smuzhiyun qcom,opp-fuse-level = <1>; 772*4882a593Smuzhiyun }; 773*4882a593Smuzhiyun cpr_opp2: opp2 { 774*4882a593Smuzhiyun opp-level = <2>; 775*4882a593Smuzhiyun qcom,opp-fuse-level = <2>; 776*4882a593Smuzhiyun }; 777*4882a593Smuzhiyun cpr_opp3: opp3 { 778*4882a593Smuzhiyun opp-level = <3>; 779*4882a593Smuzhiyun qcom,opp-fuse-level = <3>; 780*4882a593Smuzhiyun }; 781*4882a593Smuzhiyun }; 782*4882a593Smuzhiyun 783*4882a593Smuzhiyun.... 784*4882a593Smuzhiyun 785*4882a593Smuzhiyunsoc { 786*4882a593Smuzhiyun.... 787*4882a593Smuzhiyun cpr: power-controller@b018000 { 788*4882a593Smuzhiyun compatible = "qcom,qcs404-cpr", "qcom,cpr"; 789*4882a593Smuzhiyun reg = <0x0b018000 0x1000>; 790*4882a593Smuzhiyun .... 791*4882a593Smuzhiyun vdd-apc-supply = <&pms405_s3>; 792*4882a593Smuzhiyun #power-domain-cells = <0>; 793*4882a593Smuzhiyun operating-points-v2 = <&cpr_opp_table>; 794*4882a593Smuzhiyun .... 795*4882a593Smuzhiyun }; 796*4882a593Smuzhiyun}; 797