xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/opp/opp.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunGeneric OPP (Operating Performance Points) Bindings
2*4882a593Smuzhiyun----------------------------------------------------
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunDevices work at voltage-current-frequency combinations and some implementations
5*4882a593Smuzhiyunhave the liberty of choosing these. These combinations are called Operating
6*4882a593SmuzhiyunPerformance Points aka OPPs. This document defines bindings for these OPPs
7*4882a593Smuzhiyunapplicable across wide range of devices. For illustration purpose, this document
8*4882a593Smuzhiyunuses CPU as a device.
9*4882a593Smuzhiyun
10*4882a593SmuzhiyunThis document contain multiple versions of OPP binding and only one of them
11*4882a593Smuzhiyunshould be used per device.
12*4882a593Smuzhiyun
13*4882a593SmuzhiyunBinding 1: operating-points
14*4882a593Smuzhiyun============================
15*4882a593Smuzhiyun
16*4882a593SmuzhiyunThis binding only supports voltage-frequency pairs.
17*4882a593Smuzhiyun
18*4882a593SmuzhiyunProperties:
19*4882a593Smuzhiyun- operating-points: An array of 2-tuples items, and each item consists
20*4882a593Smuzhiyun  of frequency and voltage like <freq-kHz vol-uV>.
21*4882a593Smuzhiyun	freq: clock frequency in kHz
22*4882a593Smuzhiyun	vol: voltage in microvolt
23*4882a593Smuzhiyun
24*4882a593SmuzhiyunExamples:
25*4882a593Smuzhiyun
26*4882a593Smuzhiyuncpu@0 {
27*4882a593Smuzhiyun	compatible = "arm,cortex-a9";
28*4882a593Smuzhiyun	reg = <0>;
29*4882a593Smuzhiyun	next-level-cache = <&L2>;
30*4882a593Smuzhiyun	operating-points = <
31*4882a593Smuzhiyun		/* kHz    uV */
32*4882a593Smuzhiyun		792000  1100000
33*4882a593Smuzhiyun		396000  950000
34*4882a593Smuzhiyun		198000  850000
35*4882a593Smuzhiyun	>;
36*4882a593Smuzhiyun};
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun
39*4882a593SmuzhiyunBinding 2: operating-points-v2
40*4882a593Smuzhiyun============================
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun* Property: operating-points-v2
43*4882a593Smuzhiyun
44*4882a593SmuzhiyunDevices supporting OPPs must set their "operating-points-v2" property with
45*4882a593Smuzhiyunphandle to a OPP table in their DT node. The OPP core will use this phandle to
46*4882a593Smuzhiyunfind the operating points for the device.
47*4882a593Smuzhiyun
48*4882a593SmuzhiyunThis can contain more than one phandle for power domain providers that provide
49*4882a593Smuzhiyunmultiple power domains. That is, one phandle for each power domain. If only one
50*4882a593Smuzhiyunphandle is available, then the same OPP table will be used for all power domains
51*4882a593Smuzhiyunprovided by the power domain provider.
52*4882a593Smuzhiyun
53*4882a593SmuzhiyunIf required, this can be extended for SoC vendor specific bindings. Such bindings
54*4882a593Smuzhiyunshould be documented as Documentation/devicetree/bindings/power/<vendor>-opp.txt
55*4882a593Smuzhiyunand should have a compatible description like: "operating-points-v2-<vendor>".
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun* OPP Table Node
58*4882a593Smuzhiyun
59*4882a593SmuzhiyunThis describes the OPPs belonging to a device. This node can have following
60*4882a593Smuzhiyunproperties:
61*4882a593Smuzhiyun
62*4882a593SmuzhiyunRequired properties:
63*4882a593Smuzhiyun- compatible: Allow OPPs to express their compatibility. It should be:
64*4882a593Smuzhiyun  "operating-points-v2".
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun- OPP nodes: One or more OPP nodes describing voltage-current-frequency
67*4882a593Smuzhiyun  combinations. Their name isn't significant but their phandle can be used to
68*4882a593Smuzhiyun  reference an OPP.
69*4882a593Smuzhiyun
70*4882a593SmuzhiyunOptional properties:
71*4882a593Smuzhiyun- opp-shared: Indicates that device nodes using this OPP Table Node's phandle
72*4882a593Smuzhiyun  switch their DVFS state together, i.e. they share clock/voltage/current lines.
73*4882a593Smuzhiyun  Missing property means devices have independent clock/voltage/current lines,
74*4882a593Smuzhiyun  but they share OPP tables.
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun- status: Marks the OPP table enabled/disabled.
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun* OPP Node
80*4882a593Smuzhiyun
81*4882a593SmuzhiyunThis defines voltage-current-frequency combinations along with other related
82*4882a593Smuzhiyunproperties.
83*4882a593Smuzhiyun
84*4882a593SmuzhiyunRequired properties:
85*4882a593Smuzhiyun- opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer. This is a
86*4882a593Smuzhiyun  required property for all device nodes, unless another "required" property to
87*4882a593Smuzhiyun  uniquely identify the OPP nodes exists. Devices like power domains must have
88*4882a593Smuzhiyun  another (implementation dependent) property.
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun- opp-peak-kBps: Peak bandwidth in kilobytes per second, expressed as an array
91*4882a593Smuzhiyun  of 32-bit big-endian integers. Each element of the array represents the
92*4882a593Smuzhiyun  peak bandwidth value of each interconnect path. The number of elements should
93*4882a593Smuzhiyun  match the number of interconnect paths.
94*4882a593Smuzhiyun
95*4882a593SmuzhiyunOptional properties:
96*4882a593Smuzhiyun- opp-microvolt: voltage in micro Volts.
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun  A single regulator's voltage is specified with an array of size one or three.
99*4882a593Smuzhiyun  Single entry is for target voltage and three entries are for <target min max>
100*4882a593Smuzhiyun  voltages.
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun  Entries for multiple regulators shall be provided in the same field separated
103*4882a593Smuzhiyun  by angular brackets <>. The OPP binding doesn't provide any provisions to
104*4882a593Smuzhiyun  relate the values to their power supplies or the order in which the supplies
105*4882a593Smuzhiyun  need to be configured and that is left for the implementation specific
106*4882a593Smuzhiyun  binding.
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun  Entries for all regulators shall be of the same size, i.e. either all use a
109*4882a593Smuzhiyun  single value or triplets.
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun- opp-microvolt-<name>: Named opp-microvolt property. This is exactly similar to
112*4882a593Smuzhiyun  the above opp-microvolt property, but allows multiple voltage ranges to be
113*4882a593Smuzhiyun  provided for the same OPP. At runtime, the platform can pick a <name> and
114*4882a593Smuzhiyun  matching opp-microvolt-<name> property will be enabled for all OPPs. If the
115*4882a593Smuzhiyun  platform doesn't pick a specific <name> or the <name> doesn't match with any
116*4882a593Smuzhiyun  opp-microvolt-<name> properties, then opp-microvolt property shall be used, if
117*4882a593Smuzhiyun  present.
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun- opp-microamp: The maximum current drawn by the device in microamperes
120*4882a593Smuzhiyun  considering system specific parameters (such as transients, process, aging,
121*4882a593Smuzhiyun  maximum operating temperature range etc.) as necessary. This may be used to
122*4882a593Smuzhiyun  set the most efficient regulator operating mode.
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun  Should only be set if opp-microvolt is set for the OPP.
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun  Entries for multiple regulators shall be provided in the same field separated
127*4882a593Smuzhiyun  by angular brackets <>. If current values aren't required for a regulator,
128*4882a593Smuzhiyun  then it shall be filled with 0. If current values aren't required for any of
129*4882a593Smuzhiyun  the regulators, then this field is not required. The OPP binding doesn't
130*4882a593Smuzhiyun  provide any provisions to relate the values to their power supplies or the
131*4882a593Smuzhiyun  order in which the supplies need to be configured and that is left for the
132*4882a593Smuzhiyun  implementation specific binding.
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun- opp-microamp-<name>: Named opp-microamp property. Similar to
135*4882a593Smuzhiyun  opp-microvolt-<name> property, but for microamp instead.
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun- opp-level: A value representing the performance level of the device,
138*4882a593Smuzhiyun  expressed as a 32-bit integer.
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun- opp-avg-kBps: Average bandwidth in kilobytes per second, expressed as an array
141*4882a593Smuzhiyun  of 32-bit big-endian integers. Each element of the array represents the
142*4882a593Smuzhiyun  average bandwidth value of each interconnect path. The number of elements
143*4882a593Smuzhiyun  should match the number of interconnect paths. This property is only
144*4882a593Smuzhiyun  meaningful in OPP tables where opp-peak-kBps is present.
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun- clock-latency-ns: Specifies the maximum possible transition latency (in
147*4882a593Smuzhiyun  nanoseconds) for switching to this OPP from any other OPP.
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun- turbo-mode: Marks the OPP to be used only for turbo modes. Turbo mode is
150*4882a593Smuzhiyun  available on some platforms, where the device can run over its operating
151*4882a593Smuzhiyun  frequency for a short duration of time limited by the device's power, current
152*4882a593Smuzhiyun  and thermal limits.
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun- opp-suspend: Marks the OPP to be used during device suspend. If multiple OPPs
155*4882a593Smuzhiyun  in the table have this, the OPP with highest opp-hz will be used.
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun- opp-supported-hw: This property allows a platform to enable only a subset of
158*4882a593Smuzhiyun  the OPPs from the larger set present in the OPP table, based on the current
159*4882a593Smuzhiyun  version of the hardware (already known to the operating system).
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun  Each block present in the array of blocks in this property, represents a
162*4882a593Smuzhiyun  sub-group of hardware versions supported by the OPP. i.e. <sub-group A>,
163*4882a593Smuzhiyun  <sub-group B>, etc. The OPP will be enabled if _any_ of these sub-groups match
164*4882a593Smuzhiyun  the hardware's version.
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun  Each sub-group is a platform defined array representing the hierarchy of
167*4882a593Smuzhiyun  hardware versions supported by the platform. For a platform with three
168*4882a593Smuzhiyun  hierarchical levels of version (X.Y.Z), this field shall look like
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun  opp-supported-hw = <X1 Y1 Z1>, <X2 Y2 Z2>, <X3 Y3 Z3>.
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun  Each level (eg. X1) in version hierarchy is represented by a 32 bit value, one
173*4882a593Smuzhiyun  bit per version and so there can be maximum 32 versions per level. Logical AND
174*4882a593Smuzhiyun  (&) operation is performed for each level with the hardware's level version
175*4882a593Smuzhiyun  and a non-zero output for _all_ the levels in a sub-group means the OPP is
176*4882a593Smuzhiyun  supported by hardware. A value of 0xFFFFFFFF for each level in the sub-group
177*4882a593Smuzhiyun  will enable the OPP for all versions for the hardware.
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun- status: Marks the node enabled/disabled.
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun- required-opps: This contains phandle to an OPP node in another device's OPP
182*4882a593Smuzhiyun  table. It may contain an array of phandles, where each phandle points to an
183*4882a593Smuzhiyun  OPP of a different device. It should not contain multiple phandles to the OPP
184*4882a593Smuzhiyun  nodes in the same OPP table. This specifies the minimum required OPP of the
185*4882a593Smuzhiyun  device(s), whose OPP's phandle is present in this property, for the
186*4882a593Smuzhiyun  functioning of the current device at the current OPP (where this property is
187*4882a593Smuzhiyun  present).
188*4882a593Smuzhiyun
189*4882a593SmuzhiyunExample 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together.
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun/ {
192*4882a593Smuzhiyun	cpus {
193*4882a593Smuzhiyun		#address-cells = <1>;
194*4882a593Smuzhiyun		#size-cells = <0>;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun		cpu@0 {
197*4882a593Smuzhiyun			compatible = "arm,cortex-a9";
198*4882a593Smuzhiyun			reg = <0>;
199*4882a593Smuzhiyun			next-level-cache = <&L2>;
200*4882a593Smuzhiyun			clocks = <&clk_controller 0>;
201*4882a593Smuzhiyun			clock-names = "cpu";
202*4882a593Smuzhiyun			cpu-supply = <&cpu_supply0>;
203*4882a593Smuzhiyun			operating-points-v2 = <&cpu0_opp_table>;
204*4882a593Smuzhiyun		};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun		cpu@1 {
207*4882a593Smuzhiyun			compatible = "arm,cortex-a9";
208*4882a593Smuzhiyun			reg = <1>;
209*4882a593Smuzhiyun			next-level-cache = <&L2>;
210*4882a593Smuzhiyun			clocks = <&clk_controller 0>;
211*4882a593Smuzhiyun			clock-names = "cpu";
212*4882a593Smuzhiyun			cpu-supply = <&cpu_supply0>;
213*4882a593Smuzhiyun			operating-points-v2 = <&cpu0_opp_table>;
214*4882a593Smuzhiyun		};
215*4882a593Smuzhiyun	};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun	cpu0_opp_table: opp_table0 {
218*4882a593Smuzhiyun		compatible = "operating-points-v2";
219*4882a593Smuzhiyun		opp-shared;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun		opp-1000000000 {
222*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1000000000>;
223*4882a593Smuzhiyun			opp-microvolt = <975000 970000 985000>;
224*4882a593Smuzhiyun			opp-microamp = <70000>;
225*4882a593Smuzhiyun			clock-latency-ns = <300000>;
226*4882a593Smuzhiyun			opp-suspend;
227*4882a593Smuzhiyun		};
228*4882a593Smuzhiyun		opp-1100000000 {
229*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1100000000>;
230*4882a593Smuzhiyun			opp-microvolt = <1000000 980000 1010000>;
231*4882a593Smuzhiyun			opp-microamp = <80000>;
232*4882a593Smuzhiyun			clock-latency-ns = <310000>;
233*4882a593Smuzhiyun		};
234*4882a593Smuzhiyun		opp-1200000000 {
235*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1200000000>;
236*4882a593Smuzhiyun			opp-microvolt = <1025000>;
237*4882a593Smuzhiyun			clock-latency-ns = <290000>;
238*4882a593Smuzhiyun			turbo-mode;
239*4882a593Smuzhiyun		};
240*4882a593Smuzhiyun	};
241*4882a593Smuzhiyun};
242*4882a593Smuzhiyun
243*4882a593SmuzhiyunExample 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states
244*4882a593Smuzhiyunindependently.
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun/ {
247*4882a593Smuzhiyun	cpus {
248*4882a593Smuzhiyun		#address-cells = <1>;
249*4882a593Smuzhiyun		#size-cells = <0>;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun		cpu@0 {
252*4882a593Smuzhiyun			compatible = "qcom,krait";
253*4882a593Smuzhiyun			reg = <0>;
254*4882a593Smuzhiyun			next-level-cache = <&L2>;
255*4882a593Smuzhiyun			clocks = <&clk_controller 0>;
256*4882a593Smuzhiyun			clock-names = "cpu";
257*4882a593Smuzhiyun			cpu-supply = <&cpu_supply0>;
258*4882a593Smuzhiyun			operating-points-v2 = <&cpu_opp_table>;
259*4882a593Smuzhiyun		};
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun		cpu@1 {
262*4882a593Smuzhiyun			compatible = "qcom,krait";
263*4882a593Smuzhiyun			reg = <1>;
264*4882a593Smuzhiyun			next-level-cache = <&L2>;
265*4882a593Smuzhiyun			clocks = <&clk_controller 1>;
266*4882a593Smuzhiyun			clock-names = "cpu";
267*4882a593Smuzhiyun			cpu-supply = <&cpu_supply1>;
268*4882a593Smuzhiyun			operating-points-v2 = <&cpu_opp_table>;
269*4882a593Smuzhiyun		};
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun		cpu@2 {
272*4882a593Smuzhiyun			compatible = "qcom,krait";
273*4882a593Smuzhiyun			reg = <2>;
274*4882a593Smuzhiyun			next-level-cache = <&L2>;
275*4882a593Smuzhiyun			clocks = <&clk_controller 2>;
276*4882a593Smuzhiyun			clock-names = "cpu";
277*4882a593Smuzhiyun			cpu-supply = <&cpu_supply2>;
278*4882a593Smuzhiyun			operating-points-v2 = <&cpu_opp_table>;
279*4882a593Smuzhiyun		};
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun		cpu@3 {
282*4882a593Smuzhiyun			compatible = "qcom,krait";
283*4882a593Smuzhiyun			reg = <3>;
284*4882a593Smuzhiyun			next-level-cache = <&L2>;
285*4882a593Smuzhiyun			clocks = <&clk_controller 3>;
286*4882a593Smuzhiyun			clock-names = "cpu";
287*4882a593Smuzhiyun			cpu-supply = <&cpu_supply3>;
288*4882a593Smuzhiyun			operating-points-v2 = <&cpu_opp_table>;
289*4882a593Smuzhiyun		};
290*4882a593Smuzhiyun	};
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun	cpu_opp_table: opp_table {
293*4882a593Smuzhiyun		compatible = "operating-points-v2";
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun		/*
296*4882a593Smuzhiyun		 * Missing opp-shared property means CPUs switch DVFS states
297*4882a593Smuzhiyun		 * independently.
298*4882a593Smuzhiyun		 */
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun		opp-1000000000 {
301*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1000000000>;
302*4882a593Smuzhiyun			opp-microvolt = <975000 970000 985000>;
303*4882a593Smuzhiyun			opp-microamp = <70000>;
304*4882a593Smuzhiyun			clock-latency-ns = <300000>;
305*4882a593Smuzhiyun			opp-suspend;
306*4882a593Smuzhiyun		};
307*4882a593Smuzhiyun		opp-1100000000 {
308*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1100000000>;
309*4882a593Smuzhiyun			opp-microvolt = <1000000 980000 1010000>;
310*4882a593Smuzhiyun			opp-microamp = <80000>;
311*4882a593Smuzhiyun			clock-latency-ns = <310000>;
312*4882a593Smuzhiyun		};
313*4882a593Smuzhiyun		opp-1200000000 {
314*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1200000000>;
315*4882a593Smuzhiyun			opp-microvolt = <1025000>;
316*4882a593Smuzhiyun			opp-microamp = <90000;
317*4882a593Smuzhiyun			lock-latency-ns = <290000>;
318*4882a593Smuzhiyun			turbo-mode;
319*4882a593Smuzhiyun		};
320*4882a593Smuzhiyun	};
321*4882a593Smuzhiyun};
322*4882a593Smuzhiyun
323*4882a593SmuzhiyunExample 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch
324*4882a593SmuzhiyunDVFS state together.
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun/ {
327*4882a593Smuzhiyun	cpus {
328*4882a593Smuzhiyun		#address-cells = <1>;
329*4882a593Smuzhiyun		#size-cells = <0>;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun		cpu@0 {
332*4882a593Smuzhiyun			compatible = "arm,cortex-a7";
333*4882a593Smuzhiyun			reg = <0>;
334*4882a593Smuzhiyun			next-level-cache = <&L2>;
335*4882a593Smuzhiyun			clocks = <&clk_controller 0>;
336*4882a593Smuzhiyun			clock-names = "cpu";
337*4882a593Smuzhiyun			cpu-supply = <&cpu_supply0>;
338*4882a593Smuzhiyun			operating-points-v2 = <&cluster0_opp>;
339*4882a593Smuzhiyun		};
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun		cpu@1 {
342*4882a593Smuzhiyun			compatible = "arm,cortex-a7";
343*4882a593Smuzhiyun			reg = <1>;
344*4882a593Smuzhiyun			next-level-cache = <&L2>;
345*4882a593Smuzhiyun			clocks = <&clk_controller 0>;
346*4882a593Smuzhiyun			clock-names = "cpu";
347*4882a593Smuzhiyun			cpu-supply = <&cpu_supply0>;
348*4882a593Smuzhiyun			operating-points-v2 = <&cluster0_opp>;
349*4882a593Smuzhiyun		};
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun		cpu@100 {
352*4882a593Smuzhiyun			compatible = "arm,cortex-a15";
353*4882a593Smuzhiyun			reg = <100>;
354*4882a593Smuzhiyun			next-level-cache = <&L2>;
355*4882a593Smuzhiyun			clocks = <&clk_controller 1>;
356*4882a593Smuzhiyun			clock-names = "cpu";
357*4882a593Smuzhiyun			cpu-supply = <&cpu_supply1>;
358*4882a593Smuzhiyun			operating-points-v2 = <&cluster1_opp>;
359*4882a593Smuzhiyun		};
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun		cpu@101 {
362*4882a593Smuzhiyun			compatible = "arm,cortex-a15";
363*4882a593Smuzhiyun			reg = <101>;
364*4882a593Smuzhiyun			next-level-cache = <&L2>;
365*4882a593Smuzhiyun			clocks = <&clk_controller 1>;
366*4882a593Smuzhiyun			clock-names = "cpu";
367*4882a593Smuzhiyun			cpu-supply = <&cpu_supply1>;
368*4882a593Smuzhiyun			operating-points-v2 = <&cluster1_opp>;
369*4882a593Smuzhiyun		};
370*4882a593Smuzhiyun	};
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun	cluster0_opp: opp_table0 {
373*4882a593Smuzhiyun		compatible = "operating-points-v2";
374*4882a593Smuzhiyun		opp-shared;
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun		opp-1000000000 {
377*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1000000000>;
378*4882a593Smuzhiyun			opp-microvolt = <975000 970000 985000>;
379*4882a593Smuzhiyun			opp-microamp = <70000>;
380*4882a593Smuzhiyun			clock-latency-ns = <300000>;
381*4882a593Smuzhiyun			opp-suspend;
382*4882a593Smuzhiyun		};
383*4882a593Smuzhiyun		opp-1100000000 {
384*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1100000000>;
385*4882a593Smuzhiyun			opp-microvolt = <1000000 980000 1010000>;
386*4882a593Smuzhiyun			opp-microamp = <80000>;
387*4882a593Smuzhiyun			clock-latency-ns = <310000>;
388*4882a593Smuzhiyun		};
389*4882a593Smuzhiyun		opp-1200000000 {
390*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1200000000>;
391*4882a593Smuzhiyun			opp-microvolt = <1025000>;
392*4882a593Smuzhiyun			opp-microamp = <90000>;
393*4882a593Smuzhiyun			clock-latency-ns = <290000>;
394*4882a593Smuzhiyun			turbo-mode;
395*4882a593Smuzhiyun		};
396*4882a593Smuzhiyun	};
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun	cluster1_opp: opp_table1 {
399*4882a593Smuzhiyun		compatible = "operating-points-v2";
400*4882a593Smuzhiyun		opp-shared;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun		opp-1300000000 {
403*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1300000000>;
404*4882a593Smuzhiyun			opp-microvolt = <1050000 1045000 1055000>;
405*4882a593Smuzhiyun			opp-microamp = <95000>;
406*4882a593Smuzhiyun			clock-latency-ns = <400000>;
407*4882a593Smuzhiyun			opp-suspend;
408*4882a593Smuzhiyun		};
409*4882a593Smuzhiyun		opp-1400000000 {
410*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1400000000>;
411*4882a593Smuzhiyun			opp-microvolt = <1075000>;
412*4882a593Smuzhiyun			opp-microamp = <100000>;
413*4882a593Smuzhiyun			clock-latency-ns = <400000>;
414*4882a593Smuzhiyun		};
415*4882a593Smuzhiyun		opp-1500000000 {
416*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1500000000>;
417*4882a593Smuzhiyun			opp-microvolt = <1100000 1010000 1110000>;
418*4882a593Smuzhiyun			opp-microamp = <95000>;
419*4882a593Smuzhiyun			clock-latency-ns = <400000>;
420*4882a593Smuzhiyun			turbo-mode;
421*4882a593Smuzhiyun		};
422*4882a593Smuzhiyun	};
423*4882a593Smuzhiyun};
424*4882a593Smuzhiyun
425*4882a593SmuzhiyunExample 4: Handling multiple regulators
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun/ {
428*4882a593Smuzhiyun	cpus {
429*4882a593Smuzhiyun		cpu@0 {
430*4882a593Smuzhiyun			compatible = "vendor,cpu-type";
431*4882a593Smuzhiyun			...
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun			vcc0-supply = <&cpu_supply0>;
434*4882a593Smuzhiyun			vcc1-supply = <&cpu_supply1>;
435*4882a593Smuzhiyun			vcc2-supply = <&cpu_supply2>;
436*4882a593Smuzhiyun			operating-points-v2 = <&cpu0_opp_table>;
437*4882a593Smuzhiyun		};
438*4882a593Smuzhiyun	};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun	cpu0_opp_table: opp_table0 {
441*4882a593Smuzhiyun		compatible = "operating-points-v2";
442*4882a593Smuzhiyun		opp-shared;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun		opp-1000000000 {
445*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1000000000>;
446*4882a593Smuzhiyun			opp-microvolt = <970000>, /* Supply 0 */
447*4882a593Smuzhiyun					<960000>, /* Supply 1 */
448*4882a593Smuzhiyun					<960000>; /* Supply 2 */
449*4882a593Smuzhiyun			opp-microamp =  <70000>,  /* Supply 0 */
450*4882a593Smuzhiyun					<70000>,  /* Supply 1 */
451*4882a593Smuzhiyun					<70000>;  /* Supply 2 */
452*4882a593Smuzhiyun			clock-latency-ns = <300000>;
453*4882a593Smuzhiyun		};
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun		/* OR */
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun		opp-1000000000 {
458*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1000000000>;
459*4882a593Smuzhiyun			opp-microvolt = <975000 970000 985000>, /* Supply 0 */
460*4882a593Smuzhiyun					<965000 960000 975000>, /* Supply 1 */
461*4882a593Smuzhiyun					<965000 960000 975000>; /* Supply 2 */
462*4882a593Smuzhiyun			opp-microamp =  <70000>,		/* Supply 0 */
463*4882a593Smuzhiyun					<70000>,		/* Supply 1 */
464*4882a593Smuzhiyun					<70000>;		/* Supply 2 */
465*4882a593Smuzhiyun			clock-latency-ns = <300000>;
466*4882a593Smuzhiyun		};
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun		/* OR */
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun		opp-1000000000 {
471*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1000000000>;
472*4882a593Smuzhiyun			opp-microvolt = <975000 970000 985000>, /* Supply 0 */
473*4882a593Smuzhiyun					<965000 960000 975000>, /* Supply 1 */
474*4882a593Smuzhiyun					<965000 960000 975000>; /* Supply 2 */
475*4882a593Smuzhiyun			opp-microamp =  <70000>,		/* Supply 0 */
476*4882a593Smuzhiyun					<0>,			/* Supply 1 doesn't need this */
477*4882a593Smuzhiyun					<70000>;		/* Supply 2 */
478*4882a593Smuzhiyun			clock-latency-ns = <300000>;
479*4882a593Smuzhiyun		};
480*4882a593Smuzhiyun	};
481*4882a593Smuzhiyun};
482*4882a593Smuzhiyun
483*4882a593SmuzhiyunExample 5: opp-supported-hw
484*4882a593Smuzhiyun(example: three level hierarchy of versions: cuts, substrate and process)
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun/ {
487*4882a593Smuzhiyun	cpus {
488*4882a593Smuzhiyun		cpu@0 {
489*4882a593Smuzhiyun			compatible = "arm,cortex-a7";
490*4882a593Smuzhiyun			...
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun			cpu-supply = <&cpu_supply>
493*4882a593Smuzhiyun			operating-points-v2 = <&cpu0_opp_table_slow>;
494*4882a593Smuzhiyun		};
495*4882a593Smuzhiyun	};
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun	opp_table {
498*4882a593Smuzhiyun		compatible = "operating-points-v2";
499*4882a593Smuzhiyun		opp-shared;
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun		opp-600000000 {
502*4882a593Smuzhiyun			/*
503*4882a593Smuzhiyun			 * Supports all substrate and process versions for 0xF
504*4882a593Smuzhiyun			 * cuts, i.e. only first four cuts.
505*4882a593Smuzhiyun			 */
506*4882a593Smuzhiyun			opp-supported-hw = <0xF 0xFFFFFFFF 0xFFFFFFFF>
507*4882a593Smuzhiyun			opp-hz = /bits/ 64 <600000000>;
508*4882a593Smuzhiyun			...
509*4882a593Smuzhiyun		};
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun		opp-800000000 {
512*4882a593Smuzhiyun			/*
513*4882a593Smuzhiyun			 * Supports:
514*4882a593Smuzhiyun			 * - cuts: only one, 6th cut (represented by 6th bit).
515*4882a593Smuzhiyun			 * - substrate: supports 16 different substrate versions
516*4882a593Smuzhiyun			 * - process: supports 9 different process versions
517*4882a593Smuzhiyun			 */
518*4882a593Smuzhiyun			opp-supported-hw = <0x20 0xff0000ff 0x0000f4f0>
519*4882a593Smuzhiyun			opp-hz = /bits/ 64 <800000000>;
520*4882a593Smuzhiyun			...
521*4882a593Smuzhiyun		};
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun		opp-900000000 {
524*4882a593Smuzhiyun			/*
525*4882a593Smuzhiyun			 * Supports:
526*4882a593Smuzhiyun			 * - All cuts and substrate where process version is 0x2.
527*4882a593Smuzhiyun			 * - All cuts and process where substrate version is 0x2.
528*4882a593Smuzhiyun			 */
529*4882a593Smuzhiyun			opp-supported-hw = <0xFFFFFFFF 0xFFFFFFFF 0x02>, <0xFFFFFFFF 0x01 0xFFFFFFFF>
530*4882a593Smuzhiyun			opp-hz = /bits/ 64 <900000000>;
531*4882a593Smuzhiyun			...
532*4882a593Smuzhiyun		};
533*4882a593Smuzhiyun	};
534*4882a593Smuzhiyun};
535*4882a593Smuzhiyun
536*4882a593SmuzhiyunExample 6: opp-microvolt-<name>, opp-microamp-<name>:
537*4882a593Smuzhiyun(example: device with two possible microvolt ranges: slow and fast)
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun/ {
540*4882a593Smuzhiyun	cpus {
541*4882a593Smuzhiyun		cpu@0 {
542*4882a593Smuzhiyun			compatible = "arm,cortex-a7";
543*4882a593Smuzhiyun			...
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun			operating-points-v2 = <&cpu0_opp_table>;
546*4882a593Smuzhiyun		};
547*4882a593Smuzhiyun	};
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun	cpu0_opp_table: opp_table0 {
550*4882a593Smuzhiyun		compatible = "operating-points-v2";
551*4882a593Smuzhiyun		opp-shared;
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun		opp-1000000000 {
554*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1000000000>;
555*4882a593Smuzhiyun			opp-microvolt-slow = <915000 900000 925000>;
556*4882a593Smuzhiyun			opp-microvolt-fast = <975000 970000 985000>;
557*4882a593Smuzhiyun			opp-microamp-slow =  <70000>;
558*4882a593Smuzhiyun			opp-microamp-fast =  <71000>;
559*4882a593Smuzhiyun		};
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun		opp-1200000000 {
562*4882a593Smuzhiyun			opp-hz = /bits/ 64 <1200000000>;
563*4882a593Smuzhiyun			opp-microvolt-slow = <915000 900000 925000>, /* Supply vcc0 */
564*4882a593Smuzhiyun					      <925000 910000 935000>; /* Supply vcc1 */
565*4882a593Smuzhiyun			opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */
566*4882a593Smuzhiyun					     <965000 960000 975000>; /* Supply vcc1 */
567*4882a593Smuzhiyun			opp-microamp =  <70000>; /* Will be used for both slow/fast */
568*4882a593Smuzhiyun		};
569*4882a593Smuzhiyun	};
570*4882a593Smuzhiyun};
571