1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "meson-g12.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun compatible = "amlogic,g12a"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun cpus { 12*4882a593Smuzhiyun #address-cells = <0x2>; 13*4882a593Smuzhiyun #size-cells = <0x0>; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun cpu0: cpu@0 { 16*4882a593Smuzhiyun device_type = "cpu"; 17*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 18*4882a593Smuzhiyun reg = <0x0 0x0>; 19*4882a593Smuzhiyun enable-method = "psci"; 20*4882a593Smuzhiyun next-level-cache = <&l2>; 21*4882a593Smuzhiyun #cooling-cells = <2>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun cpu1: cpu@1 { 25*4882a593Smuzhiyun device_type = "cpu"; 26*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 27*4882a593Smuzhiyun reg = <0x0 0x1>; 28*4882a593Smuzhiyun enable-method = "psci"; 29*4882a593Smuzhiyun next-level-cache = <&l2>; 30*4882a593Smuzhiyun #cooling-cells = <2>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun cpu2: cpu@2 { 34*4882a593Smuzhiyun device_type = "cpu"; 35*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 36*4882a593Smuzhiyun reg = <0x0 0x2>; 37*4882a593Smuzhiyun enable-method = "psci"; 38*4882a593Smuzhiyun next-level-cache = <&l2>; 39*4882a593Smuzhiyun #cooling-cells = <2>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun cpu3: cpu@3 { 43*4882a593Smuzhiyun device_type = "cpu"; 44*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 45*4882a593Smuzhiyun reg = <0x0 0x3>; 46*4882a593Smuzhiyun enable-method = "psci"; 47*4882a593Smuzhiyun next-level-cache = <&l2>; 48*4882a593Smuzhiyun #cooling-cells = <2>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun l2: l2-cache0 { 52*4882a593Smuzhiyun compatible = "cache"; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun cpu_opp_table: opp-table { 57*4882a593Smuzhiyun compatible = "operating-points-v2"; 58*4882a593Smuzhiyun opp-shared; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun opp-100000000 { 61*4882a593Smuzhiyun opp-hz = /bits/ 64 <100000000>; 62*4882a593Smuzhiyun opp-microvolt = <731000>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun opp-250000000 { 66*4882a593Smuzhiyun opp-hz = /bits/ 64 <250000000>; 67*4882a593Smuzhiyun opp-microvolt = <731000>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun opp-500000000 { 71*4882a593Smuzhiyun opp-hz = /bits/ 64 <500000000>; 72*4882a593Smuzhiyun opp-microvolt = <731000>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun opp-667000000 { 76*4882a593Smuzhiyun opp-hz = /bits/ 64 <666666666>; 77*4882a593Smuzhiyun opp-microvolt = <731000>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun opp-1000000000 { 81*4882a593Smuzhiyun opp-hz = /bits/ 64 <1000000000>; 82*4882a593Smuzhiyun opp-microvolt = <731000>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun opp-1200000000 { 86*4882a593Smuzhiyun opp-hz = /bits/ 64 <1200000000>; 87*4882a593Smuzhiyun opp-microvolt = <731000>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun opp-1398000000 { 91*4882a593Smuzhiyun opp-hz = /bits/ 64 <1398000000>; 92*4882a593Smuzhiyun opp-microvolt = <761000>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun opp-1512000000 { 96*4882a593Smuzhiyun opp-hz = /bits/ 64 <1512000000>; 97*4882a593Smuzhiyun opp-microvolt = <791000>; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun opp-1608000000 { 101*4882a593Smuzhiyun opp-hz = /bits/ 64 <1608000000>; 102*4882a593Smuzhiyun opp-microvolt = <831000>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun opp-1704000000 { 106*4882a593Smuzhiyun opp-hz = /bits/ 64 <1704000000>; 107*4882a593Smuzhiyun opp-microvolt = <861000>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun opp-1800000000 { 111*4882a593Smuzhiyun opp-hz = /bits/ 64 <1800000000>; 112*4882a593Smuzhiyun opp-microvolt = <981000>; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun}; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun&cpu_thermal { 118*4882a593Smuzhiyun cooling-maps { 119*4882a593Smuzhiyun map0 { 120*4882a593Smuzhiyun trip = <&cpu_passive>; 121*4882a593Smuzhiyun cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 122*4882a593Smuzhiyun <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 123*4882a593Smuzhiyun <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 124*4882a593Smuzhiyun <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun map1 { 128*4882a593Smuzhiyun trip = <&cpu_hot>; 129*4882a593Smuzhiyun cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 130*4882a593Smuzhiyun <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 131*4882a593Smuzhiyun <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 132*4882a593Smuzhiyun <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun}; 136