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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra124-xusb.txt8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
16 - reg-names: Must contain the following entries:
17 - "hcd"
18 - "fpci"
[all …]
H A Dnvidia,tegra-xudc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 The Tegra XUDC controller supports both USB 2.0 HighSpeed/FullSpeed and
11 USB 3.0 SuperSpeed protocols.
14 - Nagarjuna Kristam <nkristam@nvidia.com>
15 - JC Kuo <jckuo@nvidia.com>
16 - Thierry Reding <treding@nvidia.com>
21 - enum:
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/nvidia/
H A Dtegra186-p2771-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra186-p3310.dtsi"
11 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
14 power-monitor@42 {
17 #address-cells = <1>;
18 #size-cells = <0>;
23 shunt-resistor-micro-ohms = <20000>;
[all …]
H A Dtegra210-p3450-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h>
12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
22 stdout-path = "serial0:115200n8";
33 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
34 hvddio-pex-supply = <&vdd_1v8>;
35 dvddio-pex-supply = <&vdd_pex_1v05>;
[all …]
H A Dtegra210-p2597.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
9 ethernet = "/usb@70090000/ethernet@1";
20 avdd-dsi-csi-supply = <&vdd_dsi_csi>;
30 avdd-io-hdmi-dp-supply = <&avdd_1v05>;
31 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
32 hdmi-supply = <&vdd_hdmi>;
34 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
35 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
41 pinctrl-names = "boot";
[all …]
H A Dtegra132-norrin.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
30 vdd-supply = <&vdd_3v3_hdmi>;
31 pll-supply = <&vdd_hdmi_pll>;
32 hdmi-supply = <&vdd_5v0_hdmi>;
34 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
35 nvidia,hpd-gpio =
42 avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>;
[all …]
H A Dtegra210-smaug.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/mfd/max77620.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
12 compatible = "google,smaug-rev8", "google,smaug-rev7",
13 "google,smaug-rev6", "google,smaug-rev5",
14 "google,smaug-rev4", "google,smaug-rev3",
15 "google,smaug-rev2", "google,smaug-rev1",
24 stdout-path = "serial0:115200n8";
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
13 stdout-path = "serial0:115200n8";
19 * missing a unit-address. However, the bootloader on these Chromebook
21 * Adding the unit-address causes the bootloader to create a /memory
33 /delete-node/ memory@80000000;
39 vdd-supply = <&vdd_3v3_hdmi>;
40 pll-supply = <&vdd_hdmi_pll>;
41 hdmi-supply = <&vdd_5v0_hdmi>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
[all …]
H A Dtegra124-jetson-tk1.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
7 #include "tegra124-jetson-tk1-emc.dtsi"
11 compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
17 /* This order keeps the mapping DB9 connector <-> ttyS0 */
24 stdout-path = "serial0:115200n8";
34 avddio-pex-supply = <&vdd_1v05_run>;
35 dvddio-pex-supply = <&vdd_1v05_run>;
36 avdd-pex-pll-supply = <&vdd_1v05_run>;
[all …]
H A Dtegra124-venice2.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
29 vdd-supply = <&vdd_3v3_hdmi>;
30 pll-supply = <&vdd_hdmi_pll>;
31 hdmi-supply = <&vdd_5v0_hdmi>;
33 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
34 nvidia,hpd-gpio =
41 avdd-io-hdmi-dp-supply = <&vdd_1v05_run>;
[all …]
H A Dtegra124-apalis-v1.2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2016-2018 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
21 avddio-pex-supply = <&reg_1v05_vdd>;
22 avdd-pex-pll-supply = <&reg_1v05_vdd>;
23 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
24 dvddio-pex-supply = <&reg_1v05_vdd>;
25 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
26 hvdd-pex-supply = <&reg_module_3v3>;
27 vddio-pex-ctl-supply = <&reg_module_3v3>;
[all …]
H A Dtegra124-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
20 avddio-pex-supply = <&reg_1v05_vdd>;
21 avdd-pex-pll-supply = <&reg_1v05_vdd>;
22 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
23 dvddio-pex-supply = <&reg_1v05_vdd>;
24 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
25 hvdd-pex-supply = <&reg_module_3v3>;
26 vddio-pex-ctl-supply = <&reg_module_3v3>;
[all …]
H A Dtegra30-cardhu.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
13 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
14 * tegra30-cardhu-a04.dts.
17 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
19 * The (downstream internal) U-Boot of Cardhu display the board-id as
40 stdout-path = "serial0:115200n8";
51 avdd-pexb-supply = <&ldo1_reg>;
52 vdd-pexb-supply = <&ldo1_reg>;
53 avdd-pex-pll-supply = <&ldo1_reg>;
[all …]
H A Dtegra114-dalmore.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
23 stdout-path = "serial0:115200n8";
34 hdmi-supply = <&vdd_5v0_hdmi>;
35 vdd-supply = <&vdd_hdmi_reg>;
36 pll-supply = <&palmas_smps3_reg>;
38 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
39 nvidia,hpd-gpio =
46 avdd-dsi-csi-supply = <&avdd_1v2_reg>;
[all …]
H A Dtegra30-beaver.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu-opp-microvolt.dtsi"
19 stdout-path = "serial0:115200n8";
29 avdd-pexa-supply = <&ldo1_reg>;
30 vdd-pexa-supply = <&ldo1_reg>;
31 avdd-pexb-supply = <&ldo1_reg>;
32 vdd-pexb-supply = <&ldo1_reg>;
33 avdd-pex-pll-supply = <&ldo1_reg>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dtegra124-cei-tk1-som.dts1 /dts-v1/;
6 model = "Colorado Engineering TK1-SOM";
7 compatible = "nvidia,cei-tk1-som", "nvidia,tegra124";
10 stdout-path = &uartd;
23 usb0 = "/usb@7d000000";
24 usb1 = "/usb@7d008000";
32 pcie-controller@01003000 {
35 avddio-pex-supply = <&vdd_1v05_run>;
36 dvddio-pex-supply = <&vdd_1v05_run>;
37 avdd-pex-pll-supply = <&vdd_1v05_run>;
[all …]
H A Dtegra124-jetson-tk1.dts1 /dts-v1/;
7 compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
10 stdout-path = &uartd;
23 usb0 = "/usb@7d000000";
24 usb1 = "/usb@7d008000";
32 pcie-controller@01003000 {
35 avddio-pex-supply = <&vdd_1v05_run>;
36 dvddio-pex-supply = <&vdd_1v05_run>;
37 avdd-pex-pll-supply = <&vdd_1v05_run>;
38 hvdd-pex-supply = <&vdd_3v3_lp0>;
[all …]
H A Dtegra30-apalis.dts1 /dts-v1/;
10 stdout-path = &uarta;
25 usb0 = "/usb@7d000000";
26 usb1 = "/usb@7d004000";
27 usb2 = "/usb@7d008000";
35 pcie-controller@00003000 {
37 avdd-pexa-supply = <&vdd2_reg>;
38 vdd-pexa-supply = <&vdd2_reg>;
39 avdd-pexb-supply = <&vdd2_reg>;
40 vdd-pexb-supply = <&vdd2_reg>;
[all …]
H A Dtegra124-apalis.dts4 * This file is dual-licensed: you can use it either under the terms
42 /dts-v1/;
44 #include <dt-bindings/input/input.h>
49 compatible = "toradex,apalis-tk1-eval", "toradex,apalis-tk1",
67 usb0 = "/usb@7d000000";
68 usb1 = "/usb@7d004000";
69 usb2 = "/usb@7d008000";
73 stdout-path = "serial0:115200n8";
80 pcie-controller@01003000 {
82 avddio-pex-supply = <&vdd_1v05>;
[all …]
H A Dtegra30-beaver.dts1 /dts-v1/;
10 stdout-path = &uarta;
22 usb0 = "/usb@7d000000";
23 usb1 = "/usb@7d008000";
31 pcie-controller@00003000 {
34 avdd-pexa-supply = <&ldo1_reg>;
35 vdd-pexa-supply = <&ldo1_reg>;
36 avdd-pexb-supply = <&ldo1_reg>;
37 vdd-pexb-supply = <&ldo1_reg>;
38 avdd-pex-pll-supply = <&ldo1_reg>;
[all …]
H A Dtegra30-cardhu.dts1 /dts-v1/;
10 stdout-path = &uarta;
22 usb0 = "/usb@7d008000";
30 pcie-controller@00003000 {
34 avdd-pexb-supply = <&ldo1_reg>;
35 vdd-pexb-supply = <&ldo1_reg>;
36 avdd-pex-pll-supply = <&ldo1_reg>;
37 hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
38 vddio-pex-ctl-supply = <&sys_3v3_reg>;
39 avdd-plle-supply = <&ldo2_reg>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
27 "port" is typically used to denote the physical USB receptacle. The device
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/tegra/
H A Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
259 /* must be called under padctl->lock */
262 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_enable()
267 if (pcie->enable > 0) { in tegra210_pex_uphy_enable()
268 pcie->enable++; in tegra210_pex_uphy_enable()
272 err = clk_prepare_enable(pcie->pll); in tegra210_pex_uphy_enable()
276 err = reset_control_deassert(pcie->rst); in tegra210_pex_uphy_enable()
355 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
374 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
[all …]
/OK3568_Linux_fs/kernel/drivers/usb/gadget/udc/
H A Dtegra-xudc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2013-2019, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/dma-mapping.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/otg.h>
30 #include <linux/usb/role.h>
31 #include <linux/usb/phy.h>
247 return (le32_to_cpu(ctx->member) >> (shift)) & (mask); \
254 tmp = le32_to_cpu(ctx->member) & ~((mask) << (shift)); \
[all …]