1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/dts-v1/; 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 5*4882a593Smuzhiyun#include "tegra132.dtsi" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun model = "NVIDIA Tegra132 Norrin"; 9*4882a593Smuzhiyun compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun aliases { 12*4882a593Smuzhiyun rtc0 = "/i2c@7000d000/as3722@40"; 13*4882a593Smuzhiyun rtc1 = "/rtc@7000e000"; 14*4882a593Smuzhiyun serial0 = &uarta; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun chosen { 18*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun memory@80000000 { 22*4882a593Smuzhiyun device_type = "memory"; 23*4882a593Smuzhiyun reg = <0x0 0x80000000 0x0 0x80000000>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun host1x@50000000 { 27*4882a593Smuzhiyun hdmi@54280000 { 28*4882a593Smuzhiyun status = "disabled"; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun vdd-supply = <&vdd_3v3_hdmi>; 31*4882a593Smuzhiyun pll-supply = <&vdd_hdmi_pll>; 32*4882a593Smuzhiyun hdmi-supply = <&vdd_5v0_hdmi>; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun nvidia,ddc-i2c-bus = <&hdmi_ddc>; 35*4882a593Smuzhiyun nvidia,hpd-gpio = 36*4882a593Smuzhiyun <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun sor@54540000 { 40*4882a593Smuzhiyun status = "okay"; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>; 43*4882a593Smuzhiyun vdd-hdmi-dp-pll-supply = <&vdd_hdmi_pll>; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun nvidia,dpaux = <&dpaux>; 46*4882a593Smuzhiyun nvidia,panel = <&panel>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun dpaux: dpaux@545c0000 { 50*4882a593Smuzhiyun vdd-supply = <&vdd_3v3_panel>; 51*4882a593Smuzhiyun status = "okay"; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun gpu@57000000 { 56*4882a593Smuzhiyun status = "okay"; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun vdd-supply = <&vdd_gpu>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun pinmux@70000868 { 62*4882a593Smuzhiyun pinctrl-names = "default"; 63*4882a593Smuzhiyun pinctrl-0 = <&pinmux_default>; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun pinmux_default: pinmux@0 { 66*4882a593Smuzhiyun dap_mclk1_pw4 { 67*4882a593Smuzhiyun nvidia,pins = "dap_mclk1_pw4"; 68*4882a593Smuzhiyun nvidia,function = "extperiph1"; 69*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 70*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 71*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun dap2_din_pa4 { 74*4882a593Smuzhiyun nvidia,pins = "dap2_din_pa4"; 75*4882a593Smuzhiyun nvidia,function = "i2s1"; 76*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 77*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 78*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun dap2_dout_pa5 { 81*4882a593Smuzhiyun nvidia,pins = "dap2_dout_pa5", 82*4882a593Smuzhiyun "dap2_fs_pa2", 83*4882a593Smuzhiyun "dap2_sclk_pa3"; 84*4882a593Smuzhiyun nvidia,function = "i2s1"; 85*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 86*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 87*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun dap3_dout_pp2 { 90*4882a593Smuzhiyun nvidia,pins = "dap3_dout_pp2"; 91*4882a593Smuzhiyun nvidia,function = "i2s2"; 92*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 93*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 94*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun dvfs_pwm_px0 { 97*4882a593Smuzhiyun nvidia,pins = "dvfs_pwm_px0", 98*4882a593Smuzhiyun "dvfs_clk_px2"; 99*4882a593Smuzhiyun nvidia,function = "cldvfs"; 100*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 101*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 102*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun ulpi_clk_py0 { 105*4882a593Smuzhiyun nvidia,pins = "ulpi_clk_py0", 106*4882a593Smuzhiyun "ulpi_nxt_py2", 107*4882a593Smuzhiyun "ulpi_stp_py3"; 108*4882a593Smuzhiyun nvidia,function = "spi1"; 109*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 110*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 111*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun ulpi_dir_py1 { 114*4882a593Smuzhiyun nvidia,pins = "ulpi_dir_py1"; 115*4882a593Smuzhiyun nvidia,function = "spi1"; 116*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 117*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 118*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun cam_i2c_scl_pbb1 { 121*4882a593Smuzhiyun nvidia,pins = "cam_i2c_scl_pbb1", 122*4882a593Smuzhiyun "cam_i2c_sda_pbb2"; 123*4882a593Smuzhiyun nvidia,function = "i2c3"; 124*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 125*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 126*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 127*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 128*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_ENABLE>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun gen2_i2c_scl_pt5 { 131*4882a593Smuzhiyun nvidia,pins = "gen2_i2c_scl_pt5", 132*4882a593Smuzhiyun "gen2_i2c_sda_pt6"; 133*4882a593Smuzhiyun nvidia,function = "i2c2"; 134*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 135*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 136*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 137*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 138*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_ENABLE>; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun pj7 { 141*4882a593Smuzhiyun nvidia,pins = "pj7"; 142*4882a593Smuzhiyun nvidia,function = "uartd"; 143*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 144*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 145*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun spdif_in_pk6 { 148*4882a593Smuzhiyun nvidia,pins = "spdif_in_pk6"; 149*4882a593Smuzhiyun nvidia,function = "spdif"; 150*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 151*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 152*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun pk7 { 155*4882a593Smuzhiyun nvidia,pins = "pk7"; 156*4882a593Smuzhiyun nvidia,function = "uartd"; 157*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 158*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 159*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun pg4 { 162*4882a593Smuzhiyun nvidia,pins = "pg4", 163*4882a593Smuzhiyun "pg5", 164*4882a593Smuzhiyun "pg6", 165*4882a593Smuzhiyun "pi3"; 166*4882a593Smuzhiyun nvidia,function = "spi4"; 167*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 168*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 169*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun pg7 { 172*4882a593Smuzhiyun nvidia,pins = "pg7"; 173*4882a593Smuzhiyun nvidia,function = "spi4"; 174*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 175*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 176*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun ph1 { 179*4882a593Smuzhiyun nvidia,pins = "ph1"; 180*4882a593Smuzhiyun nvidia,function = "pwm1"; 181*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 182*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 183*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun pk0 { 186*4882a593Smuzhiyun nvidia,pins = "pk0", 187*4882a593Smuzhiyun "kb_row15_ps7", 188*4882a593Smuzhiyun "clk_32k_out_pa0"; 189*4882a593Smuzhiyun nvidia,function = "soc"; 190*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 191*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 192*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun sdmmc1_clk_pz0 { 195*4882a593Smuzhiyun nvidia,pins = "sdmmc1_clk_pz0"; 196*4882a593Smuzhiyun nvidia,function = "sdmmc1"; 197*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 198*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 199*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun sdmmc1_cmd_pz1 { 202*4882a593Smuzhiyun nvidia,pins = "sdmmc1_cmd_pz1", 203*4882a593Smuzhiyun "sdmmc1_dat0_py7", 204*4882a593Smuzhiyun "sdmmc1_dat1_py6", 205*4882a593Smuzhiyun "sdmmc1_dat2_py5", 206*4882a593Smuzhiyun "sdmmc1_dat3_py4"; 207*4882a593Smuzhiyun nvidia,function = "sdmmc1"; 208*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 209*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 210*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun sdmmc3_clk_pa6 { 213*4882a593Smuzhiyun nvidia,pins = "sdmmc3_clk_pa6"; 214*4882a593Smuzhiyun nvidia,function = "sdmmc3"; 215*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 216*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 217*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun sdmmc3_cmd_pa7 { 220*4882a593Smuzhiyun nvidia,pins = "sdmmc3_cmd_pa7", 221*4882a593Smuzhiyun "sdmmc3_dat0_pb7", 222*4882a593Smuzhiyun "sdmmc3_dat1_pb6", 223*4882a593Smuzhiyun "sdmmc3_dat2_pb5", 224*4882a593Smuzhiyun "sdmmc3_dat3_pb4", 225*4882a593Smuzhiyun "kb_col4_pq4", 226*4882a593Smuzhiyun "sdmmc3_clk_lb_out_pee4", 227*4882a593Smuzhiyun "sdmmc3_clk_lb_in_pee5", 228*4882a593Smuzhiyun "sdmmc3_cd_n_pv2"; 229*4882a593Smuzhiyun nvidia,function = "sdmmc3"; 230*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 231*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 232*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun sdmmc4_clk_pcc4 { 235*4882a593Smuzhiyun nvidia,pins = "sdmmc4_clk_pcc4"; 236*4882a593Smuzhiyun nvidia,function = "sdmmc4"; 237*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 238*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 239*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun sdmmc4_cmd_pt7 { 242*4882a593Smuzhiyun nvidia,pins = "sdmmc4_cmd_pt7", 243*4882a593Smuzhiyun "sdmmc4_dat0_paa0", 244*4882a593Smuzhiyun "sdmmc4_dat1_paa1", 245*4882a593Smuzhiyun "sdmmc4_dat2_paa2", 246*4882a593Smuzhiyun "sdmmc4_dat3_paa3", 247*4882a593Smuzhiyun "sdmmc4_dat4_paa4", 248*4882a593Smuzhiyun "sdmmc4_dat5_paa5", 249*4882a593Smuzhiyun "sdmmc4_dat6_paa6", 250*4882a593Smuzhiyun "sdmmc4_dat7_paa7"; 251*4882a593Smuzhiyun nvidia,function = "sdmmc4"; 252*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 253*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 254*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun mic_det_l { 257*4882a593Smuzhiyun nvidia,pins = "kb_row7_pr7"; 258*4882a593Smuzhiyun nvidia,function = "rsvd2"; 259*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 260*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 261*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun kb_row10_ps2 { 264*4882a593Smuzhiyun nvidia,pins = "kb_row10_ps2"; 265*4882a593Smuzhiyun nvidia,function = "uarta"; 266*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 267*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 268*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun kb_row9_ps1 { 271*4882a593Smuzhiyun nvidia,pins = "kb_row9_ps1"; 272*4882a593Smuzhiyun nvidia,function = "uarta"; 273*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 274*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 275*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun pwr_i2c_scl_pz6 { 278*4882a593Smuzhiyun nvidia,pins = "pwr_i2c_scl_pz6", 279*4882a593Smuzhiyun "pwr_i2c_sda_pz7"; 280*4882a593Smuzhiyun nvidia,function = "i2cpwr"; 281*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 282*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 283*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 284*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 285*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_ENABLE>; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun jtag_rtck { 288*4882a593Smuzhiyun nvidia,pins = "jtag_rtck"; 289*4882a593Smuzhiyun nvidia,function = "rtck"; 290*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 291*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 292*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun clk_32k_in { 295*4882a593Smuzhiyun nvidia,pins = "clk_32k_in"; 296*4882a593Smuzhiyun nvidia,function = "clk"; 297*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 298*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 299*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun core_pwr_req { 302*4882a593Smuzhiyun nvidia,pins = "core_pwr_req"; 303*4882a593Smuzhiyun nvidia,function = "pwron"; 304*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 305*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 306*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 307*4882a593Smuzhiyun }; 308*4882a593Smuzhiyun cpu_pwr_req { 309*4882a593Smuzhiyun nvidia,pins = "cpu_pwr_req"; 310*4882a593Smuzhiyun nvidia,function = "cpu"; 311*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 312*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 313*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun kb_col0_ap { 316*4882a593Smuzhiyun nvidia,pins = "kb_col0_pq0"; 317*4882a593Smuzhiyun nvidia,function = "rsvd4"; 318*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 319*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 320*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 321*4882a593Smuzhiyun }; 322*4882a593Smuzhiyun en_vdd_sd { 323*4882a593Smuzhiyun nvidia,pins = "kb_row0_pr0"; 324*4882a593Smuzhiyun nvidia,function = "rsvd4"; 325*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 326*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 327*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun lid_open { 330*4882a593Smuzhiyun nvidia,pins = "kb_row4_pr4"; 331*4882a593Smuzhiyun nvidia,function = "rsvd3"; 332*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 333*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 334*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 335*4882a593Smuzhiyun }; 336*4882a593Smuzhiyun pwr_int_n { 337*4882a593Smuzhiyun nvidia,pins = "pwr_int_n"; 338*4882a593Smuzhiyun nvidia,function = "pmi"; 339*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 340*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 341*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun reset_out_n { 344*4882a593Smuzhiyun nvidia,pins = "reset_out_n"; 345*4882a593Smuzhiyun nvidia,function = "reset_out_n"; 346*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 347*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 348*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 349*4882a593Smuzhiyun }; 350*4882a593Smuzhiyun clk3_out_pee0 { 351*4882a593Smuzhiyun nvidia,pins = "clk3_out_pee0"; 352*4882a593Smuzhiyun nvidia,function = "extperiph3"; 353*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 354*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 355*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 356*4882a593Smuzhiyun }; 357*4882a593Smuzhiyun gen1_i2c_scl_pc4 { 358*4882a593Smuzhiyun nvidia,pins = "gen1_i2c_scl_pc4", 359*4882a593Smuzhiyun "gen1_i2c_sda_pc5"; 360*4882a593Smuzhiyun nvidia,function = "i2c1"; 361*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 362*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 363*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 364*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 365*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_ENABLE>; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun hdmi_cec_pee3 { 368*4882a593Smuzhiyun nvidia,pins = "hdmi_cec_pee3"; 369*4882a593Smuzhiyun nvidia,function = "cec"; 370*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 371*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 372*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 373*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 374*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_DISABLE>; 375*4882a593Smuzhiyun }; 376*4882a593Smuzhiyun hdmi_int_pn7 { 377*4882a593Smuzhiyun nvidia,pins = "hdmi_int_pn7"; 378*4882a593Smuzhiyun nvidia,function = "rsvd1"; 379*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 380*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 381*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 382*4882a593Smuzhiyun }; 383*4882a593Smuzhiyun ddc_scl_pv4 { 384*4882a593Smuzhiyun nvidia,pins = "ddc_scl_pv4", 385*4882a593Smuzhiyun "ddc_sda_pv5"; 386*4882a593Smuzhiyun nvidia,function = "i2c4"; 387*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 388*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 389*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 390*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 391*4882a593Smuzhiyun nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; 392*4882a593Smuzhiyun }; 393*4882a593Smuzhiyun usb_vbus_en0_pn4 { 394*4882a593Smuzhiyun nvidia,pins = "usb_vbus_en0_pn4", 395*4882a593Smuzhiyun "usb_vbus_en1_pn5", 396*4882a593Smuzhiyun "usb_vbus_en2_pff1"; 397*4882a593Smuzhiyun nvidia,function = "usb"; 398*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 399*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 400*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 401*4882a593Smuzhiyun nvidia,lock = <TEGRA_PIN_DISABLE>; 402*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_DISABLE>; 403*4882a593Smuzhiyun }; 404*4882a593Smuzhiyun drive_sdio1 { 405*4882a593Smuzhiyun nvidia,pins = "drive_sdio1"; 406*4882a593Smuzhiyun nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 407*4882a593Smuzhiyun nvidia,schmitt = <TEGRA_PIN_DISABLE>; 408*4882a593Smuzhiyun nvidia,pull-down-strength = <36>; 409*4882a593Smuzhiyun nvidia,pull-up-strength = <20>; 410*4882a593Smuzhiyun nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; 411*4882a593Smuzhiyun nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun drive_sdio3 { 414*4882a593Smuzhiyun nvidia,pins = "drive_sdio3"; 415*4882a593Smuzhiyun nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 416*4882a593Smuzhiyun nvidia,schmitt = <TEGRA_PIN_DISABLE>; 417*4882a593Smuzhiyun nvidia,pull-down-strength = <22>; 418*4882a593Smuzhiyun nvidia,pull-up-strength = <36>; 419*4882a593Smuzhiyun nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 420*4882a593Smuzhiyun nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 421*4882a593Smuzhiyun }; 422*4882a593Smuzhiyun drive_gma { 423*4882a593Smuzhiyun nvidia,pins = "drive_gma"; 424*4882a593Smuzhiyun nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 425*4882a593Smuzhiyun nvidia,schmitt = <TEGRA_PIN_DISABLE>; 426*4882a593Smuzhiyun nvidia,pull-down-strength = <2>; 427*4882a593Smuzhiyun nvidia,pull-up-strength = <1>; 428*4882a593Smuzhiyun nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 429*4882a593Smuzhiyun nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 430*4882a593Smuzhiyun nvidia,drive-type = <1>; 431*4882a593Smuzhiyun }; 432*4882a593Smuzhiyun ac_ok { 433*4882a593Smuzhiyun nvidia,pins = "pj0"; 434*4882a593Smuzhiyun nvidia,function = "gmi"; 435*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 436*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 437*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 438*4882a593Smuzhiyun }; 439*4882a593Smuzhiyun codec_irq_l { 440*4882a593Smuzhiyun nvidia,pins = "ph4"; 441*4882a593Smuzhiyun nvidia,function = "gmi"; 442*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 443*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 444*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 445*4882a593Smuzhiyun }; 446*4882a593Smuzhiyun lcd_bl_en { 447*4882a593Smuzhiyun nvidia,pins = "ph2"; 448*4882a593Smuzhiyun nvidia,function = "gmi"; 449*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 450*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 451*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 452*4882a593Smuzhiyun }; 453*4882a593Smuzhiyun touch_irq_l { 454*4882a593Smuzhiyun nvidia,pins = "gpio_w3_aud_pw3"; 455*4882a593Smuzhiyun nvidia,function = "spi6"; 456*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 457*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 458*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 459*4882a593Smuzhiyun }; 460*4882a593Smuzhiyun tpm_davint_l { 461*4882a593Smuzhiyun nvidia,pins = "ph6"; 462*4882a593Smuzhiyun nvidia,function = "gmi"; 463*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 464*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 465*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun ts_irq_l { 468*4882a593Smuzhiyun nvidia,pins = "pk2"; 469*4882a593Smuzhiyun nvidia,function = "gmi"; 470*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 471*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 472*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 473*4882a593Smuzhiyun }; 474*4882a593Smuzhiyun ts_reset_l { 475*4882a593Smuzhiyun nvidia,pins = "pk4"; 476*4882a593Smuzhiyun nvidia,function = "gmi"; 477*4882a593Smuzhiyun nvidia,pull = <1>; 478*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 479*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 480*4882a593Smuzhiyun }; 481*4882a593Smuzhiyun ts_shdn_l { 482*4882a593Smuzhiyun nvidia,pins = "pk1"; 483*4882a593Smuzhiyun nvidia,function = "gmi"; 484*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 485*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 486*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 487*4882a593Smuzhiyun }; 488*4882a593Smuzhiyun ph7 { 489*4882a593Smuzhiyun nvidia,pins = "ph7"; 490*4882a593Smuzhiyun nvidia,function = "gmi"; 491*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 492*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 493*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 494*4882a593Smuzhiyun }; 495*4882a593Smuzhiyun sensor_irq_l { 496*4882a593Smuzhiyun nvidia,pins = "pi6"; 497*4882a593Smuzhiyun nvidia,function = "gmi"; 498*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 499*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 500*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 501*4882a593Smuzhiyun }; 502*4882a593Smuzhiyun wifi_en { 503*4882a593Smuzhiyun nvidia,pins = "gpio_x7_aud_px7"; 504*4882a593Smuzhiyun nvidia,function = "rsvd4"; 505*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 506*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 507*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 508*4882a593Smuzhiyun }; 509*4882a593Smuzhiyun chromeos_write_protect { 510*4882a593Smuzhiyun nvidia,pins = "kb_row1_pr1"; 511*4882a593Smuzhiyun nvidia,function = "rsvd4"; 512*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 513*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 514*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 515*4882a593Smuzhiyun }; 516*4882a593Smuzhiyun hp_det_l { 517*4882a593Smuzhiyun nvidia,pins = "pi7"; 518*4882a593Smuzhiyun nvidia,function = "rsvd1"; 519*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 520*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 521*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 522*4882a593Smuzhiyun }; 523*4882a593Smuzhiyun soc_warm_reset_l { 524*4882a593Smuzhiyun nvidia,pins = "pi5"; 525*4882a593Smuzhiyun nvidia,function = "gmi"; 526*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 527*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 528*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 529*4882a593Smuzhiyun }; 530*4882a593Smuzhiyun }; 531*4882a593Smuzhiyun }; 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun serial@70006000 { 534*4882a593Smuzhiyun status = "okay"; 535*4882a593Smuzhiyun }; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun pwm: pwm@7000a000 { 538*4882a593Smuzhiyun status = "okay"; 539*4882a593Smuzhiyun }; 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun /* HDMI DDC */ 542*4882a593Smuzhiyun hdmi_ddc: i2c@7000c700 { 543*4882a593Smuzhiyun status = "okay"; 544*4882a593Smuzhiyun clock-frequency = <100000>; 545*4882a593Smuzhiyun }; 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun i2c@7000d000 { 548*4882a593Smuzhiyun status = "okay"; 549*4882a593Smuzhiyun clock-frequency = <400000>; 550*4882a593Smuzhiyun 551*4882a593Smuzhiyun as3722: pmic@40 { 552*4882a593Smuzhiyun compatible = "ams,as3722"; 553*4882a593Smuzhiyun reg = <0x40>; 554*4882a593Smuzhiyun interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun ams,system-power-controller; 557*4882a593Smuzhiyun 558*4882a593Smuzhiyun #interrupt-cells = <2>; 559*4882a593Smuzhiyun interrupt-controller; 560*4882a593Smuzhiyun 561*4882a593Smuzhiyun #gpio-cells = <2>; 562*4882a593Smuzhiyun gpio-controller; 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun pinctrl-names = "default"; 565*4882a593Smuzhiyun pinctrl-0 = <&as3722_default>; 566*4882a593Smuzhiyun 567*4882a593Smuzhiyun as3722_default: pinmux@0 { 568*4882a593Smuzhiyun gpio0 { 569*4882a593Smuzhiyun pins = "gpio0"; 570*4882a593Smuzhiyun function = "gpio"; 571*4882a593Smuzhiyun bias-pull-down; 572*4882a593Smuzhiyun }; 573*4882a593Smuzhiyun 574*4882a593Smuzhiyun gpio1 { 575*4882a593Smuzhiyun pins = "gpio1"; 576*4882a593Smuzhiyun function = "gpio"; 577*4882a593Smuzhiyun bias-pull-up; 578*4882a593Smuzhiyun }; 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun gpio2_4_7 { 581*4882a593Smuzhiyun pins = "gpio2", "gpio4", "gpio7"; 582*4882a593Smuzhiyun function = "gpio"; 583*4882a593Smuzhiyun bias-pull-up; 584*4882a593Smuzhiyun }; 585*4882a593Smuzhiyun 586*4882a593Smuzhiyun gpio3 { 587*4882a593Smuzhiyun pins = "gpio3"; 588*4882a593Smuzhiyun function = "gpio"; 589*4882a593Smuzhiyun bias-high-impedance; 590*4882a593Smuzhiyun }; 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun gpio5 { 593*4882a593Smuzhiyun pins = "gpio5"; 594*4882a593Smuzhiyun function = "clk32k-out"; 595*4882a593Smuzhiyun bias-pull-down; 596*4882a593Smuzhiyun }; 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun gpio6 { 599*4882a593Smuzhiyun pins = "gpio6"; 600*4882a593Smuzhiyun function = "clk32k-out"; 601*4882a593Smuzhiyun bias-pull-down; 602*4882a593Smuzhiyun }; 603*4882a593Smuzhiyun }; 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun regulators { 606*4882a593Smuzhiyun vsup-sd2-supply = <&vdd_5v0_sys>; 607*4882a593Smuzhiyun vsup-sd3-supply = <&vdd_5v0_sys>; 608*4882a593Smuzhiyun vsup-sd4-supply = <&vdd_5v0_sys>; 609*4882a593Smuzhiyun vsup-sd5-supply = <&vdd_5v0_sys>; 610*4882a593Smuzhiyun vin-ldo0-supply = <&vdd_1v35_lp0>; 611*4882a593Smuzhiyun vin-ldo1-6-supply = <&vdd_3v3_sys>; 612*4882a593Smuzhiyun vin-ldo2-5-7-supply = <&vddio_1v8>; 613*4882a593Smuzhiyun vin-ldo3-4-supply = <&vdd_3v3_sys>; 614*4882a593Smuzhiyun vin-ldo9-10-supply = <&vdd_5v0_sys>; 615*4882a593Smuzhiyun vin-ldo11-supply = <&vdd_3v3_run>; 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun sd0 { 618*4882a593Smuzhiyun regulator-name = "+VDD_CPU_AP"; 619*4882a593Smuzhiyun regulator-min-microvolt = <700000>; 620*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 621*4882a593Smuzhiyun regulator-max-microamp = <3500000>; 622*4882a593Smuzhiyun regulator-always-on; 623*4882a593Smuzhiyun regulator-boot-on; 624*4882a593Smuzhiyun ams,ext-control = <2>; 625*4882a593Smuzhiyun }; 626*4882a593Smuzhiyun 627*4882a593Smuzhiyun sd1 { 628*4882a593Smuzhiyun regulator-name = "+VDD_CORE"; 629*4882a593Smuzhiyun regulator-min-microvolt = <700000>; 630*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 631*4882a593Smuzhiyun regulator-max-microamp = <4000000>; 632*4882a593Smuzhiyun regulator-always-on; 633*4882a593Smuzhiyun regulator-boot-on; 634*4882a593Smuzhiyun ams,ext-control = <1>; 635*4882a593Smuzhiyun }; 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun vdd_1v35_lp0: sd2 { 638*4882a593Smuzhiyun regulator-name = "+1.35V_LP0(sd2)"; 639*4882a593Smuzhiyun regulator-min-microvolt = <1350000>; 640*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 641*4882a593Smuzhiyun regulator-always-on; 642*4882a593Smuzhiyun regulator-boot-on; 643*4882a593Smuzhiyun }; 644*4882a593Smuzhiyun 645*4882a593Smuzhiyun sd3 { 646*4882a593Smuzhiyun regulator-name = "+1.35V_LP0(sd3)"; 647*4882a593Smuzhiyun regulator-min-microvolt = <1350000>; 648*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 649*4882a593Smuzhiyun regulator-always-on; 650*4882a593Smuzhiyun regulator-boot-on; 651*4882a593Smuzhiyun }; 652*4882a593Smuzhiyun 653*4882a593Smuzhiyun vdd_1v05_run: sd4 { 654*4882a593Smuzhiyun regulator-name = "+1.05V_RUN"; 655*4882a593Smuzhiyun regulator-min-microvolt = <1050000>; 656*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 657*4882a593Smuzhiyun }; 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun vddio_1v8: sd5 { 660*4882a593Smuzhiyun regulator-name = "+1.8V_VDDIO"; 661*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 662*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 663*4882a593Smuzhiyun regulator-always-on; 664*4882a593Smuzhiyun regulator-boot-on; 665*4882a593Smuzhiyun }; 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun vdd_gpu: sd6 { 668*4882a593Smuzhiyun regulator-name = "+VDD_GPU_AP"; 669*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 670*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 671*4882a593Smuzhiyun regulator-min-microamp = <3500000>; 672*4882a593Smuzhiyun regulator-max-microamp = <3500000>; 673*4882a593Smuzhiyun regulator-always-on; 674*4882a593Smuzhiyun regulator-boot-on; 675*4882a593Smuzhiyun }; 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun avdd_1v05_run: ldo0 { 678*4882a593Smuzhiyun regulator-name = "+1.05_RUN_AVDD"; 679*4882a593Smuzhiyun regulator-min-microvolt = <1050000>; 680*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 681*4882a593Smuzhiyun regulator-always-on; 682*4882a593Smuzhiyun regulator-boot-on; 683*4882a593Smuzhiyun ams,ext-control = <1>; 684*4882a593Smuzhiyun }; 685*4882a593Smuzhiyun 686*4882a593Smuzhiyun ldo1 { 687*4882a593Smuzhiyun regulator-name = "+1.8V_RUN_CAM"; 688*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 689*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 690*4882a593Smuzhiyun }; 691*4882a593Smuzhiyun 692*4882a593Smuzhiyun ldo2 { 693*4882a593Smuzhiyun regulator-name = "+1.2V_GEN_AVDD"; 694*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 695*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 696*4882a593Smuzhiyun regulator-always-on; 697*4882a593Smuzhiyun regulator-boot-on; 698*4882a593Smuzhiyun }; 699*4882a593Smuzhiyun 700*4882a593Smuzhiyun ldo3 { 701*4882a593Smuzhiyun regulator-name = "+1.00V_LP0_VDD_RTC"; 702*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 703*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 704*4882a593Smuzhiyun regulator-always-on; 705*4882a593Smuzhiyun regulator-boot-on; 706*4882a593Smuzhiyun ams,enable-tracking; 707*4882a593Smuzhiyun }; 708*4882a593Smuzhiyun 709*4882a593Smuzhiyun vdd_run_cam: ldo4 { 710*4882a593Smuzhiyun regulator-name = "+2.8V_RUN_CAM"; 711*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 712*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 713*4882a593Smuzhiyun }; 714*4882a593Smuzhiyun 715*4882a593Smuzhiyun ldo5 { 716*4882a593Smuzhiyun regulator-name = "+1.2V_RUN_CAM_FRONT"; 717*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 718*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 719*4882a593Smuzhiyun }; 720*4882a593Smuzhiyun 721*4882a593Smuzhiyun vddio_sdmmc3: ldo6 { 722*4882a593Smuzhiyun regulator-name = "+VDDIO_SDMMC3"; 723*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 724*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 725*4882a593Smuzhiyun }; 726*4882a593Smuzhiyun 727*4882a593Smuzhiyun ldo7 { 728*4882a593Smuzhiyun regulator-name = "+1.05V_RUN_CAM_REAR"; 729*4882a593Smuzhiyun regulator-min-microvolt = <1050000>; 730*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 731*4882a593Smuzhiyun }; 732*4882a593Smuzhiyun 733*4882a593Smuzhiyun ldo9 { 734*4882a593Smuzhiyun regulator-name = "+2.8V_RUN_TOUCH"; 735*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 736*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 737*4882a593Smuzhiyun }; 738*4882a593Smuzhiyun 739*4882a593Smuzhiyun ldo10 { 740*4882a593Smuzhiyun regulator-name = "+2.8V_RUN_CAM_AF"; 741*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 742*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 743*4882a593Smuzhiyun }; 744*4882a593Smuzhiyun 745*4882a593Smuzhiyun ldo11 { 746*4882a593Smuzhiyun regulator-name = "+1.8V_RUN_VPP_FUSE"; 747*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 748*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 749*4882a593Smuzhiyun }; 750*4882a593Smuzhiyun }; 751*4882a593Smuzhiyun }; 752*4882a593Smuzhiyun }; 753*4882a593Smuzhiyun 754*4882a593Smuzhiyun spi@7000d400 { 755*4882a593Smuzhiyun status = "okay"; 756*4882a593Smuzhiyun 757*4882a593Smuzhiyun ec: cros-ec@0 { 758*4882a593Smuzhiyun compatible = "google,cros-ec-spi"; 759*4882a593Smuzhiyun spi-max-frequency = <3000000>; 760*4882a593Smuzhiyun interrupt-parent = <&gpio>; 761*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; 762*4882a593Smuzhiyun reg = <0>; 763*4882a593Smuzhiyun 764*4882a593Smuzhiyun google,cros-ec-spi-msg-delay = <2000>; 765*4882a593Smuzhiyun 766*4882a593Smuzhiyun i2c_20: i2c-tunnel { 767*4882a593Smuzhiyun compatible = "google,cros-ec-i2c-tunnel"; 768*4882a593Smuzhiyun #address-cells = <1>; 769*4882a593Smuzhiyun #size-cells = <0>; 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun google,remote-bus = <0>; 772*4882a593Smuzhiyun 773*4882a593Smuzhiyun charger: bq24735 { 774*4882a593Smuzhiyun compatible = "ti,bq24735"; 775*4882a593Smuzhiyun reg = <0x9>; 776*4882a593Smuzhiyun interrupt-parent = <&gpio>; 777*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(J, 0) 778*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 779*4882a593Smuzhiyun ti,ac-detect-gpios = <&gpio 780*4882a593Smuzhiyun TEGRA_GPIO(J, 0) 781*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 782*4882a593Smuzhiyun }; 783*4882a593Smuzhiyun 784*4882a593Smuzhiyun battery: smart-battery { 785*4882a593Smuzhiyun compatible = "sbs,sbs-battery"; 786*4882a593Smuzhiyun reg = <0xb>; 787*4882a593Smuzhiyun sbs,i2c-retry-count = <2>; 788*4882a593Smuzhiyun sbs,poll-retry-count = <10>; 789*4882a593Smuzhiyun /* power-supplies = <&charger>; */ 790*4882a593Smuzhiyun }; 791*4882a593Smuzhiyun }; 792*4882a593Smuzhiyun 793*4882a593Smuzhiyun keyboard-controller { 794*4882a593Smuzhiyun compatible = "google,cros-ec-keyb"; 795*4882a593Smuzhiyun keypad,num-rows = <8>; 796*4882a593Smuzhiyun keypad,num-columns = <13>; 797*4882a593Smuzhiyun google,needs-ghost-filter; 798*4882a593Smuzhiyun linux,keymap = 799*4882a593Smuzhiyun <MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) 800*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x02, KEY_F1) 801*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x03, KEY_B) 802*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x04, KEY_F10) 803*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x06, KEY_N) 804*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x08, KEY_EQUAL) 805*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) 806*4882a593Smuzhiyun 807*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x01, KEY_ESC) 808*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x02, KEY_F4) 809*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x03, KEY_G) 810*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x04, KEY_F7) 811*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x06, KEY_H) 812*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) 813*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x09, KEY_F9) 814*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) 815*4882a593Smuzhiyun 816*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) 817*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x01, KEY_TAB) 818*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x02, KEY_F3) 819*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x03, KEY_T) 820*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x04, KEY_F6) 821*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) 822*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x06, KEY_Y) 823*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x07, KEY_102ND) 824*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) 825*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x09, KEY_F8) 826*4882a593Smuzhiyun 827*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x01, KEY_GRAVE) 828*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x02, KEY_F2) 829*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x03, KEY_5) 830*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x04, KEY_F5) 831*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x06, KEY_6) 832*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x08, KEY_MINUS) 833*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) 834*4882a593Smuzhiyun 835*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) 836*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x01, KEY_A) 837*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x02, KEY_D) 838*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x03, KEY_F) 839*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x04, KEY_S) 840*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x05, KEY_K) 841*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x06, KEY_J) 842*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) 843*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x09, KEY_L) 844*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) 845*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x0b, KEY_ENTER) 846*4882a593Smuzhiyun 847*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x01, KEY_Z) 848*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x02, KEY_C) 849*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x03, KEY_V) 850*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x04, KEY_X) 851*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x05, KEY_COMMA) 852*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x06, KEY_M) 853*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) 854*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x08, KEY_SLASH) 855*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x09, KEY_DOT) 856*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x0b, KEY_SPACE) 857*4882a593Smuzhiyun 858*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x01, KEY_1) 859*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x02, KEY_3) 860*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x03, KEY_4) 861*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x04, KEY_2) 862*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x05, KEY_8) 863*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x06, KEY_7) 864*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x08, KEY_0) 865*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x09, KEY_9) 866*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) 867*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x0b, KEY_DOWN) 868*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) 869*4882a593Smuzhiyun 870*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x01, KEY_Q) 871*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x02, KEY_E) 872*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x03, KEY_R) 873*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x04, KEY_W) 874*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x05, KEY_I) 875*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x06, KEY_U) 876*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) 877*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x08, KEY_P) 878*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x09, KEY_O) 879*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x0b, KEY_UP) 880*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x0c, KEY_LEFT)>; 881*4882a593Smuzhiyun }; 882*4882a593Smuzhiyun }; 883*4882a593Smuzhiyun }; 884*4882a593Smuzhiyun 885*4882a593Smuzhiyun pmc@7000e400 { 886*4882a593Smuzhiyun nvidia,invert-interrupt; 887*4882a593Smuzhiyun nvidia,suspend-mode = <0>; 888*4882a593Smuzhiyun #wake-cells = <3>; 889*4882a593Smuzhiyun nvidia,cpu-pwr-good-time = <500>; 890*4882a593Smuzhiyun nvidia,cpu-pwr-off-time = <300>; 891*4882a593Smuzhiyun nvidia,core-pwr-good-time = <641 3845>; 892*4882a593Smuzhiyun nvidia,core-pwr-off-time = <61036>; 893*4882a593Smuzhiyun nvidia,core-power-req-active-high; 894*4882a593Smuzhiyun nvidia,sys-clock-req-active-high; 895*4882a593Smuzhiyun nvidia,reset-gpio = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 896*4882a593Smuzhiyun }; 897*4882a593Smuzhiyun 898*4882a593Smuzhiyun usb@70090000 { 899*4882a593Smuzhiyun phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ 900*4882a593Smuzhiyun <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ 901*4882a593Smuzhiyun <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ 902*4882a593Smuzhiyun <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ 903*4882a593Smuzhiyun <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ 904*4882a593Smuzhiyun phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; 905*4882a593Smuzhiyun 906*4882a593Smuzhiyun avddio-pex-supply = <&vdd_1v05_run>; 907*4882a593Smuzhiyun dvddio-pex-supply = <&vdd_1v05_run>; 908*4882a593Smuzhiyun avdd-usb-supply = <&vdd_3v3_lp0>; 909*4882a593Smuzhiyun hvdd-usb-ss-supply = <&vdd_3v3_lp0>; 910*4882a593Smuzhiyun 911*4882a593Smuzhiyun status = "okay"; 912*4882a593Smuzhiyun }; 913*4882a593Smuzhiyun 914*4882a593Smuzhiyun padctl@7009f000 { 915*4882a593Smuzhiyun avdd-pll-utmip-supply = <&vddio_1v8>; 916*4882a593Smuzhiyun avdd-pll-erefe-supply = <&avdd_1v05_run>; 917*4882a593Smuzhiyun avdd-pex-pll-supply = <&vdd_1v05_run>; 918*4882a593Smuzhiyun hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; 919*4882a593Smuzhiyun 920*4882a593Smuzhiyun pads { 921*4882a593Smuzhiyun usb2 { 922*4882a593Smuzhiyun status = "okay"; 923*4882a593Smuzhiyun 924*4882a593Smuzhiyun lanes { 925*4882a593Smuzhiyun usb2-0 { 926*4882a593Smuzhiyun nvidia,function = "xusb"; 927*4882a593Smuzhiyun status = "okay"; 928*4882a593Smuzhiyun }; 929*4882a593Smuzhiyun 930*4882a593Smuzhiyun usb2-1 { 931*4882a593Smuzhiyun nvidia,function = "xusb"; 932*4882a593Smuzhiyun status = "okay"; 933*4882a593Smuzhiyun }; 934*4882a593Smuzhiyun 935*4882a593Smuzhiyun usb2-2 { 936*4882a593Smuzhiyun nvidia,function = "xusb"; 937*4882a593Smuzhiyun status = "okay"; 938*4882a593Smuzhiyun }; 939*4882a593Smuzhiyun }; 940*4882a593Smuzhiyun }; 941*4882a593Smuzhiyun 942*4882a593Smuzhiyun pcie { 943*4882a593Smuzhiyun status = "okay"; 944*4882a593Smuzhiyun 945*4882a593Smuzhiyun lanes { 946*4882a593Smuzhiyun pcie-0 { 947*4882a593Smuzhiyun nvidia,function = "usb3-ss"; 948*4882a593Smuzhiyun status = "okay"; 949*4882a593Smuzhiyun }; 950*4882a593Smuzhiyun 951*4882a593Smuzhiyun pcie-1 { 952*4882a593Smuzhiyun nvidia,function = "usb3-ss"; 953*4882a593Smuzhiyun status = "okay"; 954*4882a593Smuzhiyun }; 955*4882a593Smuzhiyun }; 956*4882a593Smuzhiyun }; 957*4882a593Smuzhiyun }; 958*4882a593Smuzhiyun 959*4882a593Smuzhiyun ports { 960*4882a593Smuzhiyun usb2-0 { 961*4882a593Smuzhiyun status = "okay"; 962*4882a593Smuzhiyun mode = "otg"; 963*4882a593Smuzhiyun 964*4882a593Smuzhiyun vbus-supply = <&vdd_usb1_vbus>; 965*4882a593Smuzhiyun }; 966*4882a593Smuzhiyun 967*4882a593Smuzhiyun usb2-1 { 968*4882a593Smuzhiyun status = "okay"; 969*4882a593Smuzhiyun mode = "host"; 970*4882a593Smuzhiyun 971*4882a593Smuzhiyun vbus-supply = <&vdd_run_cam>; 972*4882a593Smuzhiyun }; 973*4882a593Smuzhiyun 974*4882a593Smuzhiyun usb2-2 { 975*4882a593Smuzhiyun status = "okay"; 976*4882a593Smuzhiyun mode = "host"; 977*4882a593Smuzhiyun 978*4882a593Smuzhiyun vbus-supply = <&vdd_usb3_vbus>; 979*4882a593Smuzhiyun }; 980*4882a593Smuzhiyun 981*4882a593Smuzhiyun usb3-0 { 982*4882a593Smuzhiyun nvidia,usb2-companion = <0>; 983*4882a593Smuzhiyun status = "okay"; 984*4882a593Smuzhiyun }; 985*4882a593Smuzhiyun 986*4882a593Smuzhiyun usb3-1 { 987*4882a593Smuzhiyun nvidia,usb2-companion = <2>; 988*4882a593Smuzhiyun status = "okay"; 989*4882a593Smuzhiyun }; 990*4882a593Smuzhiyun }; 991*4882a593Smuzhiyun }; 992*4882a593Smuzhiyun 993*4882a593Smuzhiyun /* WIFI/BT module */ 994*4882a593Smuzhiyun mmc@700b0000 { 995*4882a593Smuzhiyun status = "disabled"; 996*4882a593Smuzhiyun }; 997*4882a593Smuzhiyun 998*4882a593Smuzhiyun /* external SD/MMC */ 999*4882a593Smuzhiyun mmc@700b0400 { 1000*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 1001*4882a593Smuzhiyun power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 1002*4882a593Smuzhiyun wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; 1003*4882a593Smuzhiyun status = "okay"; 1004*4882a593Smuzhiyun bus-width = <4>; 1005*4882a593Smuzhiyun vqmmc-supply = <&vddio_sdmmc3>; 1006*4882a593Smuzhiyun }; 1007*4882a593Smuzhiyun 1008*4882a593Smuzhiyun /* EMMC 4.51 */ 1009*4882a593Smuzhiyun mmc@700b0600 { 1010*4882a593Smuzhiyun status = "okay"; 1011*4882a593Smuzhiyun bus-width = <8>; 1012*4882a593Smuzhiyun non-removable; 1013*4882a593Smuzhiyun }; 1014*4882a593Smuzhiyun 1015*4882a593Smuzhiyun backlight: backlight { 1016*4882a593Smuzhiyun compatible = "pwm-backlight"; 1017*4882a593Smuzhiyun 1018*4882a593Smuzhiyun enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; 1019*4882a593Smuzhiyun power-supply = <&vdd_led>; 1020*4882a593Smuzhiyun pwms = <&pwm 1 1000000>; 1021*4882a593Smuzhiyun 1022*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 1023*4882a593Smuzhiyun default-brightness-level = <6>; 1024*4882a593Smuzhiyun 1025*4882a593Smuzhiyun backlight-boot-off; 1026*4882a593Smuzhiyun }; 1027*4882a593Smuzhiyun 1028*4882a593Smuzhiyun clk32k_in: clock@0 { 1029*4882a593Smuzhiyun compatible = "fixed-clock"; 1030*4882a593Smuzhiyun clock-frequency = <32768>; 1031*4882a593Smuzhiyun #clock-cells = <0>; 1032*4882a593Smuzhiyun }; 1033*4882a593Smuzhiyun 1034*4882a593Smuzhiyun gpio-keys { 1035*4882a593Smuzhiyun compatible = "gpio-keys"; 1036*4882a593Smuzhiyun 1037*4882a593Smuzhiyun lid { 1038*4882a593Smuzhiyun label = "Lid"; 1039*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; 1040*4882a593Smuzhiyun linux,input-type = <5>; 1041*4882a593Smuzhiyun linux,code = <0>; 1042*4882a593Smuzhiyun debounce-interval = <1>; 1043*4882a593Smuzhiyun wakeup-source; 1044*4882a593Smuzhiyun }; 1045*4882a593Smuzhiyun 1046*4882a593Smuzhiyun power { 1047*4882a593Smuzhiyun label = "Power"; 1048*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; 1049*4882a593Smuzhiyun linux,code = <KEY_POWER>; 1050*4882a593Smuzhiyun debounce-interval = <10>; 1051*4882a593Smuzhiyun wakeup-source; 1052*4882a593Smuzhiyun }; 1053*4882a593Smuzhiyun }; 1054*4882a593Smuzhiyun 1055*4882a593Smuzhiyun panel: panel { 1056*4882a593Smuzhiyun compatible = "innolux,n116bge"; 1057*4882a593Smuzhiyun power-supply = <&vdd_3v3_panel>; 1058*4882a593Smuzhiyun backlight = <&backlight>; 1059*4882a593Smuzhiyun ddc-i2c-bus = <&dpaux>; 1060*4882a593Smuzhiyun }; 1061*4882a593Smuzhiyun 1062*4882a593Smuzhiyun vdd_mux: regulator@0 { 1063*4882a593Smuzhiyun compatible = "regulator-fixed"; 1064*4882a593Smuzhiyun regulator-name = "+VDD_MUX"; 1065*4882a593Smuzhiyun regulator-min-microvolt = <19000000>; 1066*4882a593Smuzhiyun regulator-max-microvolt = <19000000>; 1067*4882a593Smuzhiyun regulator-always-on; 1068*4882a593Smuzhiyun regulator-boot-on; 1069*4882a593Smuzhiyun }; 1070*4882a593Smuzhiyun 1071*4882a593Smuzhiyun vdd_5v0_sys: regulator@1 { 1072*4882a593Smuzhiyun compatible = "regulator-fixed"; 1073*4882a593Smuzhiyun regulator-name = "+5V_SYS"; 1074*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 1075*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 1076*4882a593Smuzhiyun regulator-always-on; 1077*4882a593Smuzhiyun regulator-boot-on; 1078*4882a593Smuzhiyun vin-supply = <&vdd_mux>; 1079*4882a593Smuzhiyun }; 1080*4882a593Smuzhiyun 1081*4882a593Smuzhiyun vdd_3v3_sys: regulator@2 { 1082*4882a593Smuzhiyun compatible = "regulator-fixed"; 1083*4882a593Smuzhiyun regulator-name = "+3.3V_SYS"; 1084*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 1085*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 1086*4882a593Smuzhiyun regulator-always-on; 1087*4882a593Smuzhiyun regulator-boot-on; 1088*4882a593Smuzhiyun vin-supply = <&vdd_mux>; 1089*4882a593Smuzhiyun }; 1090*4882a593Smuzhiyun 1091*4882a593Smuzhiyun vdd_3v3_run: regulator@3 { 1092*4882a593Smuzhiyun compatible = "regulator-fixed"; 1093*4882a593Smuzhiyun regulator-name = "+3.3V_RUN"; 1094*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 1095*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 1096*4882a593Smuzhiyun regulator-always-on; 1097*4882a593Smuzhiyun regulator-boot-on; 1098*4882a593Smuzhiyun gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; 1099*4882a593Smuzhiyun enable-active-high; 1100*4882a593Smuzhiyun vin-supply = <&vdd_3v3_sys>; 1101*4882a593Smuzhiyun }; 1102*4882a593Smuzhiyun 1103*4882a593Smuzhiyun vdd_3v3_hdmi: regulator@4 { 1104*4882a593Smuzhiyun compatible = "regulator-fixed"; 1105*4882a593Smuzhiyun regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; 1106*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 1107*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 1108*4882a593Smuzhiyun vin-supply = <&vdd_3v3_run>; 1109*4882a593Smuzhiyun }; 1110*4882a593Smuzhiyun 1111*4882a593Smuzhiyun vdd_led: regulator@5 { 1112*4882a593Smuzhiyun compatible = "regulator-fixed"; 1113*4882a593Smuzhiyun regulator-name = "+VDD_LED"; 1114*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 1115*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 1116*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; 1117*4882a593Smuzhiyun enable-active-high; 1118*4882a593Smuzhiyun vin-supply = <&vdd_mux>; 1119*4882a593Smuzhiyun }; 1120*4882a593Smuzhiyun 1121*4882a593Smuzhiyun vdd_usb1_vbus: regulator@6 { 1122*4882a593Smuzhiyun compatible = "regulator-fixed"; 1123*4882a593Smuzhiyun regulator-name = "+5V_USB_HS"; 1124*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 1125*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 1126*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; 1127*4882a593Smuzhiyun enable-active-high; 1128*4882a593Smuzhiyun gpio-open-drain; 1129*4882a593Smuzhiyun vin-supply = <&vdd_5v0_sys>; 1130*4882a593Smuzhiyun }; 1131*4882a593Smuzhiyun 1132*4882a593Smuzhiyun vdd_usb3_vbus: regulator@7 { 1133*4882a593Smuzhiyun compatible = "regulator-fixed"; 1134*4882a593Smuzhiyun regulator-name = "+5V_USB_SS"; 1135*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 1136*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 1137*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; 1138*4882a593Smuzhiyun enable-active-high; 1139*4882a593Smuzhiyun gpio-open-drain; 1140*4882a593Smuzhiyun vin-supply = <&vdd_5v0_sys>; 1141*4882a593Smuzhiyun }; 1142*4882a593Smuzhiyun 1143*4882a593Smuzhiyun vdd_3v3_panel: regulator@8 { 1144*4882a593Smuzhiyun compatible = "regulator-fixed"; 1145*4882a593Smuzhiyun regulator-name = "+3.3V_PANEL"; 1146*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 1147*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 1148*4882a593Smuzhiyun gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; 1149*4882a593Smuzhiyun enable-active-high; 1150*4882a593Smuzhiyun vin-supply = <&vdd_3v3_sys>; 1151*4882a593Smuzhiyun }; 1152*4882a593Smuzhiyun 1153*4882a593Smuzhiyun vdd_hdmi_pll: regulator@9 { 1154*4882a593Smuzhiyun compatible = "regulator-fixed"; 1155*4882a593Smuzhiyun regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE"; 1156*4882a593Smuzhiyun regulator-min-microvolt = <1050000>; 1157*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 1158*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; 1159*4882a593Smuzhiyun vin-supply = <&vdd_1v05_run>; 1160*4882a593Smuzhiyun }; 1161*4882a593Smuzhiyun 1162*4882a593Smuzhiyun vdd_5v0_hdmi: regulator@10 { 1163*4882a593Smuzhiyun compatible = "regulator-fixed"; 1164*4882a593Smuzhiyun regulator-name = "+5V_HDMI_CON"; 1165*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 1166*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 1167*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; 1168*4882a593Smuzhiyun enable-active-high; 1169*4882a593Smuzhiyun vin-supply = <&vdd_5v0_sys>; 1170*4882a593Smuzhiyun }; 1171*4882a593Smuzhiyun 1172*4882a593Smuzhiyun vdd_5v0_ts: regulator@11 { 1173*4882a593Smuzhiyun compatible = "regulator-fixed"; 1174*4882a593Smuzhiyun regulator-name = "+5V_VDD_TS"; 1175*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 1176*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 1177*4882a593Smuzhiyun regulator-always-on; 1178*4882a593Smuzhiyun regulator-boot-on; 1179*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; 1180*4882a593Smuzhiyun enable-active-high; 1181*4882a593Smuzhiyun }; 1182*4882a593Smuzhiyun 1183*4882a593Smuzhiyun vdd_3v3_lp0: regulator@12 { 1184*4882a593Smuzhiyun compatible = "regulator-fixed"; 1185*4882a593Smuzhiyun regulator-name = "+3.3V_LP0"; 1186*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 1187*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 1188*4882a593Smuzhiyun /* 1189*4882a593Smuzhiyun * TODO: find a way to wire this up with the USB EHCI 1190*4882a593Smuzhiyun * controllers so that it can be enabled on demand. 1191*4882a593Smuzhiyun */ 1192*4882a593Smuzhiyun regulator-always-on; 1193*4882a593Smuzhiyun gpio = <&as3722 2 GPIO_ACTIVE_HIGH>; 1194*4882a593Smuzhiyun enable-active-high; 1195*4882a593Smuzhiyun vin-supply = <&vdd_3v3_sys>; 1196*4882a593Smuzhiyun }; 1197*4882a593Smuzhiyun}; 1198