xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/tegra124-apalis.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 OR X11
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2016-2019 Toradex AG
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include "tegra124.dtsi"
7*4882a593Smuzhiyun#include "tegra124-apalis-emc.dtsi"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/*
10*4882a593Smuzhiyun * Toradex Apalis TK1 Module Device Tree
11*4882a593Smuzhiyun * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	memory@80000000 {
15*4882a593Smuzhiyun		reg = <0x0 0x80000000 0x0 0x80000000>;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	pcie@1003000 {
19*4882a593Smuzhiyun		status = "okay";
20*4882a593Smuzhiyun		avddio-pex-supply = <&reg_1v05_vdd>;
21*4882a593Smuzhiyun		avdd-pex-pll-supply = <&reg_1v05_vdd>;
22*4882a593Smuzhiyun		avdd-pll-erefe-supply = <&reg_1v05_avdd>;
23*4882a593Smuzhiyun		dvddio-pex-supply = <&reg_1v05_vdd>;
24*4882a593Smuzhiyun		hvdd-pex-pll-e-supply = <&reg_module_3v3>;
25*4882a593Smuzhiyun		hvdd-pex-supply = <&reg_module_3v3>;
26*4882a593Smuzhiyun		vddio-pex-ctl-supply = <&reg_module_3v3>;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun		/* Apalis PCIe (additional lane Apalis type specific) */
29*4882a593Smuzhiyun		pci@1,0 {
30*4882a593Smuzhiyun			/* PCIE1_RX/TX and TS_DIFF1/2 */
31*4882a593Smuzhiyun			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
32*4882a593Smuzhiyun			       <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
33*4882a593Smuzhiyun			phy-names = "pcie-0", "pcie-1";
34*4882a593Smuzhiyun		};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun		/* I210 Gigabit Ethernet Controller (On-module) */
37*4882a593Smuzhiyun		pci@2,0 {
38*4882a593Smuzhiyun			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
39*4882a593Smuzhiyun			phy-names = "pcie-0";
40*4882a593Smuzhiyun			status = "okay";
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun			ethernet@0,0 {
43*4882a593Smuzhiyun				reg = <0 0 0 0 0>;
44*4882a593Smuzhiyun				local-mac-address = [00 00 00 00 00 00];
45*4882a593Smuzhiyun			};
46*4882a593Smuzhiyun		};
47*4882a593Smuzhiyun	};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun	host1x@50000000 {
50*4882a593Smuzhiyun		hdmi@54280000 {
51*4882a593Smuzhiyun			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
52*4882a593Smuzhiyun			nvidia,hpd-gpio =
53*4882a593Smuzhiyun				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
54*4882a593Smuzhiyun			pll-supply = <&reg_1v05_avdd_hdmi_pll>;
55*4882a593Smuzhiyun			vdd-supply = <&reg_3v3_avdd_hdmi>;
56*4882a593Smuzhiyun		};
57*4882a593Smuzhiyun	};
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun	gpu@0,57000000 {
60*4882a593Smuzhiyun		/*
61*4882a593Smuzhiyun		 * Node left disabled on purpose - the bootloader will enable
62*4882a593Smuzhiyun		 * it after having set the VPR up
63*4882a593Smuzhiyun		 */
64*4882a593Smuzhiyun		vdd-supply = <&reg_vdd_gpu>;
65*4882a593Smuzhiyun	};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun	pinmux@70000868 {
68*4882a593Smuzhiyun		pinctrl-names = "default";
69*4882a593Smuzhiyun		pinctrl-0 = <&state_default>;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun		state_default: pinmux {
72*4882a593Smuzhiyun			/* Analogue Audio (On-module) */
73*4882a593Smuzhiyun			dap3-fs-pp0 {
74*4882a593Smuzhiyun				nvidia,pins = "dap3_fs_pp0";
75*4882a593Smuzhiyun				nvidia,function = "i2s2";
76*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
77*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
78*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
79*4882a593Smuzhiyun			};
80*4882a593Smuzhiyun			dap3-din-pp1 {
81*4882a593Smuzhiyun				nvidia,pins = "dap3_din_pp1";
82*4882a593Smuzhiyun				nvidia,function = "i2s2";
83*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
85*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
86*4882a593Smuzhiyun			};
87*4882a593Smuzhiyun			dap3-dout-pp2 {
88*4882a593Smuzhiyun				nvidia,pins = "dap3_dout_pp2";
89*4882a593Smuzhiyun				nvidia,function = "i2s2";
90*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
91*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
92*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
93*4882a593Smuzhiyun			};
94*4882a593Smuzhiyun			dap3-sclk-pp3 {
95*4882a593Smuzhiyun				nvidia,pins = "dap3_sclk_pp3";
96*4882a593Smuzhiyun				nvidia,function = "i2s2";
97*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
98*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
99*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
100*4882a593Smuzhiyun			};
101*4882a593Smuzhiyun			dap-mclk1-pw4 {
102*4882a593Smuzhiyun				nvidia,pins = "dap_mclk1_pw4";
103*4882a593Smuzhiyun				nvidia,function = "extperiph1";
104*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
105*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
106*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
107*4882a593Smuzhiyun			};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun			/* Apalis BKL1_ON */
110*4882a593Smuzhiyun			pbb5 {
111*4882a593Smuzhiyun				nvidia,pins = "pbb5";
112*4882a593Smuzhiyun				nvidia,function = "vgp5";
113*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
114*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
115*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
116*4882a593Smuzhiyun			};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun			/* Apalis BKL1_PWM */
119*4882a593Smuzhiyun			pu6 {
120*4882a593Smuzhiyun				nvidia,pins = "pu6";
121*4882a593Smuzhiyun				nvidia,function = "pwm3";
122*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
123*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
124*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
125*4882a593Smuzhiyun			};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun			/* Apalis CAM1_MCLK */
128*4882a593Smuzhiyun			cam-mclk-pcc0 {
129*4882a593Smuzhiyun				nvidia,pins = "cam_mclk_pcc0";
130*4882a593Smuzhiyun				nvidia,function = "vi_alt3";
131*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
133*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
134*4882a593Smuzhiyun			};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun			/* Apalis Digital Audio */
137*4882a593Smuzhiyun			dap2-fs-pa2 {
138*4882a593Smuzhiyun				nvidia,pins = "dap2_fs_pa2";
139*4882a593Smuzhiyun				nvidia,function = "hda";
140*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
142*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
143*4882a593Smuzhiyun			};
144*4882a593Smuzhiyun			dap2-sclk-pa3 {
145*4882a593Smuzhiyun				nvidia,pins = "dap2_sclk_pa3";
146*4882a593Smuzhiyun				nvidia,function = "hda";
147*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
148*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
149*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
150*4882a593Smuzhiyun			};
151*4882a593Smuzhiyun			dap2-din-pa4 {
152*4882a593Smuzhiyun				nvidia,pins = "dap2_din_pa4";
153*4882a593Smuzhiyun				nvidia,function = "hda";
154*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
156*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
157*4882a593Smuzhiyun			};
158*4882a593Smuzhiyun			dap2-dout-pa5 {
159*4882a593Smuzhiyun				nvidia,pins = "dap2_dout_pa5";
160*4882a593Smuzhiyun				nvidia,function = "hda";
161*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
162*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
163*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
164*4882a593Smuzhiyun			};
165*4882a593Smuzhiyun			pbb3 { /* DAP1_RESET */
166*4882a593Smuzhiyun				nvidia,pins = "pbb3";
167*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
168*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
169*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
170*4882a593Smuzhiyun			};
171*4882a593Smuzhiyun			clk3-out-pee0 {
172*4882a593Smuzhiyun				nvidia,pins = "clk3_out_pee0";
173*4882a593Smuzhiyun				nvidia,function = "extperiph3";
174*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
175*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
176*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
177*4882a593Smuzhiyun			};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun			/* Apalis GPIO */
180*4882a593Smuzhiyun			ddc-scl-pv4 {
181*4882a593Smuzhiyun				nvidia,pins = "ddc_scl_pv4";
182*4882a593Smuzhiyun				nvidia,function = "rsvd2";
183*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
184*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
185*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
186*4882a593Smuzhiyun			};
187*4882a593Smuzhiyun			ddc-sda-pv5 {
188*4882a593Smuzhiyun				nvidia,pins = "ddc_sda_pv5";
189*4882a593Smuzhiyun				nvidia,function = "rsvd2";
190*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
191*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
192*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
193*4882a593Smuzhiyun			};
194*4882a593Smuzhiyun			pex-l0-rst-n-pdd1 {
195*4882a593Smuzhiyun				nvidia,pins = "pex_l0_rst_n_pdd1";
196*4882a593Smuzhiyun				nvidia,function = "rsvd2";
197*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
199*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
200*4882a593Smuzhiyun			};
201*4882a593Smuzhiyun			pex-l0-clkreq-n-pdd2 {
202*4882a593Smuzhiyun				nvidia,pins = "pex_l0_clkreq_n_pdd2";
203*4882a593Smuzhiyun				nvidia,function = "rsvd2";
204*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
205*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
206*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
207*4882a593Smuzhiyun			};
208*4882a593Smuzhiyun			pex-l1-rst-n-pdd5 {
209*4882a593Smuzhiyun				nvidia,pins = "pex_l1_rst_n_pdd5";
210*4882a593Smuzhiyun				nvidia,function = "rsvd2";
211*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
212*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
213*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
214*4882a593Smuzhiyun			};
215*4882a593Smuzhiyun			pex-l1-clkreq-n-pdd6 {
216*4882a593Smuzhiyun				nvidia,pins = "pex_l1_clkreq_n_pdd6";
217*4882a593Smuzhiyun				nvidia,function = "rsvd2";
218*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
219*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
220*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
221*4882a593Smuzhiyun			};
222*4882a593Smuzhiyun			dp-hpd-pff0 {
223*4882a593Smuzhiyun				nvidia,pins = "dp_hpd_pff0";
224*4882a593Smuzhiyun				nvidia,function = "dp";
225*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
226*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
227*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
228*4882a593Smuzhiyun			};
229*4882a593Smuzhiyun			pff2 {
230*4882a593Smuzhiyun				nvidia,pins = "pff2";
231*4882a593Smuzhiyun				nvidia,function = "rsvd2";
232*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
233*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
234*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
235*4882a593Smuzhiyun			};
236*4882a593Smuzhiyun			owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
237*4882a593Smuzhiyun				nvidia,pins = "owr";
238*4882a593Smuzhiyun				nvidia,function = "rsvd2";
239*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
240*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
241*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
242*4882a593Smuzhiyun				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
243*4882a593Smuzhiyun			};
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun			/* Apalis HDMI1_CEC */
246*4882a593Smuzhiyun			hdmi-cec-pee3 {
247*4882a593Smuzhiyun				nvidia,pins = "hdmi_cec_pee3";
248*4882a593Smuzhiyun				nvidia,function = "cec";
249*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
250*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
251*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
252*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
253*4882a593Smuzhiyun			};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun			/* Apalis HDMI1_HPD */
256*4882a593Smuzhiyun			hdmi-int-pn7 {
257*4882a593Smuzhiyun				nvidia,pins = "hdmi_int_pn7";
258*4882a593Smuzhiyun				nvidia,function = "rsvd1";
259*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
260*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
261*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
262*4882a593Smuzhiyun				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
263*4882a593Smuzhiyun			};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun			/* Apalis I2C1 */
266*4882a593Smuzhiyun			gen1-i2c-scl-pc4 {
267*4882a593Smuzhiyun				nvidia,pins = "gen1_i2c_scl_pc4";
268*4882a593Smuzhiyun				nvidia,function = "i2c1";
269*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
270*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
271*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
272*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
273*4882a593Smuzhiyun			};
274*4882a593Smuzhiyun			gen1-i2c-sda-pc5 {
275*4882a593Smuzhiyun				nvidia,pins = "gen1_i2c_sda_pc5";
276*4882a593Smuzhiyun				nvidia,function = "i2c1";
277*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
278*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
279*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
280*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
281*4882a593Smuzhiyun			};
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun			/* Apalis I2C2 (DDC) */
284*4882a593Smuzhiyun			gen2-i2c-scl-pt5 {
285*4882a593Smuzhiyun				nvidia,pins = "gen2_i2c_scl_pt5";
286*4882a593Smuzhiyun				nvidia,function = "i2c2";
287*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
288*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
289*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
290*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
291*4882a593Smuzhiyun			};
292*4882a593Smuzhiyun			gen2-i2c-sda-pt6 {
293*4882a593Smuzhiyun				nvidia,pins = "gen2_i2c_sda_pt6";
294*4882a593Smuzhiyun				nvidia,function = "i2c2";
295*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
296*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
297*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
298*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
299*4882a593Smuzhiyun			};
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun			/* Apalis I2C3 (CAM) */
302*4882a593Smuzhiyun			cam-i2c-scl-pbb1 {
303*4882a593Smuzhiyun				nvidia,pins = "cam_i2c_scl_pbb1";
304*4882a593Smuzhiyun				nvidia,function = "i2c3";
305*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
306*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
307*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
308*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
309*4882a593Smuzhiyun			};
310*4882a593Smuzhiyun			cam-i2c-sda-pbb2 {
311*4882a593Smuzhiyun				nvidia,pins = "cam_i2c_sda_pbb2";
312*4882a593Smuzhiyun				nvidia,function = "i2c3";
313*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
314*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
315*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
316*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
317*4882a593Smuzhiyun			};
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun			/* Apalis MMC1 */
320*4882a593Smuzhiyun			sdmmc1-cd-n-pv3 { /* CD# GPIO */
321*4882a593Smuzhiyun				nvidia,pins = "sdmmc1_wp_n_pv3";
322*4882a593Smuzhiyun				nvidia,function = "sdmmc1";
323*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
324*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
325*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
326*4882a593Smuzhiyun			};
327*4882a593Smuzhiyun			clk2-out-pw5 { /* D5 GPIO */
328*4882a593Smuzhiyun				nvidia,pins = "clk2_out_pw5";
329*4882a593Smuzhiyun				nvidia,function = "rsvd2";
330*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
331*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
332*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
333*4882a593Smuzhiyun			};
334*4882a593Smuzhiyun			sdmmc1-dat3-py4 {
335*4882a593Smuzhiyun				nvidia,pins = "sdmmc1_dat3_py4";
336*4882a593Smuzhiyun				nvidia,function = "sdmmc1";
337*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
338*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
339*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
340*4882a593Smuzhiyun			};
341*4882a593Smuzhiyun			sdmmc1-dat2-py5 {
342*4882a593Smuzhiyun				nvidia,pins = "sdmmc1_dat2_py5";
343*4882a593Smuzhiyun				nvidia,function = "sdmmc1";
344*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
345*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
346*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
347*4882a593Smuzhiyun			};
348*4882a593Smuzhiyun			sdmmc1-dat1-py6 {
349*4882a593Smuzhiyun				nvidia,pins = "sdmmc1_dat1_py6";
350*4882a593Smuzhiyun				nvidia,function = "sdmmc1";
351*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
352*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
353*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
354*4882a593Smuzhiyun			};
355*4882a593Smuzhiyun			sdmmc1-dat0-py7 {
356*4882a593Smuzhiyun				nvidia,pins = "sdmmc1_dat0_py7";
357*4882a593Smuzhiyun				nvidia,function = "sdmmc1";
358*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
359*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
360*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
361*4882a593Smuzhiyun			};
362*4882a593Smuzhiyun			sdmmc1-clk-pz0 {
363*4882a593Smuzhiyun				nvidia,pins = "sdmmc1_clk_pz0";
364*4882a593Smuzhiyun				nvidia,function = "sdmmc1";
365*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
366*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
367*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
368*4882a593Smuzhiyun			};
369*4882a593Smuzhiyun			sdmmc1-cmd-pz1 {
370*4882a593Smuzhiyun				nvidia,pins = "sdmmc1_cmd_pz1";
371*4882a593Smuzhiyun				nvidia,function = "sdmmc1";
372*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
373*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
374*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
375*4882a593Smuzhiyun			};
376*4882a593Smuzhiyun			clk2-req-pcc5 { /* D4 GPIO */
377*4882a593Smuzhiyun				nvidia,pins = "clk2_req_pcc5";
378*4882a593Smuzhiyun				nvidia,function = "rsvd2";
379*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
380*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
381*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
382*4882a593Smuzhiyun			};
383*4882a593Smuzhiyun			sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */
384*4882a593Smuzhiyun				nvidia,pins = "sdmmc3_clk_lb_in_pee5";
385*4882a593Smuzhiyun				nvidia,function = "rsvd2";
386*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
387*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
388*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
389*4882a593Smuzhiyun			};
390*4882a593Smuzhiyun			usb-vbus-en2-pff1 { /* D7 GPIO */
391*4882a593Smuzhiyun				nvidia,pins = "usb_vbus_en2_pff1";
392*4882a593Smuzhiyun				nvidia,function = "rsvd2";
393*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
394*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
395*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
396*4882a593Smuzhiyun			};
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun			/* Apalis PWM */
399*4882a593Smuzhiyun			ph0 {
400*4882a593Smuzhiyun				nvidia,pins = "ph0";
401*4882a593Smuzhiyun				nvidia,function = "pwm0";
402*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
403*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
404*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
405*4882a593Smuzhiyun			};
406*4882a593Smuzhiyun			ph1 {
407*4882a593Smuzhiyun				nvidia,pins = "ph1";
408*4882a593Smuzhiyun				nvidia,function = "pwm1";
409*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
410*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
411*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
412*4882a593Smuzhiyun			};
413*4882a593Smuzhiyun			ph2 {
414*4882a593Smuzhiyun				nvidia,pins = "ph2";
415*4882a593Smuzhiyun				nvidia,function = "pwm2";
416*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
417*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
418*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
419*4882a593Smuzhiyun			};
420*4882a593Smuzhiyun			/* PWM3 active on pu6 being Apalis BKL1_PWM as well */
421*4882a593Smuzhiyun			ph3 {
422*4882a593Smuzhiyun				nvidia,pins = "ph3";
423*4882a593Smuzhiyun				nvidia,function = "pwm3";
424*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
425*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
426*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
427*4882a593Smuzhiyun			};
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun			/* Apalis SATA1_ACT# */
430*4882a593Smuzhiyun			dap1-dout-pn2 {
431*4882a593Smuzhiyun				nvidia,pins = "dap1_dout_pn2";
432*4882a593Smuzhiyun				nvidia,function = "gmi";
433*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
434*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
435*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
436*4882a593Smuzhiyun			};
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun			/* Apalis SD1 */
439*4882a593Smuzhiyun			sdmmc3-clk-pa6 {
440*4882a593Smuzhiyun				nvidia,pins = "sdmmc3_clk_pa6";
441*4882a593Smuzhiyun				nvidia,function = "sdmmc3";
442*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
443*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
444*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
445*4882a593Smuzhiyun			};
446*4882a593Smuzhiyun			sdmmc3-cmd-pa7 {
447*4882a593Smuzhiyun				nvidia,pins = "sdmmc3_cmd_pa7";
448*4882a593Smuzhiyun				nvidia,function = "sdmmc3";
449*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
450*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
451*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
452*4882a593Smuzhiyun			};
453*4882a593Smuzhiyun			sdmmc3-dat3-pb4 {
454*4882a593Smuzhiyun				nvidia,pins = "sdmmc3_dat3_pb4";
455*4882a593Smuzhiyun				nvidia,function = "sdmmc3";
456*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
457*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
458*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
459*4882a593Smuzhiyun			};
460*4882a593Smuzhiyun			sdmmc3-dat2-pb5 {
461*4882a593Smuzhiyun				nvidia,pins = "sdmmc3_dat2_pb5";
462*4882a593Smuzhiyun				nvidia,function = "sdmmc3";
463*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
464*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
465*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
466*4882a593Smuzhiyun			};
467*4882a593Smuzhiyun			sdmmc3-dat1-pb6 {
468*4882a593Smuzhiyun				nvidia,pins = "sdmmc3_dat1_pb6";
469*4882a593Smuzhiyun				nvidia,function = "sdmmc3";
470*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
471*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
472*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
473*4882a593Smuzhiyun			};
474*4882a593Smuzhiyun			sdmmc3-dat0-pb7 {
475*4882a593Smuzhiyun				nvidia,pins = "sdmmc3_dat0_pb7";
476*4882a593Smuzhiyun				nvidia,function = "sdmmc3";
477*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
478*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
479*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
480*4882a593Smuzhiyun			};
481*4882a593Smuzhiyun			sdmmc3-cd-n-pv2 { /* CD# GPIO */
482*4882a593Smuzhiyun				nvidia,pins = "sdmmc3_cd_n_pv2";
483*4882a593Smuzhiyun				nvidia,function = "rsvd3";
484*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
485*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
486*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
487*4882a593Smuzhiyun			};
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun			/* Apalis SPDIF */
490*4882a593Smuzhiyun			spdif-out-pk5 {
491*4882a593Smuzhiyun				nvidia,pins = "spdif_out_pk5";
492*4882a593Smuzhiyun				nvidia,function = "spdif";
493*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
494*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
495*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
496*4882a593Smuzhiyun			};
497*4882a593Smuzhiyun			spdif-in-pk6 {
498*4882a593Smuzhiyun				nvidia,pins = "spdif_in_pk6";
499*4882a593Smuzhiyun				nvidia,function = "spdif";
500*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
501*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
502*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
503*4882a593Smuzhiyun			};
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun			/* Apalis SPI1 */
506*4882a593Smuzhiyun			ulpi-clk-py0 {
507*4882a593Smuzhiyun				nvidia,pins = "ulpi_clk_py0";
508*4882a593Smuzhiyun				nvidia,function = "spi1";
509*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
510*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
511*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
512*4882a593Smuzhiyun			};
513*4882a593Smuzhiyun			ulpi-dir-py1 {
514*4882a593Smuzhiyun				nvidia,pins = "ulpi_dir_py1";
515*4882a593Smuzhiyun				nvidia,function = "spi1";
516*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
517*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
518*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
519*4882a593Smuzhiyun			};
520*4882a593Smuzhiyun			ulpi-nxt-py2 {
521*4882a593Smuzhiyun				nvidia,pins = "ulpi_nxt_py2";
522*4882a593Smuzhiyun				nvidia,function = "spi1";
523*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
524*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
525*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
526*4882a593Smuzhiyun			};
527*4882a593Smuzhiyun			ulpi-stp-py3 {
528*4882a593Smuzhiyun				nvidia,pins = "ulpi_stp_py3";
529*4882a593Smuzhiyun				nvidia,function = "spi1";
530*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
531*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
532*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
533*4882a593Smuzhiyun			};
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun			/* Apalis SPI2 */
536*4882a593Smuzhiyun			pg5 {
537*4882a593Smuzhiyun				nvidia,pins = "pg5";
538*4882a593Smuzhiyun				nvidia,function = "spi4";
539*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
540*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
541*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
542*4882a593Smuzhiyun			};
543*4882a593Smuzhiyun			pg6 {
544*4882a593Smuzhiyun				nvidia,pins = "pg6";
545*4882a593Smuzhiyun				nvidia,function = "spi4";
546*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
547*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
548*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
549*4882a593Smuzhiyun			};
550*4882a593Smuzhiyun			pg7 {
551*4882a593Smuzhiyun				nvidia,pins = "pg7";
552*4882a593Smuzhiyun				nvidia,function = "spi4";
553*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
554*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
555*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
556*4882a593Smuzhiyun			};
557*4882a593Smuzhiyun			pi3 {
558*4882a593Smuzhiyun				nvidia,pins = "pi3";
559*4882a593Smuzhiyun				nvidia,function = "spi4";
560*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
561*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
562*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
563*4882a593Smuzhiyun			};
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun			/* Apalis UART1 */
566*4882a593Smuzhiyun			pb1 { /* DCD GPIO */
567*4882a593Smuzhiyun				nvidia,pins = "pb1";
568*4882a593Smuzhiyun				nvidia,function = "rsvd2";
569*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
570*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
571*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
572*4882a593Smuzhiyun			};
573*4882a593Smuzhiyun			pk7 { /* RI GPIO */
574*4882a593Smuzhiyun				nvidia,pins = "pk7";
575*4882a593Smuzhiyun				nvidia,function = "rsvd2";
576*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
577*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
578*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
579*4882a593Smuzhiyun			};
580*4882a593Smuzhiyun			uart1-txd-pu0 {
581*4882a593Smuzhiyun				nvidia,pins = "pu0";
582*4882a593Smuzhiyun				nvidia,function = "uarta";
583*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
584*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
585*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
586*4882a593Smuzhiyun			};
587*4882a593Smuzhiyun			uart1-rxd-pu1 {
588*4882a593Smuzhiyun				nvidia,pins = "pu1";
589*4882a593Smuzhiyun				nvidia,function = "uarta";
590*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
591*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
592*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
593*4882a593Smuzhiyun			};
594*4882a593Smuzhiyun			uart1-cts-n-pu2 {
595*4882a593Smuzhiyun				nvidia,pins = "pu2";
596*4882a593Smuzhiyun				nvidia,function = "uarta";
597*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
598*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
599*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
600*4882a593Smuzhiyun			};
601*4882a593Smuzhiyun			uart1-rts-n-pu3 {
602*4882a593Smuzhiyun				nvidia,pins = "pu3";
603*4882a593Smuzhiyun				nvidia,function = "uarta";
604*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
605*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
606*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
607*4882a593Smuzhiyun			};
608*4882a593Smuzhiyun			uart3-cts-n-pa1 { /* DSR GPIO */
609*4882a593Smuzhiyun				nvidia,pins = "uart3_cts_n_pa1";
610*4882a593Smuzhiyun				nvidia,function = "gmi";
611*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
612*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
613*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
614*4882a593Smuzhiyun			};
615*4882a593Smuzhiyun			uart3-rts-n-pc0 { /* DTR GPIO */
616*4882a593Smuzhiyun				nvidia,pins = "uart3_rts_n_pc0";
617*4882a593Smuzhiyun				nvidia,function = "gmi";
618*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
619*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
620*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
621*4882a593Smuzhiyun			};
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun			/* Apalis UART2 */
624*4882a593Smuzhiyun			uart2-txd-pc2 {
625*4882a593Smuzhiyun				nvidia,pins = "uart2_txd_pc2";
626*4882a593Smuzhiyun				nvidia,function = "irda";
627*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
628*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
629*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
630*4882a593Smuzhiyun			};
631*4882a593Smuzhiyun			uart2-rxd-pc3 {
632*4882a593Smuzhiyun				nvidia,pins = "uart2_rxd_pc3";
633*4882a593Smuzhiyun				nvidia,function = "irda";
634*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
635*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
636*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
637*4882a593Smuzhiyun			};
638*4882a593Smuzhiyun			uart2-cts-n-pj5 {
639*4882a593Smuzhiyun				nvidia,pins = "uart2_cts_n_pj5";
640*4882a593Smuzhiyun				nvidia,function = "uartb";
641*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
642*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
643*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
644*4882a593Smuzhiyun			};
645*4882a593Smuzhiyun			uart2-rts-n-pj6 {
646*4882a593Smuzhiyun				nvidia,pins = "uart2_rts_n_pj6";
647*4882a593Smuzhiyun				nvidia,function = "uartb";
648*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
649*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
650*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
651*4882a593Smuzhiyun			};
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun			/* Apalis UART3 */
654*4882a593Smuzhiyun			uart3-txd-pw6 {
655*4882a593Smuzhiyun				nvidia,pins = "uart3_txd_pw6";
656*4882a593Smuzhiyun				nvidia,function = "uartc";
657*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
658*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
659*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
660*4882a593Smuzhiyun			};
661*4882a593Smuzhiyun			uart3-rxd-pw7 {
662*4882a593Smuzhiyun				nvidia,pins = "uart3_rxd_pw7";
663*4882a593Smuzhiyun				nvidia,function = "uartc";
664*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
665*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
666*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
667*4882a593Smuzhiyun			};
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun			/* Apalis UART4 */
670*4882a593Smuzhiyun			uart4-rxd-pb0 {
671*4882a593Smuzhiyun				nvidia,pins = "pb0";
672*4882a593Smuzhiyun				nvidia,function = "uartd";
673*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
674*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
675*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
676*4882a593Smuzhiyun			};
677*4882a593Smuzhiyun			uart4-txd-pj7 {
678*4882a593Smuzhiyun				nvidia,pins = "pj7";
679*4882a593Smuzhiyun				nvidia,function = "uartd";
680*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
681*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
682*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
683*4882a593Smuzhiyun			};
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun			/* Apalis USBH_EN */
686*4882a593Smuzhiyun			usb-vbus-en1-pn5 {
687*4882a593Smuzhiyun				nvidia,pins = "usb_vbus_en1_pn5";
688*4882a593Smuzhiyun				nvidia,function = "rsvd2";
689*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
690*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
691*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
692*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
693*4882a593Smuzhiyun			};
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun			/* Apalis USBH_OC# */
696*4882a593Smuzhiyun			pbb0 {
697*4882a593Smuzhiyun				nvidia,pins = "pbb0";
698*4882a593Smuzhiyun				nvidia,function = "vgp6";
699*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
700*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
701*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
702*4882a593Smuzhiyun			};
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun			/* Apalis USBO1_EN */
705*4882a593Smuzhiyun			usb-vbus-en0-pn4 {
706*4882a593Smuzhiyun				nvidia,pins = "usb_vbus_en0_pn4";
707*4882a593Smuzhiyun				nvidia,function = "rsvd2";
708*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
709*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
710*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
711*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
712*4882a593Smuzhiyun			};
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun			/* Apalis USBO1_OC# */
715*4882a593Smuzhiyun			pbb4 {
716*4882a593Smuzhiyun				nvidia,pins = "pbb4";
717*4882a593Smuzhiyun				nvidia,function = "vgp4";
718*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
719*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
720*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
721*4882a593Smuzhiyun			};
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun			/* Apalis WAKE1_MICO */
724*4882a593Smuzhiyun			pex-wake-n-pdd3 {
725*4882a593Smuzhiyun				nvidia,pins = "pex_wake_n_pdd3";
726*4882a593Smuzhiyun				nvidia,function = "rsvd2";
727*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
728*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
729*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
730*4882a593Smuzhiyun			};
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun			/* CORE_PWR_REQ */
733*4882a593Smuzhiyun			core-pwr-req {
734*4882a593Smuzhiyun				nvidia,pins = "core_pwr_req";
735*4882a593Smuzhiyun				nvidia,function = "pwron";
736*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
737*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
738*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
739*4882a593Smuzhiyun			};
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun			/* CPU_PWR_REQ */
742*4882a593Smuzhiyun			cpu-pwr-req {
743*4882a593Smuzhiyun				nvidia,pins = "cpu_pwr_req";
744*4882a593Smuzhiyun				nvidia,function = "cpu";
745*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
746*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
747*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
748*4882a593Smuzhiyun			};
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun			/* DVFS */
751*4882a593Smuzhiyun			dvfs-pwm-px0 {
752*4882a593Smuzhiyun				nvidia,pins = "dvfs_pwm_px0";
753*4882a593Smuzhiyun				nvidia,function = "cldvfs";
754*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
755*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
756*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
757*4882a593Smuzhiyun			};
758*4882a593Smuzhiyun			dvfs-clk-px2 {
759*4882a593Smuzhiyun				nvidia,pins = "dvfs_clk_px2";
760*4882a593Smuzhiyun				nvidia,function = "cldvfs";
761*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
762*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
763*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
764*4882a593Smuzhiyun			};
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun			/* eMMC */
767*4882a593Smuzhiyun			sdmmc4-dat0-paa0 {
768*4882a593Smuzhiyun				nvidia,pins = "sdmmc4_dat0_paa0";
769*4882a593Smuzhiyun				nvidia,function = "sdmmc4";
770*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
771*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
772*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
773*4882a593Smuzhiyun			};
774*4882a593Smuzhiyun			sdmmc4-dat1-paa1 {
775*4882a593Smuzhiyun				nvidia,pins = "sdmmc4_dat1_paa1";
776*4882a593Smuzhiyun				nvidia,function = "sdmmc4";
777*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
778*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
779*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
780*4882a593Smuzhiyun			};
781*4882a593Smuzhiyun			sdmmc4-dat2-paa2 {
782*4882a593Smuzhiyun				nvidia,pins = "sdmmc4_dat2_paa2";
783*4882a593Smuzhiyun				nvidia,function = "sdmmc4";
784*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
785*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
786*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
787*4882a593Smuzhiyun			};
788*4882a593Smuzhiyun			sdmmc4-dat3-paa3 {
789*4882a593Smuzhiyun				nvidia,pins = "sdmmc4_dat3_paa3";
790*4882a593Smuzhiyun				nvidia,function = "sdmmc4";
791*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
792*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
793*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
794*4882a593Smuzhiyun			};
795*4882a593Smuzhiyun			sdmmc4-dat4-paa4 {
796*4882a593Smuzhiyun				nvidia,pins = "sdmmc4_dat4_paa4";
797*4882a593Smuzhiyun				nvidia,function = "sdmmc4";
798*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
799*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
800*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
801*4882a593Smuzhiyun			};
802*4882a593Smuzhiyun			sdmmc4-dat5-paa5 {
803*4882a593Smuzhiyun				nvidia,pins = "sdmmc4_dat5_paa5";
804*4882a593Smuzhiyun				nvidia,function = "sdmmc4";
805*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
806*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
807*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
808*4882a593Smuzhiyun			};
809*4882a593Smuzhiyun			sdmmc4-dat6-paa6 {
810*4882a593Smuzhiyun				nvidia,pins = "sdmmc4_dat6_paa6";
811*4882a593Smuzhiyun				nvidia,function = "sdmmc4";
812*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
813*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
814*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
815*4882a593Smuzhiyun			};
816*4882a593Smuzhiyun			sdmmc4-dat7-paa7 {
817*4882a593Smuzhiyun				nvidia,pins = "sdmmc4_dat7_paa7";
818*4882a593Smuzhiyun				nvidia,function = "sdmmc4";
819*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
820*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
821*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
822*4882a593Smuzhiyun			};
823*4882a593Smuzhiyun			sdmmc4-clk-pcc4 {
824*4882a593Smuzhiyun				nvidia,pins = "sdmmc4_clk_pcc4";
825*4882a593Smuzhiyun				nvidia,function = "sdmmc4";
826*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
827*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
828*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
829*4882a593Smuzhiyun			};
830*4882a593Smuzhiyun			sdmmc4-cmd-pt7 {
831*4882a593Smuzhiyun				nvidia,pins = "sdmmc4_cmd_pt7";
832*4882a593Smuzhiyun				nvidia,function = "sdmmc4";
833*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
834*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
835*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
836*4882a593Smuzhiyun			};
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun			/* JTAG_RTCK */
839*4882a593Smuzhiyun			jtag-rtck {
840*4882a593Smuzhiyun				nvidia,pins = "jtag_rtck";
841*4882a593Smuzhiyun				nvidia,function = "rtck";
842*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
843*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
844*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
845*4882a593Smuzhiyun			};
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun			/* LAN_DEV_OFF# */
848*4882a593Smuzhiyun			ulpi-data5-po6 {
849*4882a593Smuzhiyun				nvidia,pins = "ulpi_data5_po6";
850*4882a593Smuzhiyun				nvidia,function = "ulpi";
851*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
852*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
853*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
854*4882a593Smuzhiyun			};
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun			/* LAN_RESET# */
857*4882a593Smuzhiyun			kb-row10-ps2 {
858*4882a593Smuzhiyun				nvidia,pins = "kb_row10_ps2";
859*4882a593Smuzhiyun				nvidia,function = "rsvd2";
860*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
861*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
862*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
863*4882a593Smuzhiyun			};
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun			/* LAN_WAKE# */
866*4882a593Smuzhiyun			ulpi-data4-po5 {
867*4882a593Smuzhiyun				nvidia,pins = "ulpi_data4_po5";
868*4882a593Smuzhiyun				nvidia,function = "ulpi";
869*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
870*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
871*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
872*4882a593Smuzhiyun			};
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun			/* MCU_INT1# */
875*4882a593Smuzhiyun			pk2 {
876*4882a593Smuzhiyun				nvidia,pins = "pk2";
877*4882a593Smuzhiyun				nvidia,function = "rsvd1";
878*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
879*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
880*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
881*4882a593Smuzhiyun			};
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun			/* MCU_INT2# */
884*4882a593Smuzhiyun			pj2 {
885*4882a593Smuzhiyun				nvidia,pins = "pj2";
886*4882a593Smuzhiyun				nvidia,function = "rsvd1";
887*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
888*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
889*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
890*4882a593Smuzhiyun			};
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun			/* MCU_INT3# */
893*4882a593Smuzhiyun			pi5 {
894*4882a593Smuzhiyun				nvidia,pins = "pi5";
895*4882a593Smuzhiyun				nvidia,function = "rsvd2";
896*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
897*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
898*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
899*4882a593Smuzhiyun			};
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun			/* MCU_INT4# */
902*4882a593Smuzhiyun			pj0 {
903*4882a593Smuzhiyun				nvidia,pins = "pj0";
904*4882a593Smuzhiyun				nvidia,function = "rsvd1";
905*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
906*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
907*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
908*4882a593Smuzhiyun			};
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun			/* MCU_RESET */
911*4882a593Smuzhiyun			pbb6 {
912*4882a593Smuzhiyun				nvidia,pins = "pbb6";
913*4882a593Smuzhiyun				nvidia,function = "rsvd2";
914*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
915*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
916*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
917*4882a593Smuzhiyun			};
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun			/* MCU SPI */
920*4882a593Smuzhiyun			gpio-x4-aud-px4 {
921*4882a593Smuzhiyun				nvidia,pins = "gpio_x4_aud_px4";
922*4882a593Smuzhiyun				nvidia,function = "spi2";
923*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
924*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
925*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
926*4882a593Smuzhiyun			};
927*4882a593Smuzhiyun			gpio-x5-aud-px5 {
928*4882a593Smuzhiyun				nvidia,pins = "gpio_x5_aud_px5";
929*4882a593Smuzhiyun				nvidia,function = "spi2";
930*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
931*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
932*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
933*4882a593Smuzhiyun			};
934*4882a593Smuzhiyun			gpio-x6-aud-px6 { /* MCU_CS */
935*4882a593Smuzhiyun				nvidia,pins = "gpio_x6_aud_px6";
936*4882a593Smuzhiyun				nvidia,function = "spi2";
937*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
938*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
939*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
940*4882a593Smuzhiyun			};
941*4882a593Smuzhiyun			gpio-x7-aud-px7 {
942*4882a593Smuzhiyun				nvidia,pins = "gpio_x7_aud_px7";
943*4882a593Smuzhiyun				nvidia,function = "spi2";
944*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
945*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
946*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
947*4882a593Smuzhiyun			};
948*4882a593Smuzhiyun			gpio-w2-aud-pw2 { /* MCU_CSEZP */
949*4882a593Smuzhiyun				nvidia,pins = "gpio_w2_aud_pw2";
950*4882a593Smuzhiyun				nvidia,function = "spi2";
951*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
952*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
953*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
954*4882a593Smuzhiyun			};
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun			/* PMIC_CLK_32K */
957*4882a593Smuzhiyun			clk-32k-in {
958*4882a593Smuzhiyun				nvidia,pins = "clk_32k_in";
959*4882a593Smuzhiyun				nvidia,function = "clk";
960*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
961*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
962*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
963*4882a593Smuzhiyun			};
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun			/* PMIC_CPU_OC_INT */
966*4882a593Smuzhiyun			clk-32k-out-pa0 {
967*4882a593Smuzhiyun				nvidia,pins = "clk_32k_out_pa0";
968*4882a593Smuzhiyun				nvidia,function = "soc";
969*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
970*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
971*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
972*4882a593Smuzhiyun			};
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun			/* PWR_I2C */
975*4882a593Smuzhiyun			pwr-i2c-scl-pz6 {
976*4882a593Smuzhiyun				nvidia,pins = "pwr_i2c_scl_pz6";
977*4882a593Smuzhiyun				nvidia,function = "i2cpwr";
978*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
979*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
980*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
981*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
982*4882a593Smuzhiyun			};
983*4882a593Smuzhiyun			pwr-i2c-sda-pz7 {
984*4882a593Smuzhiyun				nvidia,pins = "pwr_i2c_sda_pz7";
985*4882a593Smuzhiyun				nvidia,function = "i2cpwr";
986*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
987*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
988*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
989*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
990*4882a593Smuzhiyun			};
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun			/* PWR_INT_N */
993*4882a593Smuzhiyun			pwr-int-n {
994*4882a593Smuzhiyun				nvidia,pins = "pwr_int_n";
995*4882a593Smuzhiyun				nvidia,function = "pmi";
996*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
997*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
998*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
999*4882a593Smuzhiyun			};
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun			/* RESET_MOCI_CTRL */
1002*4882a593Smuzhiyun			pu4 {
1003*4882a593Smuzhiyun				nvidia,pins = "pu4";
1004*4882a593Smuzhiyun				nvidia,function = "gmi";
1005*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1006*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1007*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1008*4882a593Smuzhiyun			};
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun			/* RESET_OUT_N */
1011*4882a593Smuzhiyun			reset-out-n {
1012*4882a593Smuzhiyun				nvidia,pins = "reset_out_n";
1013*4882a593Smuzhiyun				nvidia,function = "reset_out_n";
1014*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1015*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1016*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1017*4882a593Smuzhiyun			};
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun			/* SHIFT_CTRL_DIR_IN */
1020*4882a593Smuzhiyun			kb-row0-pr0 {
1021*4882a593Smuzhiyun				nvidia,pins = "kb_row0_pr0";
1022*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1023*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1024*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1025*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1026*4882a593Smuzhiyun			};
1027*4882a593Smuzhiyun			kb-row1-pr1 {
1028*4882a593Smuzhiyun				nvidia,pins = "kb_row1_pr1";
1029*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1030*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1031*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1032*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1033*4882a593Smuzhiyun			};
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun			/* Configure level-shifter as output for HDA */
1036*4882a593Smuzhiyun			kb-row11-ps3 {
1037*4882a593Smuzhiyun				nvidia,pins = "kb_row11_ps3";
1038*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1039*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
1040*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1041*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1042*4882a593Smuzhiyun			};
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun			/* SHIFT_CTRL_DIR_OUT */
1045*4882a593Smuzhiyun			kb-col5-pq5 {
1046*4882a593Smuzhiyun				nvidia,pins = "kb_col5_pq5";
1047*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1048*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
1049*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1050*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1051*4882a593Smuzhiyun			};
1052*4882a593Smuzhiyun			kb-col6-pq6 {
1053*4882a593Smuzhiyun				nvidia,pins = "kb_col6_pq6";
1054*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1055*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
1056*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1057*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1058*4882a593Smuzhiyun			};
1059*4882a593Smuzhiyun			kb-col7-pq7 {
1060*4882a593Smuzhiyun				nvidia,pins = "kb_col7_pq7";
1061*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1062*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
1063*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1064*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1065*4882a593Smuzhiyun			};
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun			/* SHIFT_CTRL_OE */
1068*4882a593Smuzhiyun			kb-col0-pq0 {
1069*4882a593Smuzhiyun				nvidia,pins = "kb_col0_pq0";
1070*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1071*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1072*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1073*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1074*4882a593Smuzhiyun			};
1075*4882a593Smuzhiyun			kb-col1-pq1 {
1076*4882a593Smuzhiyun				nvidia,pins = "kb_col1_pq1";
1077*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1078*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1079*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1080*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1081*4882a593Smuzhiyun			};
1082*4882a593Smuzhiyun			kb-col2-pq2 {
1083*4882a593Smuzhiyun				nvidia,pins = "kb_col2_pq2";
1084*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1085*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1086*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1087*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1088*4882a593Smuzhiyun			};
1089*4882a593Smuzhiyun			kb-col4-pq4 {
1090*4882a593Smuzhiyun				nvidia,pins = "kb_col4_pq4";
1091*4882a593Smuzhiyun				nvidia,function = "kbc";
1092*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1093*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1094*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1095*4882a593Smuzhiyun			};
1096*4882a593Smuzhiyun			kb-row2-pr2 {
1097*4882a593Smuzhiyun				nvidia,pins = "kb_row2_pr2";
1098*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1099*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1100*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1101*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1102*4882a593Smuzhiyun			};
1103*4882a593Smuzhiyun
1104*4882a593Smuzhiyun			/* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
1105*4882a593Smuzhiyun			pi6 {
1106*4882a593Smuzhiyun				nvidia,pins = "pi6";
1107*4882a593Smuzhiyun				nvidia,function = "rsvd1";
1108*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
1109*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1110*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1111*4882a593Smuzhiyun			};
1112*4882a593Smuzhiyun
1113*4882a593Smuzhiyun			/* TOUCH_INT */
1114*4882a593Smuzhiyun			gpio-w3-aud-pw3 {
1115*4882a593Smuzhiyun				nvidia,pins = "gpio_w3_aud_pw3";
1116*4882a593Smuzhiyun				nvidia,function = "spi6";
1117*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1118*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1119*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1120*4882a593Smuzhiyun			};
1121*4882a593Smuzhiyun
1122*4882a593Smuzhiyun			pc7 { /* NC */
1123*4882a593Smuzhiyun				nvidia,pins = "pc7";
1124*4882a593Smuzhiyun				nvidia,function = "rsvd1";
1125*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1126*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1127*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1128*4882a593Smuzhiyun			};
1129*4882a593Smuzhiyun			pg0 { /* NC */
1130*4882a593Smuzhiyun				nvidia,pins = "pg0";
1131*4882a593Smuzhiyun				nvidia,function = "rsvd1";
1132*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1133*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1134*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1135*4882a593Smuzhiyun			};
1136*4882a593Smuzhiyun			pg1 { /* NC */
1137*4882a593Smuzhiyun				nvidia,pins = "pg1";
1138*4882a593Smuzhiyun				nvidia,function = "rsvd1";
1139*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1140*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1141*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1142*4882a593Smuzhiyun			};
1143*4882a593Smuzhiyun			pg2 { /* NC */
1144*4882a593Smuzhiyun				nvidia,pins = "pg2";
1145*4882a593Smuzhiyun				nvidia,function = "rsvd1";
1146*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1147*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1148*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1149*4882a593Smuzhiyun			};
1150*4882a593Smuzhiyun			pg3 { /* NC */
1151*4882a593Smuzhiyun				nvidia,pins = "pg3";
1152*4882a593Smuzhiyun				nvidia,function = "rsvd1";
1153*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1154*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1155*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1156*4882a593Smuzhiyun			};
1157*4882a593Smuzhiyun			pg4 { /* NC */
1158*4882a593Smuzhiyun				nvidia,pins = "pg4";
1159*4882a593Smuzhiyun				nvidia,function = "rsvd1";
1160*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1161*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1162*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1163*4882a593Smuzhiyun			};
1164*4882a593Smuzhiyun			ph4 { /* NC */
1165*4882a593Smuzhiyun				nvidia,pins = "ph4";
1166*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1167*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1168*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1169*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1170*4882a593Smuzhiyun			};
1171*4882a593Smuzhiyun			ph5 { /* NC */
1172*4882a593Smuzhiyun				nvidia,pins = "ph5";
1173*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1174*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1175*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1176*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1177*4882a593Smuzhiyun			};
1178*4882a593Smuzhiyun			ph6 { /* NC */
1179*4882a593Smuzhiyun				nvidia,pins = "ph6";
1180*4882a593Smuzhiyun				nvidia,function = "gmi";
1181*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1182*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1183*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1184*4882a593Smuzhiyun			};
1185*4882a593Smuzhiyun			ph7 { /* NC */
1186*4882a593Smuzhiyun				nvidia,pins = "ph7";
1187*4882a593Smuzhiyun				nvidia,function = "gmi";
1188*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1189*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1190*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1191*4882a593Smuzhiyun			};
1192*4882a593Smuzhiyun			pi0 { /* NC */
1193*4882a593Smuzhiyun				nvidia,pins = "pi0";
1194*4882a593Smuzhiyun				nvidia,function = "rsvd1";
1195*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1196*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1197*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1198*4882a593Smuzhiyun			};
1199*4882a593Smuzhiyun			pi1 { /* NC */
1200*4882a593Smuzhiyun				nvidia,pins = "pi1";
1201*4882a593Smuzhiyun				nvidia,function = "rsvd1";
1202*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1203*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1204*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1205*4882a593Smuzhiyun			};
1206*4882a593Smuzhiyun			pi2 { /* NC */
1207*4882a593Smuzhiyun				nvidia,pins = "pi2";
1208*4882a593Smuzhiyun				nvidia,function = "rsvd4";
1209*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1210*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1211*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1212*4882a593Smuzhiyun			};
1213*4882a593Smuzhiyun			pi4 { /* NC */
1214*4882a593Smuzhiyun				nvidia,pins = "pi4";
1215*4882a593Smuzhiyun				nvidia,function = "gmi";
1216*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1217*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1218*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1219*4882a593Smuzhiyun			};
1220*4882a593Smuzhiyun			pi7 { /* NC */
1221*4882a593Smuzhiyun				nvidia,pins = "pi7";
1222*4882a593Smuzhiyun				nvidia,function = "rsvd1";
1223*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1224*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1225*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1226*4882a593Smuzhiyun			};
1227*4882a593Smuzhiyun			pk0 { /* NC */
1228*4882a593Smuzhiyun				nvidia,pins = "pk0";
1229*4882a593Smuzhiyun				nvidia,function = "rsvd1";
1230*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1231*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1232*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1233*4882a593Smuzhiyun			};
1234*4882a593Smuzhiyun			pk1 { /* NC */
1235*4882a593Smuzhiyun				nvidia,pins = "pk1";
1236*4882a593Smuzhiyun				nvidia,function = "rsvd4";
1237*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1238*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1239*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1240*4882a593Smuzhiyun			};
1241*4882a593Smuzhiyun			pk3 { /* NC */
1242*4882a593Smuzhiyun				nvidia,pins = "pk3";
1243*4882a593Smuzhiyun				nvidia,function = "gmi";
1244*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1245*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1246*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1247*4882a593Smuzhiyun			};
1248*4882a593Smuzhiyun			pk4 { /* NC */
1249*4882a593Smuzhiyun				nvidia,pins = "pk4";
1250*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1251*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1252*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1253*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1254*4882a593Smuzhiyun			};
1255*4882a593Smuzhiyun			dap1-fs-pn0 { /* NC */
1256*4882a593Smuzhiyun				nvidia,pins = "dap1_fs_pn0";
1257*4882a593Smuzhiyun				nvidia,function = "rsvd4";
1258*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1259*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1260*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1261*4882a593Smuzhiyun			};
1262*4882a593Smuzhiyun			dap1-din-pn1 { /* NC */
1263*4882a593Smuzhiyun				nvidia,pins = "dap1_din_pn1";
1264*4882a593Smuzhiyun				nvidia,function = "rsvd4";
1265*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1266*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1267*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1268*4882a593Smuzhiyun			};
1269*4882a593Smuzhiyun			dap1-sclk-pn3 { /* NC */
1270*4882a593Smuzhiyun				nvidia,pins = "dap1_sclk_pn3";
1271*4882a593Smuzhiyun				nvidia,function = "rsvd4";
1272*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1273*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1274*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1275*4882a593Smuzhiyun			};
1276*4882a593Smuzhiyun			ulpi-data7-po0 { /* NC */
1277*4882a593Smuzhiyun				nvidia,pins = "ulpi_data7_po0";
1278*4882a593Smuzhiyun				nvidia,function = "ulpi";
1279*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1280*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1281*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1282*4882a593Smuzhiyun			};
1283*4882a593Smuzhiyun			ulpi-data0-po1 { /* NC */
1284*4882a593Smuzhiyun				nvidia,pins = "ulpi_data0_po1";
1285*4882a593Smuzhiyun				nvidia,function = "ulpi";
1286*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1287*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1288*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1289*4882a593Smuzhiyun			};
1290*4882a593Smuzhiyun			ulpi-data1-po2 { /* NC */
1291*4882a593Smuzhiyun				nvidia,pins = "ulpi_data1_po2";
1292*4882a593Smuzhiyun				nvidia,function = "ulpi";
1293*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1294*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1295*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1296*4882a593Smuzhiyun			};
1297*4882a593Smuzhiyun			ulpi-data2-po3 { /* NC */
1298*4882a593Smuzhiyun				nvidia,pins = "ulpi_data2_po3";
1299*4882a593Smuzhiyun				nvidia,function = "ulpi";
1300*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1301*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1302*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1303*4882a593Smuzhiyun			};
1304*4882a593Smuzhiyun			ulpi-data3-po4 { /* NC */
1305*4882a593Smuzhiyun				nvidia,pins = "ulpi_data3_po4";
1306*4882a593Smuzhiyun				nvidia,function = "ulpi";
1307*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1308*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1309*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1310*4882a593Smuzhiyun			};
1311*4882a593Smuzhiyun			ulpi-data6-po7 { /* NC */
1312*4882a593Smuzhiyun				nvidia,pins = "ulpi_data6_po7";
1313*4882a593Smuzhiyun				nvidia,function = "ulpi";
1314*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1315*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1316*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1317*4882a593Smuzhiyun			};
1318*4882a593Smuzhiyun			dap4-fs-pp4 { /* NC */
1319*4882a593Smuzhiyun				nvidia,pins = "dap4_fs_pp4";
1320*4882a593Smuzhiyun				nvidia,function = "rsvd4";
1321*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1322*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1323*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1324*4882a593Smuzhiyun			};
1325*4882a593Smuzhiyun			dap4-din-pp5 { /* NC */
1326*4882a593Smuzhiyun				nvidia,pins = "dap4_din_pp5";
1327*4882a593Smuzhiyun				nvidia,function = "rsvd3";
1328*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1329*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1330*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1331*4882a593Smuzhiyun			};
1332*4882a593Smuzhiyun			dap4-dout-pp6 { /* NC */
1333*4882a593Smuzhiyun				nvidia,pins = "dap4_dout_pp6";
1334*4882a593Smuzhiyun				nvidia,function = "rsvd4";
1335*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1336*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1337*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1338*4882a593Smuzhiyun			};
1339*4882a593Smuzhiyun			dap4-sclk-pp7 { /* NC */
1340*4882a593Smuzhiyun				nvidia,pins = "dap4_sclk_pp7";
1341*4882a593Smuzhiyun				nvidia,function = "rsvd3";
1342*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1343*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1344*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1345*4882a593Smuzhiyun			};
1346*4882a593Smuzhiyun			kb-col3-pq3 { /* NC */
1347*4882a593Smuzhiyun				nvidia,pins = "kb_col3_pq3";
1348*4882a593Smuzhiyun				nvidia,function = "kbc";
1349*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1350*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1351*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1352*4882a593Smuzhiyun			};
1353*4882a593Smuzhiyun			kb-row3-pr3 { /* NC */
1354*4882a593Smuzhiyun				nvidia,pins = "kb_row3_pr3";
1355*4882a593Smuzhiyun				nvidia,function = "kbc";
1356*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1357*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1358*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1359*4882a593Smuzhiyun			};
1360*4882a593Smuzhiyun			kb-row4-pr4 { /* NC */
1361*4882a593Smuzhiyun				nvidia,pins = "kb_row4_pr4";
1362*4882a593Smuzhiyun				nvidia,function = "rsvd3";
1363*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1364*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1365*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1366*4882a593Smuzhiyun			};
1367*4882a593Smuzhiyun			kb-row5-pr5 { /* NC */
1368*4882a593Smuzhiyun				nvidia,pins = "kb_row5_pr5";
1369*4882a593Smuzhiyun				nvidia,function = "rsvd3";
1370*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1371*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1372*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1373*4882a593Smuzhiyun			};
1374*4882a593Smuzhiyun			kb-row6-pr6 { /* NC */
1375*4882a593Smuzhiyun				nvidia,pins = "kb_row6_pr6";
1376*4882a593Smuzhiyun				nvidia,function = "kbc";
1377*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1378*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1379*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1380*4882a593Smuzhiyun			};
1381*4882a593Smuzhiyun			kb-row7-pr7 { /* NC */
1382*4882a593Smuzhiyun				nvidia,pins = "kb_row7_pr7";
1383*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1384*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1385*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1386*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1387*4882a593Smuzhiyun			};
1388*4882a593Smuzhiyun			kb-row8-ps0 { /* NC */
1389*4882a593Smuzhiyun				nvidia,pins = "kb_row8_ps0";
1390*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1391*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1392*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1393*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1394*4882a593Smuzhiyun			};
1395*4882a593Smuzhiyun			kb-row9-ps1 { /* NC */
1396*4882a593Smuzhiyun				nvidia,pins = "kb_row9_ps1";
1397*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1398*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1399*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1400*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1401*4882a593Smuzhiyun			};
1402*4882a593Smuzhiyun			kb-row12-ps4 { /* NC */
1403*4882a593Smuzhiyun				nvidia,pins = "kb_row12_ps4";
1404*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1405*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1406*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1407*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1408*4882a593Smuzhiyun			};
1409*4882a593Smuzhiyun			kb-row13-ps5 { /* NC */
1410*4882a593Smuzhiyun				nvidia,pins = "kb_row13_ps5";
1411*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1412*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1413*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1414*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1415*4882a593Smuzhiyun			};
1416*4882a593Smuzhiyun			kb-row14-ps6 { /* NC */
1417*4882a593Smuzhiyun				nvidia,pins = "kb_row14_ps6";
1418*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1419*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1420*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1421*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1422*4882a593Smuzhiyun			};
1423*4882a593Smuzhiyun			kb-row15-ps7 { /* NC */
1424*4882a593Smuzhiyun				nvidia,pins = "kb_row15_ps7";
1425*4882a593Smuzhiyun				nvidia,function = "rsvd3";
1426*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1427*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1428*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1429*4882a593Smuzhiyun			};
1430*4882a593Smuzhiyun			kb-row16-pt0 { /* NC */
1431*4882a593Smuzhiyun				nvidia,pins = "kb_row16_pt0";
1432*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1433*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1434*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1435*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1436*4882a593Smuzhiyun			};
1437*4882a593Smuzhiyun			kb-row17-pt1 { /* NC */
1438*4882a593Smuzhiyun				nvidia,pins = "kb_row17_pt1";
1439*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1440*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1441*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1442*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1443*4882a593Smuzhiyun			};
1444*4882a593Smuzhiyun			pu5 { /* NC */
1445*4882a593Smuzhiyun				nvidia,pins = "pu5";
1446*4882a593Smuzhiyun				nvidia,function = "gmi";
1447*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1448*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1449*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1450*4882a593Smuzhiyun			};
1451*4882a593Smuzhiyun			pv0 { /* NC */
1452*4882a593Smuzhiyun				nvidia,pins = "pv0";
1453*4882a593Smuzhiyun				nvidia,function = "rsvd1";
1454*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1455*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1456*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1457*4882a593Smuzhiyun			};
1458*4882a593Smuzhiyun			pv1 { /* NC */
1459*4882a593Smuzhiyun				nvidia,pins = "pv1";
1460*4882a593Smuzhiyun				nvidia,function = "rsvd1";
1461*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1462*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1463*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1464*4882a593Smuzhiyun			};
1465*4882a593Smuzhiyun			gpio-x1-aud-px1 { /* NC */
1466*4882a593Smuzhiyun				nvidia,pins = "gpio_x1_aud_px1";
1467*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1468*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1469*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1470*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1471*4882a593Smuzhiyun			};
1472*4882a593Smuzhiyun			gpio-x3-aud-px3 { /* NC */
1473*4882a593Smuzhiyun				nvidia,pins = "gpio_x3_aud_px3";
1474*4882a593Smuzhiyun				nvidia,function = "rsvd4";
1475*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1476*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1477*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1478*4882a593Smuzhiyun			};
1479*4882a593Smuzhiyun			pbb7 { /* NC */
1480*4882a593Smuzhiyun				nvidia,pins = "pbb7";
1481*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1482*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1483*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1484*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1485*4882a593Smuzhiyun			};
1486*4882a593Smuzhiyun			pcc1 { /* NC */
1487*4882a593Smuzhiyun				nvidia,pins = "pcc1";
1488*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1489*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1490*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1491*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1492*4882a593Smuzhiyun			};
1493*4882a593Smuzhiyun			pcc2 { /* NC */
1494*4882a593Smuzhiyun				nvidia,pins = "pcc2";
1495*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1496*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1497*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1498*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1499*4882a593Smuzhiyun			};
1500*4882a593Smuzhiyun			clk3-req-pee1 { /* NC */
1501*4882a593Smuzhiyun				nvidia,pins = "clk3_req_pee1";
1502*4882a593Smuzhiyun				nvidia,function = "rsvd2";
1503*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1504*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1505*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1506*4882a593Smuzhiyun			};
1507*4882a593Smuzhiyun			dap-mclk1-req-pee2 { /* NC */
1508*4882a593Smuzhiyun				nvidia,pins = "dap_mclk1_req_pee2";
1509*4882a593Smuzhiyun				nvidia,function = "rsvd4";
1510*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1511*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1512*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1513*4882a593Smuzhiyun			};
1514*4882a593Smuzhiyun			/*
1515*4882a593Smuzhiyun			 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
1516*4882a593Smuzhiyun			 * driver enabled aka not tristated and input driver
1517*4882a593Smuzhiyun			 * enabled as well as it features some magic properties
1518*4882a593Smuzhiyun			 * even though the external loopback is disabled and the
1519*4882a593Smuzhiyun			 * internal loopback used as per
1520*4882a593Smuzhiyun			 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
1521*4882a593Smuzhiyun			 * bits being set to 0xfffd according to the TRM!
1522*4882a593Smuzhiyun			 */
1523*4882a593Smuzhiyun			sdmmc3-clk-lb-out-pee4 { /* NC */
1524*4882a593Smuzhiyun				nvidia,pins = "sdmmc3_clk_lb_out_pee4";
1525*4882a593Smuzhiyun				nvidia,function = "sdmmc3";
1526*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1527*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1528*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1529*4882a593Smuzhiyun			};
1530*4882a593Smuzhiyun		};
1531*4882a593Smuzhiyun	};
1532*4882a593Smuzhiyun
1533*4882a593Smuzhiyun	serial@70006040 {
1534*4882a593Smuzhiyun		compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
1535*4882a593Smuzhiyun	};
1536*4882a593Smuzhiyun
1537*4882a593Smuzhiyun	serial@70006200 {
1538*4882a593Smuzhiyun		compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
1539*4882a593Smuzhiyun	};
1540*4882a593Smuzhiyun
1541*4882a593Smuzhiyun	serial@70006300 {
1542*4882a593Smuzhiyun		compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
1543*4882a593Smuzhiyun	};
1544*4882a593Smuzhiyun
1545*4882a593Smuzhiyun	hdmi_ddc: i2c@7000c400 {
1546*4882a593Smuzhiyun		clock-frequency = <10000>;
1547*4882a593Smuzhiyun	};
1548*4882a593Smuzhiyun
1549*4882a593Smuzhiyun	/* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
1550*4882a593Smuzhiyun	i2c@7000d000 {
1551*4882a593Smuzhiyun		status = "okay";
1552*4882a593Smuzhiyun		clock-frequency = <400000>;
1553*4882a593Smuzhiyun
1554*4882a593Smuzhiyun		/* SGTL5000 audio codec */
1555*4882a593Smuzhiyun		sgtl5000: codec@a {
1556*4882a593Smuzhiyun			compatible = "fsl,sgtl5000";
1557*4882a593Smuzhiyun			reg = <0x0a>;
1558*4882a593Smuzhiyun			#sound-dai-cells = <0>;
1559*4882a593Smuzhiyun			VDDA-supply = <&reg_module_3v3_audio>;
1560*4882a593Smuzhiyun			VDDD-supply = <&reg_1v8_vddio>;
1561*4882a593Smuzhiyun			VDDIO-supply = <&reg_1v8_vddio>;
1562*4882a593Smuzhiyun			clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
1563*4882a593Smuzhiyun		};
1564*4882a593Smuzhiyun
1565*4882a593Smuzhiyun		pmic: pmic@40 {
1566*4882a593Smuzhiyun			compatible = "ams,as3722";
1567*4882a593Smuzhiyun			reg = <0x40>;
1568*4882a593Smuzhiyun			interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
1569*4882a593Smuzhiyun			ams,system-power-controller;
1570*4882a593Smuzhiyun			#interrupt-cells = <2>;
1571*4882a593Smuzhiyun			interrupt-controller;
1572*4882a593Smuzhiyun			gpio-controller;
1573*4882a593Smuzhiyun			#gpio-cells = <2>;
1574*4882a593Smuzhiyun			pinctrl-names = "default";
1575*4882a593Smuzhiyun			pinctrl-0 = <&as3722_default>;
1576*4882a593Smuzhiyun
1577*4882a593Smuzhiyun			as3722_default: pinmux {
1578*4882a593Smuzhiyun				gpio2-7 {
1579*4882a593Smuzhiyun					pins = "gpio2", /* PWR_EN_+V3.3 */
1580*4882a593Smuzhiyun					       "gpio7"; /* +V1.6_LPO */
1581*4882a593Smuzhiyun					function = "gpio";
1582*4882a593Smuzhiyun					bias-pull-up;
1583*4882a593Smuzhiyun				};
1584*4882a593Smuzhiyun
1585*4882a593Smuzhiyun				gpio0-1-3-4-5-6 {
1586*4882a593Smuzhiyun					pins = "gpio0", "gpio1", "gpio3",
1587*4882a593Smuzhiyun					       "gpio4", "gpio5", "gpio6";
1588*4882a593Smuzhiyun					bias-high-impedance;
1589*4882a593Smuzhiyun				};
1590*4882a593Smuzhiyun			};
1591*4882a593Smuzhiyun
1592*4882a593Smuzhiyun			regulators {
1593*4882a593Smuzhiyun				vsup-sd2-supply = <&reg_module_3v3>;
1594*4882a593Smuzhiyun				vsup-sd3-supply = <&reg_module_3v3>;
1595*4882a593Smuzhiyun				vsup-sd4-supply = <&reg_module_3v3>;
1596*4882a593Smuzhiyun				vsup-sd5-supply = <&reg_module_3v3>;
1597*4882a593Smuzhiyun				vin-ldo0-supply = <&reg_1v35_vddio_ddr>;
1598*4882a593Smuzhiyun				vin-ldo1-6-supply = <&reg_module_3v3>;
1599*4882a593Smuzhiyun				vin-ldo2-5-7-supply = <&reg_1v8_vddio>;
1600*4882a593Smuzhiyun				vin-ldo3-4-supply = <&reg_module_3v3>;
1601*4882a593Smuzhiyun				vin-ldo9-10-supply = <&reg_module_3v3>;
1602*4882a593Smuzhiyun				vin-ldo11-supply = <&reg_module_3v3>;
1603*4882a593Smuzhiyun
1604*4882a593Smuzhiyun				reg_vdd_cpu: sd0 {
1605*4882a593Smuzhiyun					regulator-name = "+VDD_CPU_AP";
1606*4882a593Smuzhiyun					regulator-min-microvolt = <700000>;
1607*4882a593Smuzhiyun					regulator-max-microvolt = <1400000>;
1608*4882a593Smuzhiyun					regulator-min-microamp = <3500000>;
1609*4882a593Smuzhiyun					regulator-max-microamp = <3500000>;
1610*4882a593Smuzhiyun					regulator-always-on;
1611*4882a593Smuzhiyun					regulator-boot-on;
1612*4882a593Smuzhiyun					ams,ext-control = <2>;
1613*4882a593Smuzhiyun				};
1614*4882a593Smuzhiyun
1615*4882a593Smuzhiyun				sd1 {
1616*4882a593Smuzhiyun					regulator-name = "+VDD_CORE";
1617*4882a593Smuzhiyun					regulator-min-microvolt = <700000>;
1618*4882a593Smuzhiyun					regulator-max-microvolt = <1350000>;
1619*4882a593Smuzhiyun					regulator-min-microamp = <2500000>;
1620*4882a593Smuzhiyun					regulator-max-microamp = <4000000>;
1621*4882a593Smuzhiyun					regulator-always-on;
1622*4882a593Smuzhiyun					regulator-boot-on;
1623*4882a593Smuzhiyun					ams,ext-control = <1>;
1624*4882a593Smuzhiyun				};
1625*4882a593Smuzhiyun
1626*4882a593Smuzhiyun				reg_1v35_vddio_ddr: sd2 {
1627*4882a593Smuzhiyun					regulator-name =
1628*4882a593Smuzhiyun						"+V1.35_VDDIO_DDR(sd2)";
1629*4882a593Smuzhiyun					regulator-min-microvolt = <1350000>;
1630*4882a593Smuzhiyun					regulator-max-microvolt = <1350000>;
1631*4882a593Smuzhiyun					regulator-always-on;
1632*4882a593Smuzhiyun					regulator-boot-on;
1633*4882a593Smuzhiyun				};
1634*4882a593Smuzhiyun
1635*4882a593Smuzhiyun				sd3 {
1636*4882a593Smuzhiyun					regulator-name =
1637*4882a593Smuzhiyun						"+V1.35_VDDIO_DDR(sd3)";
1638*4882a593Smuzhiyun					regulator-min-microvolt = <1350000>;
1639*4882a593Smuzhiyun					regulator-max-microvolt = <1350000>;
1640*4882a593Smuzhiyun					regulator-always-on;
1641*4882a593Smuzhiyun					regulator-boot-on;
1642*4882a593Smuzhiyun				};
1643*4882a593Smuzhiyun
1644*4882a593Smuzhiyun				reg_1v05_vdd: sd4 {
1645*4882a593Smuzhiyun					regulator-name = "+V1.05";
1646*4882a593Smuzhiyun					regulator-min-microvolt = <1050000>;
1647*4882a593Smuzhiyun					regulator-max-microvolt = <1050000>;
1648*4882a593Smuzhiyun				};
1649*4882a593Smuzhiyun
1650*4882a593Smuzhiyun				reg_1v8_vddio: sd5 {
1651*4882a593Smuzhiyun					regulator-name = "+V1.8";
1652*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
1653*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
1654*4882a593Smuzhiyun					regulator-boot-on;
1655*4882a593Smuzhiyun					regulator-always-on;
1656*4882a593Smuzhiyun				};
1657*4882a593Smuzhiyun
1658*4882a593Smuzhiyun				reg_vdd_gpu: sd6 {
1659*4882a593Smuzhiyun					regulator-name = "+VDD_GPU_AP";
1660*4882a593Smuzhiyun					regulator-min-microvolt = <650000>;
1661*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
1662*4882a593Smuzhiyun					regulator-min-microamp = <3500000>;
1663*4882a593Smuzhiyun					regulator-max-microamp = <3500000>;
1664*4882a593Smuzhiyun					regulator-boot-on;
1665*4882a593Smuzhiyun					regulator-always-on;
1666*4882a593Smuzhiyun				};
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun				reg_1v05_avdd: ldo0 {
1669*4882a593Smuzhiyun					regulator-name = "+V1.05_AVDD";
1670*4882a593Smuzhiyun					regulator-min-microvolt = <1050000>;
1671*4882a593Smuzhiyun					regulator-max-microvolt = <1050000>;
1672*4882a593Smuzhiyun					regulator-boot-on;
1673*4882a593Smuzhiyun					regulator-always-on;
1674*4882a593Smuzhiyun					ams,ext-control = <1>;
1675*4882a593Smuzhiyun				};
1676*4882a593Smuzhiyun
1677*4882a593Smuzhiyun				vddio_sdmmc1: ldo1 {
1678*4882a593Smuzhiyun					regulator-name = "VDDIO_SDMMC1";
1679*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
1680*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
1681*4882a593Smuzhiyun				};
1682*4882a593Smuzhiyun
1683*4882a593Smuzhiyun				ldo2 {
1684*4882a593Smuzhiyun					regulator-name = "+V1.2";
1685*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
1686*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
1687*4882a593Smuzhiyun					regulator-boot-on;
1688*4882a593Smuzhiyun					regulator-always-on;
1689*4882a593Smuzhiyun				};
1690*4882a593Smuzhiyun
1691*4882a593Smuzhiyun				ldo3 {
1692*4882a593Smuzhiyun					regulator-name = "+V1.05_RTC";
1693*4882a593Smuzhiyun					regulator-min-microvolt = <1000000>;
1694*4882a593Smuzhiyun					regulator-max-microvolt = <1000000>;
1695*4882a593Smuzhiyun					regulator-boot-on;
1696*4882a593Smuzhiyun					regulator-always-on;
1697*4882a593Smuzhiyun					ams,enable-tracking;
1698*4882a593Smuzhiyun				};
1699*4882a593Smuzhiyun
1700*4882a593Smuzhiyun				/* 1.8V for LVDS, 3.3V for eDP */
1701*4882a593Smuzhiyun				ldo4 {
1702*4882a593Smuzhiyun					regulator-name = "AVDD_LVDS0_PLL";
1703*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
1704*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
1705*4882a593Smuzhiyun				};
1706*4882a593Smuzhiyun
1707*4882a593Smuzhiyun				/* LDO5 not used */
1708*4882a593Smuzhiyun
1709*4882a593Smuzhiyun				vddio_sdmmc3: ldo6 {
1710*4882a593Smuzhiyun					regulator-name = "VDDIO_SDMMC3";
1711*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
1712*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
1713*4882a593Smuzhiyun				};
1714*4882a593Smuzhiyun
1715*4882a593Smuzhiyun				/* LDO7 not used */
1716*4882a593Smuzhiyun
1717*4882a593Smuzhiyun				ldo9 {
1718*4882a593Smuzhiyun					regulator-name = "+V3.3_ETH(ldo9)";
1719*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
1720*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
1721*4882a593Smuzhiyun					regulator-always-on;
1722*4882a593Smuzhiyun				};
1723*4882a593Smuzhiyun
1724*4882a593Smuzhiyun				ldo10 {
1725*4882a593Smuzhiyun					regulator-name = "+V3.3_ETH(ldo10)";
1726*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
1727*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
1728*4882a593Smuzhiyun					regulator-always-on;
1729*4882a593Smuzhiyun				};
1730*4882a593Smuzhiyun
1731*4882a593Smuzhiyun				ldo11 {
1732*4882a593Smuzhiyun					regulator-name = "+V1.8_VPP_FUSE";
1733*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
1734*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
1735*4882a593Smuzhiyun				};
1736*4882a593Smuzhiyun			};
1737*4882a593Smuzhiyun		};
1738*4882a593Smuzhiyun
1739*4882a593Smuzhiyun		/*
1740*4882a593Smuzhiyun		 * TMP451 temperature sensor
1741*4882a593Smuzhiyun		 * Note: THERM_N directly connected to AS3722 PMIC THERM
1742*4882a593Smuzhiyun		 */
1743*4882a593Smuzhiyun		temp-sensor@4c {
1744*4882a593Smuzhiyun			compatible = "ti,tmp451";
1745*4882a593Smuzhiyun			reg = <0x4c>;
1746*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
1747*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
1748*4882a593Smuzhiyun			#thermal-sensor-cells = <1>;
1749*4882a593Smuzhiyun			vcc-supply = <&reg_module_3v3>;
1750*4882a593Smuzhiyun		};
1751*4882a593Smuzhiyun	};
1752*4882a593Smuzhiyun
1753*4882a593Smuzhiyun	/* SPI2: MCU SPI */
1754*4882a593Smuzhiyun	spi@7000d600 {
1755*4882a593Smuzhiyun		status = "okay";
1756*4882a593Smuzhiyun		spi-max-frequency = <25000000>;
1757*4882a593Smuzhiyun	};
1758*4882a593Smuzhiyun
1759*4882a593Smuzhiyun	pmc@7000e400 {
1760*4882a593Smuzhiyun		nvidia,invert-interrupt;
1761*4882a593Smuzhiyun		nvidia,suspend-mode = <1>;
1762*4882a593Smuzhiyun		nvidia,cpu-pwr-good-time = <500>;
1763*4882a593Smuzhiyun		nvidia,cpu-pwr-off-time = <300>;
1764*4882a593Smuzhiyun		nvidia,core-pwr-good-time = <641 3845>;
1765*4882a593Smuzhiyun		nvidia,core-pwr-off-time = <61036>;
1766*4882a593Smuzhiyun		nvidia,core-power-req-active-high;
1767*4882a593Smuzhiyun		nvidia,sys-clock-req-active-high;
1768*4882a593Smuzhiyun
1769*4882a593Smuzhiyun		/* Set power_off bit in ResetControl register of AS3722 PMIC */
1770*4882a593Smuzhiyun		i2c-thermtrip {
1771*4882a593Smuzhiyun			nvidia,i2c-controller-id = <4>;
1772*4882a593Smuzhiyun			nvidia,bus-addr = <0x40>;
1773*4882a593Smuzhiyun			nvidia,reg-addr = <0x36>;
1774*4882a593Smuzhiyun			nvidia,reg-data = <0x2>;
1775*4882a593Smuzhiyun		};
1776*4882a593Smuzhiyun	};
1777*4882a593Smuzhiyun
1778*4882a593Smuzhiyun	sata@70020000 {
1779*4882a593Smuzhiyun		phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
1780*4882a593Smuzhiyun		phy-names = "sata-0";
1781*4882a593Smuzhiyun		avdd-supply = <&reg_1v05_vdd>;
1782*4882a593Smuzhiyun		hvdd-supply = <&reg_module_3v3>;
1783*4882a593Smuzhiyun		vddio-supply = <&reg_1v05_vdd>;
1784*4882a593Smuzhiyun	};
1785*4882a593Smuzhiyun
1786*4882a593Smuzhiyun	usb@70090000 {
1787*4882a593Smuzhiyun		/* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
1788*4882a593Smuzhiyun		phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
1789*4882a593Smuzhiyun		       <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
1790*4882a593Smuzhiyun		       <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
1791*4882a593Smuzhiyun		       <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
1792*4882a593Smuzhiyun		       <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
1793*4882a593Smuzhiyun		phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
1794*4882a593Smuzhiyun		avddio-pex-supply = <&reg_1v05_vdd>;
1795*4882a593Smuzhiyun		avdd-pll-erefe-supply = <&reg_1v05_avdd>;
1796*4882a593Smuzhiyun		avdd-pll-utmip-supply = <&reg_1v8_vddio>;
1797*4882a593Smuzhiyun		avdd-usb-ss-pll-supply = <&reg_1v05_vdd>;
1798*4882a593Smuzhiyun		avdd-usb-supply = <&reg_module_3v3>;
1799*4882a593Smuzhiyun		dvddio-pex-supply = <&reg_1v05_vdd>;
1800*4882a593Smuzhiyun		hvdd-usb-ss-pll-e-supply = <&reg_module_3v3>;
1801*4882a593Smuzhiyun		hvdd-usb-ss-supply = <&reg_module_3v3>;
1802*4882a593Smuzhiyun	};
1803*4882a593Smuzhiyun
1804*4882a593Smuzhiyun	padctl@7009f000 {
1805*4882a593Smuzhiyun		avdd-pll-utmip-supply = <&reg_1v8_vddio>;
1806*4882a593Smuzhiyun		avdd-pll-erefe-supply = <&reg_1v05_avdd>;
1807*4882a593Smuzhiyun		avdd-pex-pll-supply = <&reg_1v05_vdd>;
1808*4882a593Smuzhiyun		hvdd-pex-pll-e-supply = <&reg_module_3v3>;
1809*4882a593Smuzhiyun
1810*4882a593Smuzhiyun		pads {
1811*4882a593Smuzhiyun			usb2 {
1812*4882a593Smuzhiyun				status = "okay";
1813*4882a593Smuzhiyun
1814*4882a593Smuzhiyun				lanes {
1815*4882a593Smuzhiyun					usb2-0 {
1816*4882a593Smuzhiyun						status = "okay";
1817*4882a593Smuzhiyun						nvidia,function = "xusb";
1818*4882a593Smuzhiyun					};
1819*4882a593Smuzhiyun
1820*4882a593Smuzhiyun					usb2-1 {
1821*4882a593Smuzhiyun						status = "okay";
1822*4882a593Smuzhiyun						nvidia,function = "xusb";
1823*4882a593Smuzhiyun					};
1824*4882a593Smuzhiyun
1825*4882a593Smuzhiyun					usb2-2 {
1826*4882a593Smuzhiyun						status = "okay";
1827*4882a593Smuzhiyun						nvidia,function = "xusb";
1828*4882a593Smuzhiyun					};
1829*4882a593Smuzhiyun				};
1830*4882a593Smuzhiyun			};
1831*4882a593Smuzhiyun
1832*4882a593Smuzhiyun			pcie {
1833*4882a593Smuzhiyun				status = "okay";
1834*4882a593Smuzhiyun
1835*4882a593Smuzhiyun				lanes {
1836*4882a593Smuzhiyun					pcie-0 {
1837*4882a593Smuzhiyun						status = "okay";
1838*4882a593Smuzhiyun						nvidia,function = "usb3-ss";
1839*4882a593Smuzhiyun					};
1840*4882a593Smuzhiyun
1841*4882a593Smuzhiyun					pcie-1 {
1842*4882a593Smuzhiyun						status = "okay";
1843*4882a593Smuzhiyun						nvidia,function = "usb3-ss";
1844*4882a593Smuzhiyun					};
1845*4882a593Smuzhiyun
1846*4882a593Smuzhiyun					pcie-2 {
1847*4882a593Smuzhiyun						status = "okay";
1848*4882a593Smuzhiyun						nvidia,function = "pcie";
1849*4882a593Smuzhiyun					};
1850*4882a593Smuzhiyun
1851*4882a593Smuzhiyun					pcie-3 {
1852*4882a593Smuzhiyun						status = "okay";
1853*4882a593Smuzhiyun						nvidia,function = "pcie";
1854*4882a593Smuzhiyun					};
1855*4882a593Smuzhiyun
1856*4882a593Smuzhiyun					pcie-4 {
1857*4882a593Smuzhiyun						status = "okay";
1858*4882a593Smuzhiyun						nvidia,function = "pcie";
1859*4882a593Smuzhiyun					};
1860*4882a593Smuzhiyun				};
1861*4882a593Smuzhiyun			};
1862*4882a593Smuzhiyun
1863*4882a593Smuzhiyun			sata {
1864*4882a593Smuzhiyun				status = "okay";
1865*4882a593Smuzhiyun
1866*4882a593Smuzhiyun				lanes {
1867*4882a593Smuzhiyun					sata-0 {
1868*4882a593Smuzhiyun						status = "okay";
1869*4882a593Smuzhiyun						nvidia,function = "sata";
1870*4882a593Smuzhiyun					};
1871*4882a593Smuzhiyun				};
1872*4882a593Smuzhiyun			};
1873*4882a593Smuzhiyun		};
1874*4882a593Smuzhiyun
1875*4882a593Smuzhiyun		ports {
1876*4882a593Smuzhiyun			/* USBO1 */
1877*4882a593Smuzhiyun			usb2-0 {
1878*4882a593Smuzhiyun				status = "okay";
1879*4882a593Smuzhiyun				mode = "otg";
1880*4882a593Smuzhiyun				vbus-supply = <&reg_usbo1_vbus>;
1881*4882a593Smuzhiyun			};
1882*4882a593Smuzhiyun
1883*4882a593Smuzhiyun			/* USBH2 */
1884*4882a593Smuzhiyun			usb2-1 {
1885*4882a593Smuzhiyun				status = "okay";
1886*4882a593Smuzhiyun				mode = "host";
1887*4882a593Smuzhiyun				vbus-supply = <&reg_usbh_vbus>;
1888*4882a593Smuzhiyun			};
1889*4882a593Smuzhiyun
1890*4882a593Smuzhiyun			/* USBH4 */
1891*4882a593Smuzhiyun			usb2-2 {
1892*4882a593Smuzhiyun				status = "okay";
1893*4882a593Smuzhiyun				mode = "host";
1894*4882a593Smuzhiyun				vbus-supply = <&reg_usbh_vbus>;
1895*4882a593Smuzhiyun			};
1896*4882a593Smuzhiyun
1897*4882a593Smuzhiyun			usb3-0 {
1898*4882a593Smuzhiyun				status = "okay";
1899*4882a593Smuzhiyun				nvidia,usb2-companion = <2>;
1900*4882a593Smuzhiyun				vbus-supply = <&reg_usbh_vbus>;
1901*4882a593Smuzhiyun			};
1902*4882a593Smuzhiyun
1903*4882a593Smuzhiyun			usb3-1 {
1904*4882a593Smuzhiyun				status = "okay";
1905*4882a593Smuzhiyun				nvidia,usb2-companion = <0>;
1906*4882a593Smuzhiyun				vbus-supply = <&reg_usbo1_vbus>;
1907*4882a593Smuzhiyun			};
1908*4882a593Smuzhiyun		};
1909*4882a593Smuzhiyun	};
1910*4882a593Smuzhiyun
1911*4882a593Smuzhiyun	/* eMMC */
1912*4882a593Smuzhiyun	mmc@700b0600 {
1913*4882a593Smuzhiyun		status = "okay";
1914*4882a593Smuzhiyun		bus-width = <8>;
1915*4882a593Smuzhiyun		non-removable;
1916*4882a593Smuzhiyun		vmmc-supply = <&reg_module_3v3>; /* VCC */
1917*4882a593Smuzhiyun		vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */
1918*4882a593Smuzhiyun		mmc-ddr-1_8v;
1919*4882a593Smuzhiyun	};
1920*4882a593Smuzhiyun
1921*4882a593Smuzhiyun	/* CPU DFLL clock */
1922*4882a593Smuzhiyun	clock@70110000 {
1923*4882a593Smuzhiyun		status = "okay";
1924*4882a593Smuzhiyun		nvidia,i2c-fs-rate = <400000>;
1925*4882a593Smuzhiyun		vdd-cpu-supply = <&reg_vdd_cpu>;
1926*4882a593Smuzhiyun	};
1927*4882a593Smuzhiyun
1928*4882a593Smuzhiyun	ahub@70300000 {
1929*4882a593Smuzhiyun		i2s@70301200 {
1930*4882a593Smuzhiyun			status = "okay";
1931*4882a593Smuzhiyun		};
1932*4882a593Smuzhiyun	};
1933*4882a593Smuzhiyun
1934*4882a593Smuzhiyun	clk32k_in: osc3 {
1935*4882a593Smuzhiyun		compatible = "fixed-clock";
1936*4882a593Smuzhiyun		#clock-cells = <0>;
1937*4882a593Smuzhiyun		clock-frequency = <32768>;
1938*4882a593Smuzhiyun	};
1939*4882a593Smuzhiyun
1940*4882a593Smuzhiyun	cpus {
1941*4882a593Smuzhiyun		cpu@0 {
1942*4882a593Smuzhiyun			vdd-cpu-supply = <&reg_vdd_cpu>;
1943*4882a593Smuzhiyun		};
1944*4882a593Smuzhiyun	};
1945*4882a593Smuzhiyun
1946*4882a593Smuzhiyun	reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
1947*4882a593Smuzhiyun		compatible = "regulator-fixed";
1948*4882a593Smuzhiyun		regulator-name = "+V1.05_AVDD_HDMI_PLL";
1949*4882a593Smuzhiyun		regulator-min-microvolt = <1050000>;
1950*4882a593Smuzhiyun		regulator-max-microvolt = <1050000>;
1951*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1952*4882a593Smuzhiyun		vin-supply = <&reg_1v05_vdd>;
1953*4882a593Smuzhiyun	};
1954*4882a593Smuzhiyun
1955*4882a593Smuzhiyun	reg_3v3_mxm: regulator-3v3-mxm {
1956*4882a593Smuzhiyun		compatible = "regulator-fixed";
1957*4882a593Smuzhiyun		regulator-name = "+V3.3_MXM";
1958*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
1959*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
1960*4882a593Smuzhiyun		regulator-always-on;
1961*4882a593Smuzhiyun		regulator-boot-on;
1962*4882a593Smuzhiyun	};
1963*4882a593Smuzhiyun
1964*4882a593Smuzhiyun	reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1965*4882a593Smuzhiyun		compatible = "regulator-fixed";
1966*4882a593Smuzhiyun		regulator-name = "+V3.3_AVDD_HDMI";
1967*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
1968*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
1969*4882a593Smuzhiyun		vin-supply = <&reg_1v05_vdd>;
1970*4882a593Smuzhiyun	};
1971*4882a593Smuzhiyun
1972*4882a593Smuzhiyun	reg_module_3v3: regulator-module-3v3 {
1973*4882a593Smuzhiyun		compatible = "regulator-fixed";
1974*4882a593Smuzhiyun		regulator-name = "+V3.3";
1975*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
1976*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
1977*4882a593Smuzhiyun		regulator-always-on;
1978*4882a593Smuzhiyun		regulator-boot-on;
1979*4882a593Smuzhiyun		/* PWR_EN_+V3.3 */
1980*4882a593Smuzhiyun		gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
1981*4882a593Smuzhiyun		enable-active-high;
1982*4882a593Smuzhiyun		vin-supply = <&reg_3v3_mxm>;
1983*4882a593Smuzhiyun	};
1984*4882a593Smuzhiyun
1985*4882a593Smuzhiyun	reg_module_3v3_audio: regulator-module-3v3-audio {
1986*4882a593Smuzhiyun		compatible = "regulator-fixed";
1987*4882a593Smuzhiyun		regulator-name = "+V3.3_AUDIO_AVDD_S";
1988*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
1989*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
1990*4882a593Smuzhiyun		regulator-always-on;
1991*4882a593Smuzhiyun	};
1992*4882a593Smuzhiyun
1993*4882a593Smuzhiyun	sound {
1994*4882a593Smuzhiyun		compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
1995*4882a593Smuzhiyun			     "nvidia,tegra-audio-sgtl5000";
1996*4882a593Smuzhiyun		nvidia,model = "Toradex Apalis TK1";
1997*4882a593Smuzhiyun		nvidia,audio-routing =
1998*4882a593Smuzhiyun			"Headphone Jack", "HP_OUT",
1999*4882a593Smuzhiyun			"LINE_IN", "Line In Jack",
2000*4882a593Smuzhiyun			"MIC_IN", "Mic Jack";
2001*4882a593Smuzhiyun		nvidia,i2s-controller = <&tegra_i2s2>;
2002*4882a593Smuzhiyun		nvidia,audio-codec = <&sgtl5000>;
2003*4882a593Smuzhiyun		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
2004*4882a593Smuzhiyun			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
2005*4882a593Smuzhiyun			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
2006*4882a593Smuzhiyun		clock-names = "pll_a", "pll_a_out0", "mclk";
2007*4882a593Smuzhiyun
2008*4882a593Smuzhiyun		assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
2009*4882a593Smuzhiyun				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
2010*4882a593Smuzhiyun
2011*4882a593Smuzhiyun		assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
2012*4882a593Smuzhiyun					 <&tegra_car TEGRA124_CLK_EXTERN1>;
2013*4882a593Smuzhiyun	};
2014*4882a593Smuzhiyun
2015*4882a593Smuzhiyun	thermal-zones {
2016*4882a593Smuzhiyun		cpu {
2017*4882a593Smuzhiyun			trips {
2018*4882a593Smuzhiyun				cpu-shutdown-trip {
2019*4882a593Smuzhiyun					temperature = <101000>;
2020*4882a593Smuzhiyun					hysteresis = <0>;
2021*4882a593Smuzhiyun					type = "critical";
2022*4882a593Smuzhiyun				};
2023*4882a593Smuzhiyun			};
2024*4882a593Smuzhiyun		};
2025*4882a593Smuzhiyun
2026*4882a593Smuzhiyun		mem {
2027*4882a593Smuzhiyun			trips {
2028*4882a593Smuzhiyun				mem-shutdown-trip {
2029*4882a593Smuzhiyun					temperature = <101000>;
2030*4882a593Smuzhiyun					hysteresis = <0>;
2031*4882a593Smuzhiyun					type = "critical";
2032*4882a593Smuzhiyun				};
2033*4882a593Smuzhiyun			};
2034*4882a593Smuzhiyun		};
2035*4882a593Smuzhiyun
2036*4882a593Smuzhiyun		gpu {
2037*4882a593Smuzhiyun			trips {
2038*4882a593Smuzhiyun				gpu-shutdown-trip {
2039*4882a593Smuzhiyun					temperature = <101000>;
2040*4882a593Smuzhiyun					hysteresis = <0>;
2041*4882a593Smuzhiyun					type = "critical";
2042*4882a593Smuzhiyun				};
2043*4882a593Smuzhiyun			};
2044*4882a593Smuzhiyun		};
2045*4882a593Smuzhiyun	};
2046*4882a593Smuzhiyun};
2047*4882a593Smuzhiyun
2048*4882a593Smuzhiyun&gpio {
2049*4882a593Smuzhiyun	/* I210 Gigabit Ethernet Controller Reset */
2050*4882a593Smuzhiyun	lan-reset-n {
2051*4882a593Smuzhiyun		gpio-hog;
2052*4882a593Smuzhiyun		gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
2053*4882a593Smuzhiyun		output-high;
2054*4882a593Smuzhiyun		line-name = "LAN_RESET_N";
2055*4882a593Smuzhiyun	};
2056*4882a593Smuzhiyun
2057*4882a593Smuzhiyun	/* Control MXM3 pin 26 Reset Module Output Carrier Input */
2058*4882a593Smuzhiyun	reset-moci-ctrl {
2059*4882a593Smuzhiyun		gpio-hog;
2060*4882a593Smuzhiyun		gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
2061*4882a593Smuzhiyun		output-high;
2062*4882a593Smuzhiyun		line-name = "RESET_MOCI_CTRL";
2063*4882a593Smuzhiyun	};
2064*4882a593Smuzhiyun};
2065