1*4882a593Smuzhiyun/dts-v1/; 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun#include "tegra30.dtsi" 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun/ { 6*4882a593Smuzhiyun model = "Toradex Apalis T30"; 7*4882a593Smuzhiyun compatible = "toradex,apalis_t30", "nvidia,tegra30"; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun chosen { 10*4882a593Smuzhiyun stdout-path = &uarta; 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun aliases { 14*4882a593Smuzhiyun i2c0 = "/i2c@7000d000"; 15*4882a593Smuzhiyun i2c1 = "/i2c@7000c000"; 16*4882a593Smuzhiyun i2c2 = "/i2c@7000c500"; 17*4882a593Smuzhiyun i2c3 = "/i2c@7000c700"; 18*4882a593Smuzhiyun mmc0 = "/sdhci@78000600"; 19*4882a593Smuzhiyun mmc1 = "/sdhci@78000400"; 20*4882a593Smuzhiyun mmc2 = "/sdhci@78000000"; 21*4882a593Smuzhiyun spi0 = "/spi@7000d400"; 22*4882a593Smuzhiyun spi1 = "/spi@7000dc00"; 23*4882a593Smuzhiyun spi2 = "/spi@7000de00"; 24*4882a593Smuzhiyun spi3 = "/spi@7000da00"; 25*4882a593Smuzhiyun usb0 = "/usb@7d000000"; 26*4882a593Smuzhiyun usb1 = "/usb@7d004000"; 27*4882a593Smuzhiyun usb2 = "/usb@7d008000"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun memory { 31*4882a593Smuzhiyun device_type = "memory"; 32*4882a593Smuzhiyun reg = <0x80000000 0x40000000>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun pcie-controller@00003000 { 36*4882a593Smuzhiyun status = "okay"; 37*4882a593Smuzhiyun avdd-pexa-supply = <&vdd2_reg>; 38*4882a593Smuzhiyun vdd-pexa-supply = <&vdd2_reg>; 39*4882a593Smuzhiyun avdd-pexb-supply = <&vdd2_reg>; 40*4882a593Smuzhiyun vdd-pexb-supply = <&vdd2_reg>; 41*4882a593Smuzhiyun avdd-pex-pll-supply = <&vdd2_reg>; 42*4882a593Smuzhiyun avdd-plle-supply = <&ldo6_reg>; 43*4882a593Smuzhiyun vddio-pex-ctl-supply = <&sys_3v3_reg>; 44*4882a593Smuzhiyun hvdd-pex-supply = <&sys_3v3_reg>; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun pci@1,0 { 47*4882a593Smuzhiyun /* TS_DIFF1/2/3/4 left disabled */ 48*4882a593Smuzhiyun nvidia,num-lanes = <4>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun pci@2,0 { 52*4882a593Smuzhiyun /* PCIE1_RX/TX left disabled */ 53*4882a593Smuzhiyun nvidia,num-lanes = <1>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun pci@3,0 { 57*4882a593Smuzhiyun status = "okay"; 58*4882a593Smuzhiyun nvidia,num-lanes = <1>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier 64*4882a593Smuzhiyun * board) 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun i2c@7000c000 { 67*4882a593Smuzhiyun status = "okay"; 68*4882a593Smuzhiyun clock-frequency = <400000>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* GEN2_I2C: unused */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on 75*4882a593Smuzhiyun * carrier board) 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun i2c@7000c500 { 78*4882a593Smuzhiyun status = "okay"; 79*4882a593Smuzhiyun clock-frequency = <400000>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ 83*4882a593Smuzhiyun i2c@7000c700 { 84*4882a593Smuzhiyun status = "okay"; 85*4882a593Smuzhiyun clock-frequency = <10000>; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 90*4882a593Smuzhiyun * touch screen controller 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun i2c@7000d000 { 93*4882a593Smuzhiyun status = "okay"; 94*4882a593Smuzhiyun clock-frequency = <100000>; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun pmic: tps65911@2d { 97*4882a593Smuzhiyun compatible = "ti,tps65911"; 98*4882a593Smuzhiyun reg = <0x2d>; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 101*4882a593Smuzhiyun #interrupt-cells = <2>; 102*4882a593Smuzhiyun interrupt-controller; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun ti,system-power-controller; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #gpio-cells = <2>; 107*4882a593Smuzhiyun gpio-controller; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun vcc1-supply = <&sys_3v3_reg>; 110*4882a593Smuzhiyun vcc2-supply = <&sys_3v3_reg>; 111*4882a593Smuzhiyun vcc3-supply = <&vio_reg>; 112*4882a593Smuzhiyun vcc4-supply = <&sys_3v3_reg>; 113*4882a593Smuzhiyun vcc5-supply = <&sys_3v3_reg>; 114*4882a593Smuzhiyun vcc6-supply = <&vio_reg>; 115*4882a593Smuzhiyun vcc7-supply = <&charge_pump_5v0_reg>; 116*4882a593Smuzhiyun vccio-supply = <&sys_3v3_reg>; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun regulators { 119*4882a593Smuzhiyun #address-cells = <1>; 120*4882a593Smuzhiyun #size-cells = <0>; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* SW1: +V1.35_VDDIO_DDR */ 123*4882a593Smuzhiyun vdd1_reg: vdd1 { 124*4882a593Smuzhiyun regulator-name = "vddio_ddr_1v35"; 125*4882a593Smuzhiyun regulator-min-microvolt = <1350000>; 126*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 127*4882a593Smuzhiyun regulator-always-on; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* SW2: +V1.05 */ 131*4882a593Smuzhiyun vdd2_reg: vdd2 { 132*4882a593Smuzhiyun regulator-name = 133*4882a593Smuzhiyun "vdd_pexa,vdd_pexb,vdd_sata"; 134*4882a593Smuzhiyun regulator-min-microvolt = <1050000>; 135*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* SW CTRL: +V1.0_VDD_CPU */ 139*4882a593Smuzhiyun vddctrl_reg: vddctrl { 140*4882a593Smuzhiyun regulator-name = "vdd_cpu,vdd_sys"; 141*4882a593Smuzhiyun regulator-min-microvolt = <1150000>; 142*4882a593Smuzhiyun regulator-max-microvolt = <1150000>; 143*4882a593Smuzhiyun regulator-always-on; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* SWIO: +V1.8 */ 147*4882a593Smuzhiyun vio_reg: vio { 148*4882a593Smuzhiyun regulator-name = "vdd_1v8_gen"; 149*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 150*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 151*4882a593Smuzhiyun regulator-always-on; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* LDO1: unused */ 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* 157*4882a593Smuzhiyun * EN_+V3.3 switching via FET: 158*4882a593Smuzhiyun * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN 159*4882a593Smuzhiyun * see also v3_3 fixed supply 160*4882a593Smuzhiyun */ 161*4882a593Smuzhiyun ldo2_reg: ldo2 { 162*4882a593Smuzhiyun regulator-name = "en_3v3"; 163*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 164*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 165*4882a593Smuzhiyun regulator-always-on; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* +V1.2_CSI */ 169*4882a593Smuzhiyun ldo3_reg: ldo3 { 170*4882a593Smuzhiyun regulator-name = 171*4882a593Smuzhiyun "avdd_dsi_csi,pwrdet_mipi"; 172*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 173*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* +V1.2_VDD_RTC */ 177*4882a593Smuzhiyun ldo4_reg: ldo4 { 178*4882a593Smuzhiyun regulator-name = "vdd_rtc"; 179*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 180*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 181*4882a593Smuzhiyun regulator-always-on; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun /* 185*4882a593Smuzhiyun * +V2.8_AVDD_VDAC: 186*4882a593Smuzhiyun * only required for analog RGB 187*4882a593Smuzhiyun */ 188*4882a593Smuzhiyun ldo5_reg: ldo5 { 189*4882a593Smuzhiyun regulator-name = "avdd_vdac"; 190*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 191*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 192*4882a593Smuzhiyun regulator-always-on; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* 196*4882a593Smuzhiyun * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V 197*4882a593Smuzhiyun * but LDO6 can't set voltage in 50mV 198*4882a593Smuzhiyun * granularity 199*4882a593Smuzhiyun */ 200*4882a593Smuzhiyun ldo6_reg: ldo6 { 201*4882a593Smuzhiyun regulator-name = "avdd_plle"; 202*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 203*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun /* +V1.2_AVDD_PLL */ 207*4882a593Smuzhiyun ldo7_reg: ldo7 { 208*4882a593Smuzhiyun regulator-name = "avdd_pll"; 209*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 210*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 211*4882a593Smuzhiyun regulator-always-on; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun /* +V1.0_VDD_DDR_HS */ 215*4882a593Smuzhiyun ldo8_reg: ldo8 { 216*4882a593Smuzhiyun regulator-name = "vdd_ddr_hs"; 217*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 218*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 219*4882a593Smuzhiyun regulator-always-on; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun /* SPI1: Apalis SPI1 */ 226*4882a593Smuzhiyun spi@7000d400 { 227*4882a593Smuzhiyun status = "okay"; 228*4882a593Smuzhiyun spi-max-frequency = <25000000>; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* SPI4: CAN2 */ 232*4882a593Smuzhiyun spi@7000da00 { 233*4882a593Smuzhiyun status = "okay"; 234*4882a593Smuzhiyun spi-max-frequency = <25000000>; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* SPI5: Apalis SPI2 */ 238*4882a593Smuzhiyun spi@7000dc00 { 239*4882a593Smuzhiyun status = "okay"; 240*4882a593Smuzhiyun spi-max-frequency = <25000000>; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun /* SPI6: CAN1 */ 244*4882a593Smuzhiyun spi@7000de00 { 245*4882a593Smuzhiyun status = "okay"; 246*4882a593Smuzhiyun spi-max-frequency = <25000000>; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun sdhci@78000000 { 250*4882a593Smuzhiyun status = "okay"; 251*4882a593Smuzhiyun bus-width = <4>; 252*4882a593Smuzhiyun /* SD1_CD# */ 253*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun sdhci@78000400 { 257*4882a593Smuzhiyun status = "okay"; 258*4882a593Smuzhiyun bus-width = <8>; 259*4882a593Smuzhiyun /* MMC1_CD# */ 260*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun sdhci@78000600 { 264*4882a593Smuzhiyun status = "okay"; 265*4882a593Smuzhiyun bus-width = <8>; 266*4882a593Smuzhiyun non-removable; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ 270*4882a593Smuzhiyun usb@7d000000 { 271*4882a593Smuzhiyun status = "okay"; 272*4882a593Smuzhiyun dr_mode = "otg"; 273*4882a593Smuzhiyun /* USBO1_EN */ 274*4882a593Smuzhiyun nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ 278*4882a593Smuzhiyun usb@7d004000 { 279*4882a593Smuzhiyun status = "okay"; 280*4882a593Smuzhiyun /* USBH_EN */ 281*4882a593Smuzhiyun nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; 282*4882a593Smuzhiyun }; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ 285*4882a593Smuzhiyun usb@7d008000 { 286*4882a593Smuzhiyun status = "okay"; 287*4882a593Smuzhiyun /* USBH_EN */ 288*4882a593Smuzhiyun nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun clocks { 292*4882a593Smuzhiyun compatible = "simple-bus"; 293*4882a593Smuzhiyun #address-cells = <1>; 294*4882a593Smuzhiyun #size-cells = <0>; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun clk32k_in: clk@0 { 297*4882a593Smuzhiyun compatible = "fixed-clock"; 298*4882a593Smuzhiyun reg=<0>; 299*4882a593Smuzhiyun #clock-cells = <0>; 300*4882a593Smuzhiyun clock-frequency = <32768>; 301*4882a593Smuzhiyun }; 302*4882a593Smuzhiyun clk16m: clk@1 { 303*4882a593Smuzhiyun compatible = "fixed-clock"; 304*4882a593Smuzhiyun reg=<1>; 305*4882a593Smuzhiyun #clock-cells = <0>; 306*4882a593Smuzhiyun clock-frequency = <16000000>; 307*4882a593Smuzhiyun clock-output-names = "clk16m"; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun regulators { 312*4882a593Smuzhiyun compatible = "simple-bus"; 313*4882a593Smuzhiyun #address-cells = <1>; 314*4882a593Smuzhiyun #size-cells = <0>; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun sys_3v3_reg: regulator@100 { 317*4882a593Smuzhiyun compatible = "regulator-fixed"; 318*4882a593Smuzhiyun reg = <100>; 319*4882a593Smuzhiyun regulator-name = "3v3"; 320*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 321*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 322*4882a593Smuzhiyun regulator-always-on; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun charge_pump_5v0_reg: regulator@101 { 326*4882a593Smuzhiyun compatible = "regulator-fixed"; 327*4882a593Smuzhiyun reg = <101>; 328*4882a593Smuzhiyun regulator-name = "5v0"; 329*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 330*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 331*4882a593Smuzhiyun regulator-always-on; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun }; 334*4882a593Smuzhiyun}; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun&uarta { 337*4882a593Smuzhiyun status = "okay"; 338*4882a593Smuzhiyun}; 339