xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/tegra114-dalmore.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * This dts file supports Dalmore A04.
4*4882a593Smuzhiyun * Other board revisions are not supported
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
10*4882a593Smuzhiyun#include "tegra114.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "NVIDIA Tegra114 Dalmore evaluation board";
14*4882a593Smuzhiyun	compatible = "nvidia,dalmore", "nvidia,tegra114";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	aliases {
17*4882a593Smuzhiyun		rtc0 = "/i2c@7000d000/tps65913@58";
18*4882a593Smuzhiyun		rtc1 = "/rtc@7000e000";
19*4882a593Smuzhiyun		serial0 = &uartd;
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	chosen {
23*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	memory@80000000 {
27*4882a593Smuzhiyun		reg = <0x80000000 0x40000000>;
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	host1x@50000000 {
31*4882a593Smuzhiyun		hdmi@54280000 {
32*4882a593Smuzhiyun			status = "okay";
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun			hdmi-supply = <&vdd_5v0_hdmi>;
35*4882a593Smuzhiyun			vdd-supply = <&vdd_hdmi_reg>;
36*4882a593Smuzhiyun			pll-supply = <&palmas_smps3_reg>;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
39*4882a593Smuzhiyun			nvidia,hpd-gpio =
40*4882a593Smuzhiyun				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
41*4882a593Smuzhiyun		};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		dsi@54300000 {
44*4882a593Smuzhiyun			status = "okay";
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun			avdd-dsi-csi-supply = <&avdd_1v2_reg>;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun			panel@0 {
49*4882a593Smuzhiyun				compatible = "panasonic,vvx10f004b00";
50*4882a593Smuzhiyun				reg = <0>;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun				power-supply = <&avdd_lcd_reg>;
53*4882a593Smuzhiyun				backlight = <&backlight>;
54*4882a593Smuzhiyun			};
55*4882a593Smuzhiyun		};
56*4882a593Smuzhiyun	};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	pinmux@70000868 {
59*4882a593Smuzhiyun		pinctrl-names = "default";
60*4882a593Smuzhiyun		pinctrl-0 = <&state_default>;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		state_default: pinmux {
63*4882a593Smuzhiyun			clk1_out_pw4 {
64*4882a593Smuzhiyun				nvidia,pins = "clk1_out_pw4";
65*4882a593Smuzhiyun				nvidia,function = "extperiph1";
66*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
67*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
68*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
69*4882a593Smuzhiyun			};
70*4882a593Smuzhiyun			dap1_din_pn1 {
71*4882a593Smuzhiyun				nvidia,pins = "dap1_din_pn1";
72*4882a593Smuzhiyun				nvidia,function = "i2s0";
73*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
74*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
75*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
76*4882a593Smuzhiyun			};
77*4882a593Smuzhiyun			dap1_dout_pn2 {
78*4882a593Smuzhiyun				nvidia,pins = "dap1_dout_pn2",
79*4882a593Smuzhiyun						"dap1_fs_pn0",
80*4882a593Smuzhiyun						"dap1_sclk_pn3";
81*4882a593Smuzhiyun				nvidia,function = "i2s0";
82*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
83*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
84*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
85*4882a593Smuzhiyun			};
86*4882a593Smuzhiyun			dap2_din_pa4 {
87*4882a593Smuzhiyun				nvidia,pins = "dap2_din_pa4";
88*4882a593Smuzhiyun				nvidia,function = "i2s1";
89*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
90*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
91*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
92*4882a593Smuzhiyun			};
93*4882a593Smuzhiyun			dap2_dout_pa5 {
94*4882a593Smuzhiyun				nvidia,pins = "dap2_dout_pa5",
95*4882a593Smuzhiyun						"dap2_fs_pa2",
96*4882a593Smuzhiyun						"dap2_sclk_pa3";
97*4882a593Smuzhiyun				nvidia,function = "i2s1";
98*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
99*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
100*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
101*4882a593Smuzhiyun			};
102*4882a593Smuzhiyun			dap4_din_pp5 {
103*4882a593Smuzhiyun				nvidia,pins = "dap4_din_pp5",
104*4882a593Smuzhiyun						"dap4_dout_pp6",
105*4882a593Smuzhiyun						"dap4_fs_pp4",
106*4882a593Smuzhiyun						"dap4_sclk_pp7";
107*4882a593Smuzhiyun				nvidia,function = "i2s3";
108*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
109*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
110*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
111*4882a593Smuzhiyun			};
112*4882a593Smuzhiyun			dvfs_pwm_px0 {
113*4882a593Smuzhiyun				nvidia,pins = "dvfs_pwm_px0",
114*4882a593Smuzhiyun						"dvfs_clk_px2";
115*4882a593Smuzhiyun				nvidia,function = "cldvfs";
116*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
117*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
118*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
119*4882a593Smuzhiyun			};
120*4882a593Smuzhiyun			ulpi_clk_py0 {
121*4882a593Smuzhiyun				nvidia,pins = "ulpi_clk_py0",
122*4882a593Smuzhiyun						"ulpi_data0_po1",
123*4882a593Smuzhiyun						"ulpi_data1_po2",
124*4882a593Smuzhiyun						"ulpi_data2_po3",
125*4882a593Smuzhiyun						"ulpi_data3_po4",
126*4882a593Smuzhiyun						"ulpi_data4_po5",
127*4882a593Smuzhiyun						"ulpi_data5_po6",
128*4882a593Smuzhiyun						"ulpi_data6_po7",
129*4882a593Smuzhiyun						"ulpi_data7_po0";
130*4882a593Smuzhiyun				nvidia,function = "ulpi";
131*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
133*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
134*4882a593Smuzhiyun			};
135*4882a593Smuzhiyun			ulpi_dir_py1 {
136*4882a593Smuzhiyun				nvidia,pins = "ulpi_dir_py1",
137*4882a593Smuzhiyun						"ulpi_nxt_py2";
138*4882a593Smuzhiyun				nvidia,function = "ulpi";
139*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
140*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
141*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
142*4882a593Smuzhiyun			};
143*4882a593Smuzhiyun			ulpi_stp_py3 {
144*4882a593Smuzhiyun				nvidia,pins = "ulpi_stp_py3";
145*4882a593Smuzhiyun				nvidia,function = "ulpi";
146*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
147*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
148*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
149*4882a593Smuzhiyun			};
150*4882a593Smuzhiyun			cam_i2c_scl_pbb1 {
151*4882a593Smuzhiyun				nvidia,pins = "cam_i2c_scl_pbb1",
152*4882a593Smuzhiyun						"cam_i2c_sda_pbb2";
153*4882a593Smuzhiyun				nvidia,function = "i2c3";
154*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
156*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
157*4882a593Smuzhiyun				nvidia,lock = <TEGRA_PIN_DISABLE>;
158*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
159*4882a593Smuzhiyun			};
160*4882a593Smuzhiyun			cam_mclk_pcc0 {
161*4882a593Smuzhiyun				nvidia,pins = "cam_mclk_pcc0",
162*4882a593Smuzhiyun						"pbb0";
163*4882a593Smuzhiyun				nvidia,function = "vi_alt3";
164*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
165*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
166*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
167*4882a593Smuzhiyun				nvidia,lock = <TEGRA_PIN_DISABLE>;
168*4882a593Smuzhiyun			};
169*4882a593Smuzhiyun			gen2_i2c_scl_pt5 {
170*4882a593Smuzhiyun				nvidia,pins = "gen2_i2c_scl_pt5",
171*4882a593Smuzhiyun						"gen2_i2c_sda_pt6";
172*4882a593Smuzhiyun				nvidia,function = "i2c2";
173*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
174*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
175*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
176*4882a593Smuzhiyun				nvidia,lock = <TEGRA_PIN_DISABLE>;
177*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
178*4882a593Smuzhiyun			};
179*4882a593Smuzhiyun			gmi_a16_pj7 {
180*4882a593Smuzhiyun				nvidia,pins = "gmi_a16_pj7";
181*4882a593Smuzhiyun				nvidia,function = "uartd";
182*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
183*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
184*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
185*4882a593Smuzhiyun			};
186*4882a593Smuzhiyun			gmi_a17_pb0 {
187*4882a593Smuzhiyun				nvidia,pins = "gmi_a17_pb0",
188*4882a593Smuzhiyun						"gmi_a18_pb1";
189*4882a593Smuzhiyun				nvidia,function = "uartd";
190*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
191*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
192*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
193*4882a593Smuzhiyun			};
194*4882a593Smuzhiyun			gmi_a19_pk7 {
195*4882a593Smuzhiyun				nvidia,pins = "gmi_a19_pk7";
196*4882a593Smuzhiyun				nvidia,function = "uartd";
197*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
199*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
200*4882a593Smuzhiyun			};
201*4882a593Smuzhiyun			gmi_ad5_pg5 {
202*4882a593Smuzhiyun				nvidia,pins = "gmi_ad5_pg5",
203*4882a593Smuzhiyun						"gmi_cs6_n_pi3",
204*4882a593Smuzhiyun						"gmi_wr_n_pi0";
205*4882a593Smuzhiyun				nvidia,function = "spi4";
206*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
207*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
208*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
209*4882a593Smuzhiyun			};
210*4882a593Smuzhiyun			gmi_ad6_pg6 {
211*4882a593Smuzhiyun				nvidia,pins = "gmi_ad6_pg6",
212*4882a593Smuzhiyun						"gmi_ad7_pg7";
213*4882a593Smuzhiyun				nvidia,function = "spi4";
214*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
215*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
216*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
217*4882a593Smuzhiyun			};
218*4882a593Smuzhiyun			gmi_ad12_ph4 {
219*4882a593Smuzhiyun				nvidia,pins = "gmi_ad12_ph4";
220*4882a593Smuzhiyun				nvidia,function = "rsvd4";
221*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
222*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
223*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
224*4882a593Smuzhiyun			};
225*4882a593Smuzhiyun			gmi_ad9_ph1 {
226*4882a593Smuzhiyun				nvidia,pins = "gmi_ad9_ph1";
227*4882a593Smuzhiyun				nvidia,function = "pwm1";
228*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
229*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
230*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
231*4882a593Smuzhiyun			};
232*4882a593Smuzhiyun			gmi_cs1_n_pj2 {
233*4882a593Smuzhiyun				nvidia,pins = "gmi_cs1_n_pj2",
234*4882a593Smuzhiyun						"gmi_oe_n_pi1";
235*4882a593Smuzhiyun				nvidia,function = "soc";
236*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
237*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
238*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
239*4882a593Smuzhiyun			};
240*4882a593Smuzhiyun			clk2_out_pw5 {
241*4882a593Smuzhiyun				nvidia,pins = "clk2_out_pw5";
242*4882a593Smuzhiyun				nvidia,function = "extperiph2";
243*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
244*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
245*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
246*4882a593Smuzhiyun			};
247*4882a593Smuzhiyun			sdmmc1_clk_pz0 {
248*4882a593Smuzhiyun				nvidia,pins = "sdmmc1_clk_pz0";
249*4882a593Smuzhiyun				nvidia,function = "sdmmc1";
250*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
251*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
252*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
253*4882a593Smuzhiyun			};
254*4882a593Smuzhiyun			sdmmc1_cmd_pz1 {
255*4882a593Smuzhiyun				nvidia,pins = "sdmmc1_cmd_pz1",
256*4882a593Smuzhiyun						"sdmmc1_dat0_py7",
257*4882a593Smuzhiyun						"sdmmc1_dat1_py6",
258*4882a593Smuzhiyun						"sdmmc1_dat2_py5",
259*4882a593Smuzhiyun						"sdmmc1_dat3_py4";
260*4882a593Smuzhiyun				nvidia,function = "sdmmc1";
261*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
262*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
263*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
264*4882a593Smuzhiyun			};
265*4882a593Smuzhiyun			sdmmc1_wp_n_pv3 {
266*4882a593Smuzhiyun				nvidia,pins = "sdmmc1_wp_n_pv3";
267*4882a593Smuzhiyun				nvidia,function = "spi4";
268*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
269*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
270*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
271*4882a593Smuzhiyun			};
272*4882a593Smuzhiyun			sdmmc3_clk_pa6 {
273*4882a593Smuzhiyun				nvidia,pins = "sdmmc3_clk_pa6";
274*4882a593Smuzhiyun				nvidia,function = "sdmmc3";
275*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
276*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
277*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
278*4882a593Smuzhiyun			};
279*4882a593Smuzhiyun			sdmmc3_cmd_pa7 {
280*4882a593Smuzhiyun				nvidia,pins = "sdmmc3_cmd_pa7",
281*4882a593Smuzhiyun						"sdmmc3_dat0_pb7",
282*4882a593Smuzhiyun						"sdmmc3_dat1_pb6",
283*4882a593Smuzhiyun						"sdmmc3_dat2_pb5",
284*4882a593Smuzhiyun						"sdmmc3_dat3_pb4",
285*4882a593Smuzhiyun						"kb_col4_pq4",
286*4882a593Smuzhiyun						"sdmmc3_clk_lb_out_pee4",
287*4882a593Smuzhiyun						"sdmmc3_clk_lb_in_pee5";
288*4882a593Smuzhiyun				nvidia,function = "sdmmc3";
289*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
290*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
291*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
292*4882a593Smuzhiyun			};
293*4882a593Smuzhiyun			sdmmc4_clk_pcc4 {
294*4882a593Smuzhiyun				nvidia,pins = "sdmmc4_clk_pcc4";
295*4882a593Smuzhiyun				nvidia,function = "sdmmc4";
296*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
297*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
298*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
299*4882a593Smuzhiyun			};
300*4882a593Smuzhiyun			sdmmc4_cmd_pt7 {
301*4882a593Smuzhiyun				nvidia,pins = "sdmmc4_cmd_pt7",
302*4882a593Smuzhiyun						"sdmmc4_dat0_paa0",
303*4882a593Smuzhiyun						"sdmmc4_dat1_paa1",
304*4882a593Smuzhiyun						"sdmmc4_dat2_paa2",
305*4882a593Smuzhiyun						"sdmmc4_dat3_paa3",
306*4882a593Smuzhiyun						"sdmmc4_dat4_paa4",
307*4882a593Smuzhiyun						"sdmmc4_dat5_paa5",
308*4882a593Smuzhiyun						"sdmmc4_dat6_paa6",
309*4882a593Smuzhiyun						"sdmmc4_dat7_paa7";
310*4882a593Smuzhiyun				nvidia,function = "sdmmc4";
311*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
312*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
313*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
314*4882a593Smuzhiyun			};
315*4882a593Smuzhiyun			clk_32k_out_pa0 {
316*4882a593Smuzhiyun				nvidia,pins = "clk_32k_out_pa0";
317*4882a593Smuzhiyun				nvidia,function = "blink";
318*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
319*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
320*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
321*4882a593Smuzhiyun			};
322*4882a593Smuzhiyun			kb_col0_pq0 {
323*4882a593Smuzhiyun				nvidia,pins = "kb_col0_pq0",
324*4882a593Smuzhiyun						"kb_col1_pq1",
325*4882a593Smuzhiyun						"kb_col2_pq2",
326*4882a593Smuzhiyun						"kb_row0_pr0",
327*4882a593Smuzhiyun						"kb_row1_pr1",
328*4882a593Smuzhiyun						"kb_row2_pr2";
329*4882a593Smuzhiyun				nvidia,function = "kbc";
330*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
331*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
332*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
333*4882a593Smuzhiyun			};
334*4882a593Smuzhiyun			dap3_din_pp1 {
335*4882a593Smuzhiyun				nvidia,pins = "dap3_din_pp1",
336*4882a593Smuzhiyun						"dap3_sclk_pp3";
337*4882a593Smuzhiyun				nvidia,function = "displayb";
338*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
339*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
340*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
341*4882a593Smuzhiyun			};
342*4882a593Smuzhiyun			pv0 {
343*4882a593Smuzhiyun				nvidia,pins = "pv0";
344*4882a593Smuzhiyun				nvidia,function = "rsvd4";
345*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
346*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
347*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
348*4882a593Smuzhiyun			};
349*4882a593Smuzhiyun			kb_row7_pr7 {
350*4882a593Smuzhiyun				nvidia,pins = "kb_row7_pr7";
351*4882a593Smuzhiyun				nvidia,function = "rsvd2";
352*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
353*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
354*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
355*4882a593Smuzhiyun			};
356*4882a593Smuzhiyun			kb_row10_ps2 {
357*4882a593Smuzhiyun				nvidia,pins = "kb_row10_ps2";
358*4882a593Smuzhiyun				nvidia,function = "uarta";
359*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
360*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
361*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
362*4882a593Smuzhiyun			};
363*4882a593Smuzhiyun			kb_row9_ps1 {
364*4882a593Smuzhiyun				nvidia,pins = "kb_row9_ps1";
365*4882a593Smuzhiyun				nvidia,function = "uarta";
366*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
367*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
368*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
369*4882a593Smuzhiyun			};
370*4882a593Smuzhiyun			pwr_i2c_scl_pz6 {
371*4882a593Smuzhiyun				nvidia,pins = "pwr_i2c_scl_pz6",
372*4882a593Smuzhiyun						"pwr_i2c_sda_pz7";
373*4882a593Smuzhiyun				nvidia,function = "i2cpwr";
374*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
375*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
376*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
377*4882a593Smuzhiyun				nvidia,lock = <TEGRA_PIN_DISABLE>;
378*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
379*4882a593Smuzhiyun			};
380*4882a593Smuzhiyun			sys_clk_req_pz5 {
381*4882a593Smuzhiyun				nvidia,pins = "sys_clk_req_pz5";
382*4882a593Smuzhiyun				nvidia,function = "sysclk";
383*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
384*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
385*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
386*4882a593Smuzhiyun			};
387*4882a593Smuzhiyun			core_pwr_req {
388*4882a593Smuzhiyun				nvidia,pins = "core_pwr_req";
389*4882a593Smuzhiyun				nvidia,function = "pwron";
390*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
391*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
392*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
393*4882a593Smuzhiyun			};
394*4882a593Smuzhiyun			cpu_pwr_req {
395*4882a593Smuzhiyun				nvidia,pins = "cpu_pwr_req";
396*4882a593Smuzhiyun				nvidia,function = "cpu";
397*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
398*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
399*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
400*4882a593Smuzhiyun			};
401*4882a593Smuzhiyun			pwr_int_n {
402*4882a593Smuzhiyun				nvidia,pins = "pwr_int_n";
403*4882a593Smuzhiyun				nvidia,function = "pmi";
404*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
405*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
406*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
407*4882a593Smuzhiyun			};
408*4882a593Smuzhiyun			reset_out_n {
409*4882a593Smuzhiyun				nvidia,pins = "reset_out_n";
410*4882a593Smuzhiyun				nvidia,function = "reset_out_n";
411*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
412*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
413*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
414*4882a593Smuzhiyun			};
415*4882a593Smuzhiyun			clk3_out_pee0 {
416*4882a593Smuzhiyun				nvidia,pins = "clk3_out_pee0";
417*4882a593Smuzhiyun				nvidia,function = "extperiph3";
418*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
419*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
420*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
421*4882a593Smuzhiyun			};
422*4882a593Smuzhiyun			gen1_i2c_scl_pc4 {
423*4882a593Smuzhiyun				nvidia,pins = "gen1_i2c_scl_pc4",
424*4882a593Smuzhiyun						"gen1_i2c_sda_pc5";
425*4882a593Smuzhiyun				nvidia,function = "i2c1";
426*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
427*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
428*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
429*4882a593Smuzhiyun				nvidia,lock = <TEGRA_PIN_DISABLE>;
430*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
431*4882a593Smuzhiyun			};
432*4882a593Smuzhiyun			uart2_cts_n_pj5 {
433*4882a593Smuzhiyun				nvidia,pins = "uart2_cts_n_pj5";
434*4882a593Smuzhiyun				nvidia,function = "uartb";
435*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
436*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
437*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
438*4882a593Smuzhiyun			};
439*4882a593Smuzhiyun			uart2_rts_n_pj6 {
440*4882a593Smuzhiyun				nvidia,pins = "uart2_rts_n_pj6";
441*4882a593Smuzhiyun				nvidia,function = "uartb";
442*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
443*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
444*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
445*4882a593Smuzhiyun			};
446*4882a593Smuzhiyun			uart2_rxd_pc3 {
447*4882a593Smuzhiyun				nvidia,pins = "uart2_rxd_pc3";
448*4882a593Smuzhiyun				nvidia,function = "irda";
449*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
450*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
451*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
452*4882a593Smuzhiyun			};
453*4882a593Smuzhiyun			uart2_txd_pc2 {
454*4882a593Smuzhiyun				nvidia,pins = "uart2_txd_pc2";
455*4882a593Smuzhiyun				nvidia,function = "irda";
456*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
457*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
458*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
459*4882a593Smuzhiyun			};
460*4882a593Smuzhiyun			uart3_cts_n_pa1 {
461*4882a593Smuzhiyun				nvidia,pins = "uart3_cts_n_pa1",
462*4882a593Smuzhiyun						"uart3_rxd_pw7";
463*4882a593Smuzhiyun				nvidia,function = "uartc";
464*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
465*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
466*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
467*4882a593Smuzhiyun			};
468*4882a593Smuzhiyun			uart3_rts_n_pc0 {
469*4882a593Smuzhiyun				nvidia,pins = "uart3_rts_n_pc0",
470*4882a593Smuzhiyun						"uart3_txd_pw6";
471*4882a593Smuzhiyun				nvidia,function = "uartc";
472*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
473*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
474*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
475*4882a593Smuzhiyun			};
476*4882a593Smuzhiyun			owr {
477*4882a593Smuzhiyun				nvidia,pins = "owr";
478*4882a593Smuzhiyun				nvidia,function = "owr";
479*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
480*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
481*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
482*4882a593Smuzhiyun			};
483*4882a593Smuzhiyun			hdmi_cec_pee3 {
484*4882a593Smuzhiyun				nvidia,pins = "hdmi_cec_pee3";
485*4882a593Smuzhiyun				nvidia,function = "cec";
486*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
487*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
488*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
489*4882a593Smuzhiyun				nvidia,lock = <TEGRA_PIN_DISABLE>;
490*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
491*4882a593Smuzhiyun			};
492*4882a593Smuzhiyun			ddc_scl_pv4 {
493*4882a593Smuzhiyun				nvidia,pins = "ddc_scl_pv4",
494*4882a593Smuzhiyun						"ddc_sda_pv5";
495*4882a593Smuzhiyun				nvidia,function = "i2c4";
496*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
497*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
498*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
499*4882a593Smuzhiyun				nvidia,lock = <TEGRA_PIN_DISABLE>;
500*4882a593Smuzhiyun				nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
501*4882a593Smuzhiyun			};
502*4882a593Smuzhiyun			spdif_in_pk6 {
503*4882a593Smuzhiyun				nvidia,pins = "spdif_in_pk6";
504*4882a593Smuzhiyun				nvidia,function = "usb";
505*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
506*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
507*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
508*4882a593Smuzhiyun				nvidia,lock = <TEGRA_PIN_DISABLE>;
509*4882a593Smuzhiyun			};
510*4882a593Smuzhiyun			usb_vbus_en0_pn4 {
511*4882a593Smuzhiyun				nvidia,pins = "usb_vbus_en0_pn4";
512*4882a593Smuzhiyun				nvidia,function = "usb";
513*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
514*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
515*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
516*4882a593Smuzhiyun				nvidia,lock = <TEGRA_PIN_DISABLE>;
517*4882a593Smuzhiyun				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
518*4882a593Smuzhiyun			};
519*4882a593Smuzhiyun			gpio_x6_aud_px6 {
520*4882a593Smuzhiyun				nvidia,pins = "gpio_x6_aud_px6";
521*4882a593Smuzhiyun				nvidia,function = "spi6";
522*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
523*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
524*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
525*4882a593Smuzhiyun			};
526*4882a593Smuzhiyun			gpio_x4_aud_px4 {
527*4882a593Smuzhiyun				nvidia,pins = "gpio_x4_aud_px4",
528*4882a593Smuzhiyun						"gpio_x7_aud_px7";
529*4882a593Smuzhiyun				nvidia,function = "rsvd1";
530*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
531*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
532*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
533*4882a593Smuzhiyun			};
534*4882a593Smuzhiyun			gpio_x5_aud_px5 {
535*4882a593Smuzhiyun				nvidia,pins = "gpio_x5_aud_px5";
536*4882a593Smuzhiyun				nvidia,function = "rsvd1";
537*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
538*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
539*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
540*4882a593Smuzhiyun			};
541*4882a593Smuzhiyun			gpio_w2_aud_pw2 {
542*4882a593Smuzhiyun				nvidia,pins = "gpio_w2_aud_pw2";
543*4882a593Smuzhiyun				nvidia,function = "rsvd2";
544*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
545*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
546*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
547*4882a593Smuzhiyun			};
548*4882a593Smuzhiyun			gpio_w3_aud_pw3 {
549*4882a593Smuzhiyun				nvidia,pins = "gpio_w3_aud_pw3";
550*4882a593Smuzhiyun				nvidia,function = "spi6";
551*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
552*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
553*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
554*4882a593Smuzhiyun			};
555*4882a593Smuzhiyun			gpio_x1_aud_px1 {
556*4882a593Smuzhiyun				nvidia,pins = "gpio_x1_aud_px1";
557*4882a593Smuzhiyun				nvidia,function = "rsvd4";
558*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
559*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
560*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
561*4882a593Smuzhiyun			};
562*4882a593Smuzhiyun			gpio_x3_aud_px3 {
563*4882a593Smuzhiyun				nvidia,pins = "gpio_x3_aud_px3";
564*4882a593Smuzhiyun				nvidia,function = "rsvd4";
565*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
566*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
567*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
568*4882a593Smuzhiyun			};
569*4882a593Smuzhiyun			dap3_fs_pp0 {
570*4882a593Smuzhiyun				nvidia,pins = "dap3_fs_pp0";
571*4882a593Smuzhiyun				nvidia,function = "i2s2";
572*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
573*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
574*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
575*4882a593Smuzhiyun			};
576*4882a593Smuzhiyun			dap3_dout_pp2 {
577*4882a593Smuzhiyun				nvidia,pins = "dap3_dout_pp2";
578*4882a593Smuzhiyun				nvidia,function = "i2s2";
579*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
580*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
581*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
582*4882a593Smuzhiyun			};
583*4882a593Smuzhiyun			pv1 {
584*4882a593Smuzhiyun				nvidia,pins = "pv1";
585*4882a593Smuzhiyun				nvidia,function = "rsvd1";
586*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
587*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
588*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
589*4882a593Smuzhiyun			};
590*4882a593Smuzhiyun			pbb3 {
591*4882a593Smuzhiyun				nvidia,pins = "pbb3",
592*4882a593Smuzhiyun						"pbb5",
593*4882a593Smuzhiyun						"pbb6",
594*4882a593Smuzhiyun						"pbb7";
595*4882a593Smuzhiyun				nvidia,function = "rsvd4";
596*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
597*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
598*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
599*4882a593Smuzhiyun			};
600*4882a593Smuzhiyun			pcc1 {
601*4882a593Smuzhiyun				nvidia,pins = "pcc1",
602*4882a593Smuzhiyun						"pcc2";
603*4882a593Smuzhiyun				nvidia,function = "rsvd4";
604*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
605*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
606*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
607*4882a593Smuzhiyun			};
608*4882a593Smuzhiyun			gmi_ad0_pg0 {
609*4882a593Smuzhiyun				nvidia,pins = "gmi_ad0_pg0",
610*4882a593Smuzhiyun						"gmi_ad1_pg1";
611*4882a593Smuzhiyun				nvidia,function = "gmi";
612*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
613*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
614*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
615*4882a593Smuzhiyun			};
616*4882a593Smuzhiyun			gmi_ad10_ph2 {
617*4882a593Smuzhiyun				nvidia,pins = "gmi_ad10_ph2",
618*4882a593Smuzhiyun						"gmi_ad11_ph3",
619*4882a593Smuzhiyun						"gmi_ad13_ph5",
620*4882a593Smuzhiyun						"gmi_ad8_ph0",
621*4882a593Smuzhiyun						"gmi_clk_pk1";
622*4882a593Smuzhiyun				nvidia,function = "gmi";
623*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
624*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
625*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
626*4882a593Smuzhiyun			};
627*4882a593Smuzhiyun			gmi_ad2_pg2 {
628*4882a593Smuzhiyun				nvidia,pins = "gmi_ad2_pg2",
629*4882a593Smuzhiyun						"gmi_ad3_pg3";
630*4882a593Smuzhiyun				nvidia,function = "gmi";
631*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
632*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
633*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
634*4882a593Smuzhiyun			};
635*4882a593Smuzhiyun			gmi_adv_n_pk0 {
636*4882a593Smuzhiyun				nvidia,pins = "gmi_adv_n_pk0",
637*4882a593Smuzhiyun						"gmi_cs0_n_pj0",
638*4882a593Smuzhiyun						"gmi_cs2_n_pk3",
639*4882a593Smuzhiyun						"gmi_cs4_n_pk2",
640*4882a593Smuzhiyun						"gmi_cs7_n_pi6",
641*4882a593Smuzhiyun						"gmi_dqs_p_pj3",
642*4882a593Smuzhiyun						"gmi_iordy_pi5",
643*4882a593Smuzhiyun						"gmi_wp_n_pc7";
644*4882a593Smuzhiyun				nvidia,function = "gmi";
645*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
646*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
647*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
648*4882a593Smuzhiyun			};
649*4882a593Smuzhiyun			gmi_cs3_n_pk4 {
650*4882a593Smuzhiyun				nvidia,pins = "gmi_cs3_n_pk4";
651*4882a593Smuzhiyun				nvidia,function = "gmi";
652*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
653*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
654*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
655*4882a593Smuzhiyun			};
656*4882a593Smuzhiyun			clk2_req_pcc5 {
657*4882a593Smuzhiyun				nvidia,pins = "clk2_req_pcc5";
658*4882a593Smuzhiyun				nvidia,function = "rsvd4";
659*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
660*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
661*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
662*4882a593Smuzhiyun			};
663*4882a593Smuzhiyun			kb_col3_pq3 {
664*4882a593Smuzhiyun				nvidia,pins = "kb_col3_pq3",
665*4882a593Smuzhiyun						"kb_col6_pq6",
666*4882a593Smuzhiyun						"kb_col7_pq7";
667*4882a593Smuzhiyun				nvidia,function = "kbc";
668*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
669*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
670*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
671*4882a593Smuzhiyun			};
672*4882a593Smuzhiyun			kb_col5_pq5 {
673*4882a593Smuzhiyun				nvidia,pins = "kb_col5_pq5";
674*4882a593Smuzhiyun				nvidia,function = "kbc";
675*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
676*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
677*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
678*4882a593Smuzhiyun			};
679*4882a593Smuzhiyun			kb_row3_pr3 {
680*4882a593Smuzhiyun				nvidia,pins = "kb_row3_pr3",
681*4882a593Smuzhiyun						"kb_row4_pr4",
682*4882a593Smuzhiyun						"kb_row6_pr6",
683*4882a593Smuzhiyun						"kb_row8_ps0";
684*4882a593Smuzhiyun				nvidia,function = "kbc";
685*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
686*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
687*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
688*4882a593Smuzhiyun			};
689*4882a593Smuzhiyun			clk3_req_pee1 {
690*4882a593Smuzhiyun				nvidia,pins = "clk3_req_pee1";
691*4882a593Smuzhiyun				nvidia,function = "rsvd4";
692*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
693*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
694*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
695*4882a593Smuzhiyun			};
696*4882a593Smuzhiyun			pu4 {
697*4882a593Smuzhiyun				nvidia,pins = "pu4";
698*4882a593Smuzhiyun				nvidia,function = "displayb";
699*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
700*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
701*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
702*4882a593Smuzhiyun			};
703*4882a593Smuzhiyun			pu5 {
704*4882a593Smuzhiyun				nvidia,pins = "pu5",
705*4882a593Smuzhiyun						"pu6";
706*4882a593Smuzhiyun				nvidia,function = "displayb";
707*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
708*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
709*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
710*4882a593Smuzhiyun			};
711*4882a593Smuzhiyun			hdmi_int_pn7 {
712*4882a593Smuzhiyun				nvidia,pins = "hdmi_int_pn7";
713*4882a593Smuzhiyun				nvidia,function = "rsvd1";
714*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
715*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
716*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
717*4882a593Smuzhiyun			};
718*4882a593Smuzhiyun			clk1_req_pee2 {
719*4882a593Smuzhiyun				nvidia,pins = "clk1_req_pee2",
720*4882a593Smuzhiyun						"usb_vbus_en1_pn5";
721*4882a593Smuzhiyun				nvidia,function = "rsvd4";
722*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
723*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
724*4882a593Smuzhiyun				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
725*4882a593Smuzhiyun			};
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun			drive_sdio1 {
728*4882a593Smuzhiyun				nvidia,pins = "drive_sdio1";
729*4882a593Smuzhiyun				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
730*4882a593Smuzhiyun				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
731*4882a593Smuzhiyun				nvidia,pull-down-strength = <36>;
732*4882a593Smuzhiyun				nvidia,pull-up-strength = <20>;
733*4882a593Smuzhiyun				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
734*4882a593Smuzhiyun				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
735*4882a593Smuzhiyun			};
736*4882a593Smuzhiyun			drive_sdio3 {
737*4882a593Smuzhiyun				nvidia,pins = "drive_sdio3";
738*4882a593Smuzhiyun				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
739*4882a593Smuzhiyun				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
740*4882a593Smuzhiyun				nvidia,pull-down-strength = <22>;
741*4882a593Smuzhiyun				nvidia,pull-up-strength = <36>;
742*4882a593Smuzhiyun				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
743*4882a593Smuzhiyun				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
744*4882a593Smuzhiyun			};
745*4882a593Smuzhiyun			drive_gma {
746*4882a593Smuzhiyun				nvidia,pins = "drive_gma";
747*4882a593Smuzhiyun				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
748*4882a593Smuzhiyun				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
749*4882a593Smuzhiyun				nvidia,pull-down-strength = <2>;
750*4882a593Smuzhiyun				nvidia,pull-up-strength = <1>;
751*4882a593Smuzhiyun				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
752*4882a593Smuzhiyun				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
753*4882a593Smuzhiyun			};
754*4882a593Smuzhiyun		};
755*4882a593Smuzhiyun	};
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun	serial@70006300 {
758*4882a593Smuzhiyun		status = "okay";
759*4882a593Smuzhiyun	};
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun	pwm@7000a000 {
762*4882a593Smuzhiyun		status = "okay";
763*4882a593Smuzhiyun	};
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun	i2c@7000c000 {
766*4882a593Smuzhiyun		status = "okay";
767*4882a593Smuzhiyun		clock-frequency = <100000>;
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun		battery: smart-battery@b {
770*4882a593Smuzhiyun			compatible = "ti,bq20z45", "sbs,sbs-battery";
771*4882a593Smuzhiyun			reg = <0xb>;
772*4882a593Smuzhiyun			sbs,i2c-retry-count = <2>;
773*4882a593Smuzhiyun			sbs,poll-retry-count = <100>;
774*4882a593Smuzhiyun			power-supplies = <&charger>;
775*4882a593Smuzhiyun		};
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun		rt5640: rt5640@1c {
778*4882a593Smuzhiyun			compatible = "realtek,rt5640";
779*4882a593Smuzhiyun			reg = <0x1c>;
780*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
781*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
782*4882a593Smuzhiyun			realtek,ldo1-en-gpios =
783*4882a593Smuzhiyun				<&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
784*4882a593Smuzhiyun		};
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun		temperature-sensor@4c {
787*4882a593Smuzhiyun			compatible = "onnn,nct1008";
788*4882a593Smuzhiyun			reg = <0x4c>;
789*4882a593Smuzhiyun			vcc-supply = <&palmas_ldo6_reg>;
790*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
791*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>;
792*4882a593Smuzhiyun		};
793*4882a593Smuzhiyun	};
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun	hdmi_ddc: i2c@7000c700 {
796*4882a593Smuzhiyun		status = "okay";
797*4882a593Smuzhiyun	};
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun	i2c@7000d000 {
800*4882a593Smuzhiyun		status = "okay";
801*4882a593Smuzhiyun		clock-frequency = <400000>;
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun		tps51632@43 {
804*4882a593Smuzhiyun			compatible = "ti,tps51632";
805*4882a593Smuzhiyun			reg = <0x43>;
806*4882a593Smuzhiyun			regulator-name = "vdd-cpu";
807*4882a593Smuzhiyun			regulator-min-microvolt = <500000>;
808*4882a593Smuzhiyun			regulator-max-microvolt = <1520000>;
809*4882a593Smuzhiyun			regulator-boot-on;
810*4882a593Smuzhiyun			regulator-always-on;
811*4882a593Smuzhiyun		};
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun		tps65090@48 {
814*4882a593Smuzhiyun			compatible = "ti,tps65090";
815*4882a593Smuzhiyun			reg = <0x48>;
816*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
817*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun			vsys1-supply = <&vdd_ac_bat_reg>;
820*4882a593Smuzhiyun			vsys2-supply = <&vdd_ac_bat_reg>;
821*4882a593Smuzhiyun			vsys3-supply = <&vdd_ac_bat_reg>;
822*4882a593Smuzhiyun			infet1-supply = <&vdd_ac_bat_reg>;
823*4882a593Smuzhiyun			infet2-supply = <&vdd_ac_bat_reg>;
824*4882a593Smuzhiyun			infet3-supply = <&tps65090_dcdc2_reg>;
825*4882a593Smuzhiyun			infet4-supply = <&tps65090_dcdc2_reg>;
826*4882a593Smuzhiyun			infet5-supply = <&tps65090_dcdc2_reg>;
827*4882a593Smuzhiyun			infet6-supply = <&tps65090_dcdc2_reg>;
828*4882a593Smuzhiyun			infet7-supply = <&tps65090_dcdc2_reg>;
829*4882a593Smuzhiyun			vsys-l1-supply = <&vdd_ac_bat_reg>;
830*4882a593Smuzhiyun			vsys-l2-supply = <&vdd_ac_bat_reg>;
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun			charger: charger {
833*4882a593Smuzhiyun				compatible = "ti,tps65090-charger";
834*4882a593Smuzhiyun				ti,enable-low-current-chrg;
835*4882a593Smuzhiyun			};
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun			regulators {
838*4882a593Smuzhiyun				tps65090_dcdc1_reg: dcdc1 {
839*4882a593Smuzhiyun					regulator-name = "vdd-sys-5v0";
840*4882a593Smuzhiyun					regulator-always-on;
841*4882a593Smuzhiyun					regulator-boot-on;
842*4882a593Smuzhiyun				};
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun				tps65090_dcdc2_reg: dcdc2 {
845*4882a593Smuzhiyun					regulator-name = "vdd-sys-3v3";
846*4882a593Smuzhiyun					regulator-always-on;
847*4882a593Smuzhiyun					regulator-boot-on;
848*4882a593Smuzhiyun				};
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun				tps65090_dcdc3_reg: dcdc3 {
851*4882a593Smuzhiyun					regulator-name = "vdd-ao";
852*4882a593Smuzhiyun					regulator-always-on;
853*4882a593Smuzhiyun					regulator-boot-on;
854*4882a593Smuzhiyun				};
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun				vdd_bl_reg: fet1 {
857*4882a593Smuzhiyun					regulator-name = "vdd-lcd-bl";
858*4882a593Smuzhiyun				};
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun				fet3 {
861*4882a593Smuzhiyun					regulator-name = "vdd-modem-3v3";
862*4882a593Smuzhiyun				};
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun				avdd_lcd_reg: fet4 {
865*4882a593Smuzhiyun					regulator-name = "avdd-lcd";
866*4882a593Smuzhiyun				};
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun				fet5 {
869*4882a593Smuzhiyun					regulator-name = "vdd-lvds";
870*4882a593Smuzhiyun				};
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun				fet6 {
873*4882a593Smuzhiyun					regulator-name = "vdd-sd-slot";
874*4882a593Smuzhiyun					regulator-always-on;
875*4882a593Smuzhiyun					regulator-boot-on;
876*4882a593Smuzhiyun				};
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun				fet7 {
879*4882a593Smuzhiyun					regulator-name = "vdd-com-3v3";
880*4882a593Smuzhiyun				};
881*4882a593Smuzhiyun
882*4882a593Smuzhiyun				ldo1 {
883*4882a593Smuzhiyun					regulator-name = "vdd-sby-5v0";
884*4882a593Smuzhiyun					regulator-always-on;
885*4882a593Smuzhiyun					regulator-boot-on;
886*4882a593Smuzhiyun				};
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun				ldo2 {
889*4882a593Smuzhiyun					regulator-name = "vdd-sby-3v3";
890*4882a593Smuzhiyun					regulator-always-on;
891*4882a593Smuzhiyun					regulator-boot-on;
892*4882a593Smuzhiyun				};
893*4882a593Smuzhiyun			};
894*4882a593Smuzhiyun		};
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun		palmas: tps65913@58 {
897*4882a593Smuzhiyun			compatible = "ti,palmas";
898*4882a593Smuzhiyun			reg = <0x58>;
899*4882a593Smuzhiyun			interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun			#interrupt-cells = <2>;
902*4882a593Smuzhiyun			interrupt-controller;
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun			ti,system-power-controller;
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun			palmas_gpio: gpio {
907*4882a593Smuzhiyun				compatible = "ti,palmas-gpio";
908*4882a593Smuzhiyun				gpio-controller;
909*4882a593Smuzhiyun				#gpio-cells = <2>;
910*4882a593Smuzhiyun			};
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun			pmic {
913*4882a593Smuzhiyun				compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
914*4882a593Smuzhiyun				smps1-in-supply = <&tps65090_dcdc3_reg>;
915*4882a593Smuzhiyun				smps3-in-supply = <&tps65090_dcdc3_reg>;
916*4882a593Smuzhiyun				smps4-in-supply = <&tps65090_dcdc2_reg>;
917*4882a593Smuzhiyun				smps7-in-supply = <&tps65090_dcdc2_reg>;
918*4882a593Smuzhiyun				smps8-in-supply = <&tps65090_dcdc2_reg>;
919*4882a593Smuzhiyun				smps9-in-supply = <&tps65090_dcdc2_reg>;
920*4882a593Smuzhiyun				ldo1-in-supply = <&tps65090_dcdc2_reg>;
921*4882a593Smuzhiyun				ldo2-in-supply = <&tps65090_dcdc2_reg>;
922*4882a593Smuzhiyun				ldo3-in-supply = <&palmas_smps3_reg>;
923*4882a593Smuzhiyun				ldo4-in-supply = <&tps65090_dcdc2_reg>;
924*4882a593Smuzhiyun				ldo5-in-supply = <&vdd_ac_bat_reg>;
925*4882a593Smuzhiyun				ldo6-in-supply = <&tps65090_dcdc2_reg>;
926*4882a593Smuzhiyun				ldo7-in-supply = <&tps65090_dcdc2_reg>;
927*4882a593Smuzhiyun				ldo8-in-supply = <&tps65090_dcdc3_reg>;
928*4882a593Smuzhiyun				ldo9-in-supply = <&palmas_smps9_reg>;
929*4882a593Smuzhiyun				ldoln-in-supply = <&tps65090_dcdc1_reg>;
930*4882a593Smuzhiyun				ldousb-in-supply = <&tps65090_dcdc1_reg>;
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun				regulators {
933*4882a593Smuzhiyun					smps12 {
934*4882a593Smuzhiyun						regulator-name = "vddio-ddr";
935*4882a593Smuzhiyun						regulator-min-microvolt = <1350000>;
936*4882a593Smuzhiyun						regulator-max-microvolt = <1350000>;
937*4882a593Smuzhiyun						regulator-always-on;
938*4882a593Smuzhiyun						regulator-boot-on;
939*4882a593Smuzhiyun					};
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun					palmas_smps3_reg: smps3 {
942*4882a593Smuzhiyun						regulator-name = "vddio-1v8";
943*4882a593Smuzhiyun						regulator-min-microvolt = <1800000>;
944*4882a593Smuzhiyun						regulator-max-microvolt = <1800000>;
945*4882a593Smuzhiyun						regulator-always-on;
946*4882a593Smuzhiyun						regulator-boot-on;
947*4882a593Smuzhiyun					};
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun					smps45 {
950*4882a593Smuzhiyun						regulator-name = "vdd-core";
951*4882a593Smuzhiyun						regulator-min-microvolt = <900000>;
952*4882a593Smuzhiyun						regulator-max-microvolt = <1400000>;
953*4882a593Smuzhiyun						regulator-always-on;
954*4882a593Smuzhiyun						regulator-boot-on;
955*4882a593Smuzhiyun					};
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun					smps457 {
958*4882a593Smuzhiyun						regulator-name = "vdd-core";
959*4882a593Smuzhiyun						regulator-min-microvolt = <900000>;
960*4882a593Smuzhiyun						regulator-max-microvolt = <1400000>;
961*4882a593Smuzhiyun						regulator-always-on;
962*4882a593Smuzhiyun						regulator-boot-on;
963*4882a593Smuzhiyun					};
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun					smps8 {
966*4882a593Smuzhiyun						regulator-name = "avdd-pll";
967*4882a593Smuzhiyun						regulator-min-microvolt = <1050000>;
968*4882a593Smuzhiyun						regulator-max-microvolt = <1050000>;
969*4882a593Smuzhiyun						regulator-always-on;
970*4882a593Smuzhiyun						regulator-boot-on;
971*4882a593Smuzhiyun					};
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun					palmas_smps9_reg: smps9 {
974*4882a593Smuzhiyun						regulator-name = "sdhci-vdd-sd-slot";
975*4882a593Smuzhiyun						regulator-min-microvolt = <2800000>;
976*4882a593Smuzhiyun						regulator-max-microvolt = <2800000>;
977*4882a593Smuzhiyun						regulator-always-on;
978*4882a593Smuzhiyun					};
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun					ldo1 {
981*4882a593Smuzhiyun						regulator-name = "avdd-cam1";
982*4882a593Smuzhiyun						regulator-min-microvolt = <2800000>;
983*4882a593Smuzhiyun						regulator-max-microvolt = <2800000>;
984*4882a593Smuzhiyun					};
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun					ldo2 {
987*4882a593Smuzhiyun						regulator-name = "avdd-cam2";
988*4882a593Smuzhiyun						regulator-min-microvolt = <2800000>;
989*4882a593Smuzhiyun						regulator-max-microvolt = <2800000>;
990*4882a593Smuzhiyun					};
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun					avdd_1v2_reg: ldo3 {
993*4882a593Smuzhiyun						regulator-name = "avdd-dsi-csi";
994*4882a593Smuzhiyun						regulator-min-microvolt = <1200000>;
995*4882a593Smuzhiyun						regulator-max-microvolt = <1200000>;
996*4882a593Smuzhiyun					};
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun					ldo4 {
999*4882a593Smuzhiyun						regulator-name = "vpp-fuse";
1000*4882a593Smuzhiyun						regulator-min-microvolt = <1800000>;
1001*4882a593Smuzhiyun						regulator-max-microvolt = <1800000>;
1002*4882a593Smuzhiyun					};
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun					palmas_ldo6_reg: ldo6 {
1005*4882a593Smuzhiyun						regulator-name = "vdd-sensor-2v85";
1006*4882a593Smuzhiyun						regulator-min-microvolt = <2850000>;
1007*4882a593Smuzhiyun						regulator-max-microvolt = <2850000>;
1008*4882a593Smuzhiyun					};
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun					ldo7 {
1011*4882a593Smuzhiyun						regulator-name = "vdd-af-cam1";
1012*4882a593Smuzhiyun						regulator-min-microvolt = <2800000>;
1013*4882a593Smuzhiyun						regulator-max-microvolt = <2800000>;
1014*4882a593Smuzhiyun					};
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun					ldo8 {
1017*4882a593Smuzhiyun						regulator-name = "vdd-rtc";
1018*4882a593Smuzhiyun						regulator-min-microvolt = <900000>;
1019*4882a593Smuzhiyun						regulator-max-microvolt = <900000>;
1020*4882a593Smuzhiyun						regulator-always-on;
1021*4882a593Smuzhiyun						regulator-boot-on;
1022*4882a593Smuzhiyun						ti,enable-ldo8-tracking;
1023*4882a593Smuzhiyun					};
1024*4882a593Smuzhiyun
1025*4882a593Smuzhiyun					ldo9 {
1026*4882a593Smuzhiyun						regulator-name = "vddio-sdmmc-2";
1027*4882a593Smuzhiyun						regulator-min-microvolt = <1800000>;
1028*4882a593Smuzhiyun						regulator-max-microvolt = <3300000>;
1029*4882a593Smuzhiyun						regulator-always-on;
1030*4882a593Smuzhiyun						regulator-boot-on;
1031*4882a593Smuzhiyun					};
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun					ldoln {
1034*4882a593Smuzhiyun						regulator-name = "hvdd-usb";
1035*4882a593Smuzhiyun						regulator-min-microvolt = <3300000>;
1036*4882a593Smuzhiyun						regulator-max-microvolt = <3300000>;
1037*4882a593Smuzhiyun					};
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun					ldousb {
1040*4882a593Smuzhiyun						regulator-name = "avdd-usb";
1041*4882a593Smuzhiyun						regulator-min-microvolt = <3300000>;
1042*4882a593Smuzhiyun						regulator-max-microvolt = <3300000>;
1043*4882a593Smuzhiyun						regulator-always-on;
1044*4882a593Smuzhiyun						regulator-boot-on;
1045*4882a593Smuzhiyun					};
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun					regen1 {
1048*4882a593Smuzhiyun						regulator-name = "rail-3v3";
1049*4882a593Smuzhiyun						regulator-max-microvolt = <3300000>;
1050*4882a593Smuzhiyun						regulator-always-on;
1051*4882a593Smuzhiyun						regulator-boot-on;
1052*4882a593Smuzhiyun					};
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun					regen2 {
1055*4882a593Smuzhiyun						regulator-name = "rail-5v0";
1056*4882a593Smuzhiyun						regulator-max-microvolt = <5000000>;
1057*4882a593Smuzhiyun						regulator-always-on;
1058*4882a593Smuzhiyun						regulator-boot-on;
1059*4882a593Smuzhiyun					};
1060*4882a593Smuzhiyun				};
1061*4882a593Smuzhiyun			};
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun			rtc {
1064*4882a593Smuzhiyun				compatible = "ti,palmas-rtc";
1065*4882a593Smuzhiyun				interrupt-parent = <&palmas>;
1066*4882a593Smuzhiyun				interrupts = <8 0>;
1067*4882a593Smuzhiyun			};
1068*4882a593Smuzhiyun
1069*4882a593Smuzhiyun			pinmux {
1070*4882a593Smuzhiyun				compatible = "ti,tps65913-pinctrl";
1071*4882a593Smuzhiyun				pinctrl-names = "default";
1072*4882a593Smuzhiyun				pinctrl-0 = <&palmas_default>;
1073*4882a593Smuzhiyun
1074*4882a593Smuzhiyun				palmas_default: pinmux {
1075*4882a593Smuzhiyun					pin_gpio6 {
1076*4882a593Smuzhiyun						pins = "gpio6";
1077*4882a593Smuzhiyun						function = "gpio";
1078*4882a593Smuzhiyun					};
1079*4882a593Smuzhiyun				};
1080*4882a593Smuzhiyun			};
1081*4882a593Smuzhiyun		};
1082*4882a593Smuzhiyun	};
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun	spi@7000da00 {
1085*4882a593Smuzhiyun		status = "okay";
1086*4882a593Smuzhiyun		spi-max-frequency = <25000000>;
1087*4882a593Smuzhiyun		spi-flash@0 {
1088*4882a593Smuzhiyun			compatible = "winbond,w25q32dw", "jedec,spi-nor";
1089*4882a593Smuzhiyun			reg = <0>;
1090*4882a593Smuzhiyun			spi-max-frequency = <20000000>;
1091*4882a593Smuzhiyun		};
1092*4882a593Smuzhiyun	};
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun	pmc@7000e400 {
1095*4882a593Smuzhiyun		nvidia,invert-interrupt;
1096*4882a593Smuzhiyun		nvidia,suspend-mode = <1>;
1097*4882a593Smuzhiyun		nvidia,cpu-pwr-good-time = <500>;
1098*4882a593Smuzhiyun		nvidia,cpu-pwr-off-time = <300>;
1099*4882a593Smuzhiyun		nvidia,core-pwr-good-time = <641 3845>;
1100*4882a593Smuzhiyun		nvidia,core-pwr-off-time = <61036>;
1101*4882a593Smuzhiyun		nvidia,core-power-req-active-high;
1102*4882a593Smuzhiyun		nvidia,sys-clock-req-active-high;
1103*4882a593Smuzhiyun	};
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun	ahub@70080000 {
1106*4882a593Smuzhiyun		i2s@70080400 {
1107*4882a593Smuzhiyun			status = "okay";
1108*4882a593Smuzhiyun		};
1109*4882a593Smuzhiyun	};
1110*4882a593Smuzhiyun
1111*4882a593Smuzhiyun	mmc@78000400 {
1112*4882a593Smuzhiyun		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
1113*4882a593Smuzhiyun		wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
1114*4882a593Smuzhiyun		bus-width = <4>;
1115*4882a593Smuzhiyun		status = "okay";
1116*4882a593Smuzhiyun	};
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun	mmc@78000600 {
1119*4882a593Smuzhiyun		bus-width = <8>;
1120*4882a593Smuzhiyun		status = "okay";
1121*4882a593Smuzhiyun		non-removable;
1122*4882a593Smuzhiyun	};
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun	usb@7d000000 {
1125*4882a593Smuzhiyun		compatible = "nvidia,tegra114-udc";
1126*4882a593Smuzhiyun		status = "okay";
1127*4882a593Smuzhiyun		dr_mode = "peripheral";
1128*4882a593Smuzhiyun	};
1129*4882a593Smuzhiyun
1130*4882a593Smuzhiyun	usb-phy@7d000000 {
1131*4882a593Smuzhiyun		status = "okay";
1132*4882a593Smuzhiyun	};
1133*4882a593Smuzhiyun
1134*4882a593Smuzhiyun	usb@7d008000 {
1135*4882a593Smuzhiyun		status = "okay";
1136*4882a593Smuzhiyun	};
1137*4882a593Smuzhiyun
1138*4882a593Smuzhiyun	usb-phy@7d008000 {
1139*4882a593Smuzhiyun		status = "okay";
1140*4882a593Smuzhiyun		vbus-supply = <&usb3_vbus_reg>;
1141*4882a593Smuzhiyun	};
1142*4882a593Smuzhiyun
1143*4882a593Smuzhiyun	backlight: backlight {
1144*4882a593Smuzhiyun		compatible = "pwm-backlight";
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun		enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1147*4882a593Smuzhiyun		power-supply = <&vdd_bl_reg>;
1148*4882a593Smuzhiyun		pwms = <&pwm 1 1000000>;
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
1151*4882a593Smuzhiyun		default-brightness-level = <6>;
1152*4882a593Smuzhiyun	};
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun	clk32k_in: clock@0 {
1155*4882a593Smuzhiyun		compatible = "fixed-clock";
1156*4882a593Smuzhiyun		clock-frequency = <32768>;
1157*4882a593Smuzhiyun		#clock-cells = <0>;
1158*4882a593Smuzhiyun	};
1159*4882a593Smuzhiyun
1160*4882a593Smuzhiyun	gpio-keys {
1161*4882a593Smuzhiyun		compatible = "gpio-keys";
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun		home {
1164*4882a593Smuzhiyun			label = "Home";
1165*4882a593Smuzhiyun			gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
1166*4882a593Smuzhiyun			linux,code = <KEY_HOME>;
1167*4882a593Smuzhiyun		};
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun		power {
1170*4882a593Smuzhiyun			label = "Power";
1171*4882a593Smuzhiyun			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
1172*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
1173*4882a593Smuzhiyun			wakeup-source;
1174*4882a593Smuzhiyun		};
1175*4882a593Smuzhiyun
1176*4882a593Smuzhiyun		volume_down {
1177*4882a593Smuzhiyun			label = "Volume Down";
1178*4882a593Smuzhiyun			gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
1179*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
1180*4882a593Smuzhiyun		};
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun		volume_up {
1183*4882a593Smuzhiyun			label = "Volume Up";
1184*4882a593Smuzhiyun			gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
1185*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
1186*4882a593Smuzhiyun		};
1187*4882a593Smuzhiyun	};
1188*4882a593Smuzhiyun
1189*4882a593Smuzhiyun	vdd_ac_bat_reg: regulator@0 {
1190*4882a593Smuzhiyun		compatible = "regulator-fixed";
1191*4882a593Smuzhiyun		regulator-name = "vdd_ac_bat";
1192*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
1193*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
1194*4882a593Smuzhiyun		regulator-always-on;
1195*4882a593Smuzhiyun	};
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun	dvdd_ts_reg: regulator@1 {
1198*4882a593Smuzhiyun		compatible = "regulator-fixed";
1199*4882a593Smuzhiyun		regulator-name = "dvdd_ts";
1200*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
1201*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
1202*4882a593Smuzhiyun		enable-active-high;
1203*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
1204*4882a593Smuzhiyun	};
1205*4882a593Smuzhiyun
1206*4882a593Smuzhiyun	usb1_vbus_reg: regulator@3 {
1207*4882a593Smuzhiyun		compatible = "regulator-fixed";
1208*4882a593Smuzhiyun		regulator-name = "usb1_vbus";
1209*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
1210*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
1211*4882a593Smuzhiyun		enable-active-high;
1212*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
1213*4882a593Smuzhiyun		gpio-open-drain;
1214*4882a593Smuzhiyun		vin-supply = <&tps65090_dcdc1_reg>;
1215*4882a593Smuzhiyun	};
1216*4882a593Smuzhiyun
1217*4882a593Smuzhiyun	usb3_vbus_reg: regulator@4 {
1218*4882a593Smuzhiyun		compatible = "regulator-fixed";
1219*4882a593Smuzhiyun		regulator-name = "usb2_vbus";
1220*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
1221*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
1222*4882a593Smuzhiyun		enable-active-high;
1223*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
1224*4882a593Smuzhiyun		gpio-open-drain;
1225*4882a593Smuzhiyun		vin-supply = <&tps65090_dcdc1_reg>;
1226*4882a593Smuzhiyun	};
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun	vdd_hdmi_reg: regulator@5 {
1229*4882a593Smuzhiyun		compatible = "regulator-fixed";
1230*4882a593Smuzhiyun		regulator-name = "vdd_hdmi_5v0";
1231*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
1232*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
1233*4882a593Smuzhiyun		vin-supply = <&tps65090_dcdc1_reg>;
1234*4882a593Smuzhiyun	};
1235*4882a593Smuzhiyun
1236*4882a593Smuzhiyun	vdd_cam_1v8_reg: regulator@6 {
1237*4882a593Smuzhiyun		compatible = "regulator-fixed";
1238*4882a593Smuzhiyun		regulator-name = "vdd_cam_1v8_reg";
1239*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
1240*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
1241*4882a593Smuzhiyun		enable-active-high;
1242*4882a593Smuzhiyun		gpio = <&palmas_gpio 6 0>;
1243*4882a593Smuzhiyun	};
1244*4882a593Smuzhiyun
1245*4882a593Smuzhiyun	vdd_5v0_hdmi: regulator@7 {
1246*4882a593Smuzhiyun		compatible = "regulator-fixed";
1247*4882a593Smuzhiyun		regulator-name = "VDD_5V0_HDMI_CON";
1248*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
1249*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
1250*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
1251*4882a593Smuzhiyun		enable-active-high;
1252*4882a593Smuzhiyun		vin-supply = <&tps65090_dcdc1_reg>;
1253*4882a593Smuzhiyun	};
1254*4882a593Smuzhiyun
1255*4882a593Smuzhiyun	sound {
1256*4882a593Smuzhiyun		compatible = "nvidia,tegra-audio-rt5640-dalmore",
1257*4882a593Smuzhiyun			     "nvidia,tegra-audio-rt5640";
1258*4882a593Smuzhiyun		nvidia,model = "NVIDIA Tegra Dalmore";
1259*4882a593Smuzhiyun
1260*4882a593Smuzhiyun		nvidia,audio-routing =
1261*4882a593Smuzhiyun			"Headphones", "HPOR",
1262*4882a593Smuzhiyun			"Headphones", "HPOL",
1263*4882a593Smuzhiyun			"Speakers", "SPORP",
1264*4882a593Smuzhiyun			"Speakers", "SPORN",
1265*4882a593Smuzhiyun			"Speakers", "SPOLP",
1266*4882a593Smuzhiyun			"Speakers", "SPOLN",
1267*4882a593Smuzhiyun			"Mic Jack", "MICBIAS1",
1268*4882a593Smuzhiyun			"IN2P", "Mic Jack";
1269*4882a593Smuzhiyun
1270*4882a593Smuzhiyun		nvidia,i2s-controller = <&tegra_i2s1>;
1271*4882a593Smuzhiyun		nvidia,audio-codec = <&rt5640>;
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun		clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
1276*4882a593Smuzhiyun			 <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
1277*4882a593Smuzhiyun			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1278*4882a593Smuzhiyun		clock-names = "pll_a", "pll_a_out0", "mclk";
1279*4882a593Smuzhiyun
1280*4882a593Smuzhiyun		assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>,
1281*4882a593Smuzhiyun				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1282*4882a593Smuzhiyun
1283*4882a593Smuzhiyun		assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
1284*4882a593Smuzhiyun					 <&tegra_car TEGRA114_CLK_EXTERN1>;
1285*4882a593Smuzhiyun	};
1286*4882a593Smuzhiyun};
1287