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/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-width = <1>;
[all …]
H A Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
57 ethernet@e0000 {
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
62 ethernet@e2000 {
63 phy-handle = <&phy_sgmii_s7_1d>;
[all …]
H A Dt2080qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
65 ethernet@e0000 {
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
70 ethernet@e2000 {
71 phy-handle = <&phy_sgmii_s3_1f>;
[all …]
H A Dt4240rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
[all …]
H A Dp5040ds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "p5040si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
74 reserved-memory {
75 #address-cells = <2>;
76 #size-cells = <2>;
79 bman_fbpr: bman-fbpr {
83 qman_fqd: qman-fqd {
[all …]
H A Dt2080rdb.dts2 * T2080PCIe-RDB Board Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
59 ethernet@e0000 {
60 phy-handle = <&xg_aq1202_phy3>;
61 phy-connection-type = "xgmii";
64 ethernet@e2000 {
[all …]
H A Dp4080ds.dts4 * Copyright 2009 - 2015 Freescale Semiconductor Inc.
35 /include/ "p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
[all …]
H A Dt1040rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t104xsi-pre.dtsi"
48 ethernet@e0000 {
49 fixed-link = <0 1 1000 0 0>;
50 phy-connection-type = "sgmii";
53 ethernet@e2000 {
54 fixed-link = <1 1 1000 0 0>;
55 phy-connection-type = "sgmii";
58 ethernet@e4000 {
59 phy-handle = <&phy_sgmii_2>;
[all …]
H A Dt104xqds.dtsi4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
37 #address-cells = <2>;
38 #size-cells = <2>;
39 interrupt-parent = <&mpic>;
68 reserved-memory {
69 #address-cells = <2>;
70 #size-cells = <2>;
73 bman_fbpr: bman-fbpr {
77 qman_fqd: qman-fqd {
81 qman_pfdr: qman-pfdr {
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Generic Binding
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
[all …]
H A Dhisilicon-hip04-net.txt1 Hisilicon hip04 Ethernet Controller
3 * Ethernet controller node
6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
14 - phy-mode: see ethernet.txt [1].
17 - phy-handle: see ethernet.txt [1].
19 [1] Documentation/devicetree/bindings/net/ethernet.txt
22 * Ethernet ppe node:
[all …]
H A Dfsl-enetc.txt1 * ENETC ethernet device tree bindings
9 - reg : Specifies PCIe Device Number and Function
12 - compatible : Should be "fsl,enetc".
14 1. The ENETC external port is connected to a MDIO configurable phy
18 In this case, the ENETC node should include a "mdio" sub-node
19 that in turn should contain the "ethernet-phy" node describing the
20 external phy. Below properties are required, their bindings
21 already defined in Documentation/devicetree/bindings/net/ethernet.txt or
22 Documentation/devicetree/bindings/net/phy.txt.
26 - phy-handle : Phandle to a PHY on the MDIO bus.
[all …]
H A Dsnps,dwc-qos-ethernet.txt1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
6 This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
[all …]
H A Dsocionext-netsec.txt1 * Socionext NetSec Ethernet Controller IP
4 - compatible: Should be "socionext,synquacer-netsec"
5 - reg: Address and length of the control register area, followed by the
8 - interrupts: Should contain ethernet controller interrupt
9 - clocks: phandle to the PHY reference clock
10 - clock-names: Should be "phy_ref_clk"
11 - phy-mode: See ethernet.txt file in the same directory
12 - phy-handle: See ethernet.txt in the same directory.
14 - mdio device tree subnode: When the Netsec has a phy connected to its local
18 - #address-cells: Must be <1>.
[all …]
H A Dcortina,gemini-ethernet.txt1 Cortina Systems Gemini Ethernet Controller
4 This ethernet controller is found in the Gemini SoC family:
9 - compatible: must be "cortina,gemini-ethernet"
10 - reg: must contain the global registers and the V-bit and A-bit
12 - syscon: a phandle to the system controller
13 - #address-cells: must be specified, must be <1>
14 - #size-cells: must be specified, must be <1>
15 - ranges: should be state like this giving a 1:1 address translation
18 The subnodes represents the two ethernet ports in this device.
23 - port0: contains the resources for ethernet port 0
[all …]
H A Dxilinx_axienet.txt1 XILINX AXI ETHERNET Device Tree Bindings
2 --------------------------------------------------------
4 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
5 provides connectivity to an external ethernet PHY supporting different
15 For more details about mdio please refer phy.txt file in the same directory.
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/phy/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # PHY Layer Configuration
12 PHYlink models the link between the PHY and MAC, allowing fixed
17 tristate "PHY Device support and infrastructure"
22 Ethernet controllers are usually attached to PHY
24 managing PHY devices.
35 Adds support for a set of LED trigger events per-PHY. Link
38 supported by the PHY and also a one common "link" trigger as a
39 logical-or of all the link speed ones.
41 <mii bus id>:<phy>:<speed>
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1043a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
26 stdout-path = "serial0:115200n8";
35 shunt-resistor = <1000>;
57 #address-cells = <2>;
58 #size-cells = <1>;
[all …]
H A Dfsl-ls1046a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
10 /dts-v1/;
12 #include "fsl-ls1046a.dtsi"
16 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
26 stdout-path = "serial0:115200n8";
39 mmc-hs200-1_8v;
40 sd-uhs-sdr104;
41 sd-uhs-sdr50;
42 sd-uhs-sdr25;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dorion5x-netgear-wnr854t.dts9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include "orion5x-mv88f5181.dtsi"
16 model = "Netgear WNR854-t";
17 compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
29 stdout-path = "serial0:115200n8";
38 gpio-keys {
39 compatible = "gpio-keys";
40 pinctrl-0 = <&pmx_reset_button>;
[all …]
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
3 This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)
10 - compatible: One of:
11 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
13 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
15 - "snps,dwc-qos-ethernet-4.10"
17 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
19 - reg: Address and length of the register set for the device
20 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
[all …]
H A Daltera_tse.txt1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
6 - reg: Address and length of the register set for the device. It contains
7 the information of registers in the same order as described by reg-names
8 - reg-names: Should contain the reg names
16 - interrupts: Should contain the TSE interrupts and it's mode.
17 - interrupt-names: Should contain the interrupt names
20 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
21 - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/phy/
H A DKconfig3 bool "Bit-banged ethernet MII management channel support"
9 bool "Ethernet PHY (physical media interface) support"
11 Enable Ethernet PHY (physical media interface) support.
16 bool "Marvel MV88E61xx Ethernet switch PHY support."
24 hex "Bitmask of PHY Ports"
32 bool "Generic 10G PHY support"
35 bool "Aquantia Ethernet PHYs support"
38 bool "Atheros Ethernet PHYs support"
41 bool "Broadcom Ethernet PHYs support"
44 bool "Cortina Ethernet PHYs support"
[all …]
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/cavium-octeon/
H A Docteon_3xxx.dts1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
29 marvell,reg-init =
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/
H A DKconfig1 source "drivers/net/phy/Kconfig"
4 bool "Enable Driver Model for Ethernet drivers"
7 Enable driver model for Ethernet.
20 stand-alone devices. Useful in particular for systems that support
21 DM_ETH and have a stand-alone MDIO hardware block shared by multiple
22 Ethernet interfaces.
23 This is currently implemented in net/mdio-uclass.c
27 bool "Enable Driver Model for Ethernet Generic PHY drivers"
30 Enable driver model for Ethernet Generic PHY .
45 bool "Enable GbE PHY status parsing and configuration"
[all …]

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