1*4882a593SmuzhiyunXILINX AXI ETHERNET Device Tree Bindings 2*4882a593Smuzhiyun-------------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunAlso called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core 5*4882a593Smuzhiyunprovides connectivity to an external ethernet PHY supporting different 6*4882a593Smuzhiyuninterfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two 7*4882a593Smuzhiyunsegments of memory for buffering TX and RX, as well as the capability of 8*4882a593Smuzhiyunoffloading TX/RX checksum calculation off the processor. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunManagement configuration is done through the AXI interface, while payload is 11*4882a593Smuzhiyunsent and received through means of an AXI DMA controller. This driver 12*4882a593Smuzhiyunincludes the DMA driver code, so this driver is incompatible with AXI DMA 13*4882a593Smuzhiyundriver. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunFor more details about mdio please refer phy.txt file in the same directory. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunRequired properties: 18*4882a593Smuzhiyun- compatible : Must be one of "xlnx,axi-ethernet-1.00.a", 19*4882a593Smuzhiyun "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a" 20*4882a593Smuzhiyun- reg : Address and length of the IO space, as well as the address 21*4882a593Smuzhiyun and length of the AXI DMA controller IO space, unless 22*4882a593Smuzhiyun axistream-connected is specified, in which case the reg 23*4882a593Smuzhiyun attribute of the node referenced by it is used. 24*4882a593Smuzhiyun- interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA, 25*4882a593Smuzhiyun and optionally Ethernet core. If axistream-connected is 26*4882a593Smuzhiyun specified, the TX/RX DMA interrupts should be on that node 27*4882a593Smuzhiyun instead, and only the Ethernet core interrupt is optionally 28*4882a593Smuzhiyun specified here. 29*4882a593Smuzhiyun- phy-handle : Should point to the external phy device. 30*4882a593Smuzhiyun See ethernet.txt file in the same directory. 31*4882a593Smuzhiyun- xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunOptional properties: 34*4882a593Smuzhiyun- phy-mode : See ethernet.txt 35*4882a593Smuzhiyun- xlnx,phy-type : Deprecated, do not use, but still accepted in preference 36*4882a593Smuzhiyun to phy-mode. 37*4882a593Smuzhiyun- xlnx,txcsum : 0 or empty for disabling TX checksum offload, 38*4882a593Smuzhiyun 1 to enable partial TX checksum offload, 39*4882a593Smuzhiyun 2 to enable full TX checksum offload 40*4882a593Smuzhiyun- xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload 41*4882a593Smuzhiyun- clocks : AXI bus clock for the device. Refer to common clock bindings. 42*4882a593Smuzhiyun Used to calculate MDIO clock divisor. If not specified, it is 43*4882a593Smuzhiyun auto-detected from the CPU clock (but only on platforms where 44*4882a593Smuzhiyun this is possible). New device trees should specify this - the 45*4882a593Smuzhiyun auto detection is only for backward compatibility. 46*4882a593Smuzhiyun- axistream-connected: Reference to another node which contains the resources 47*4882a593Smuzhiyun for the AXI DMA controller used by this device. 48*4882a593Smuzhiyun If this is specified, the DMA-related resources from that 49*4882a593Smuzhiyun device (DMA registers and DMA TX/RX interrupts) rather 50*4882a593Smuzhiyun than this one will be used. 51*4882a593Smuzhiyun - mdio : Child node for MDIO bus. Must be defined if PHY access is 52*4882a593Smuzhiyun required through the core's MDIO interface (i.e. always, 53*4882a593Smuzhiyun unless the PHY is accessed through a different bus). 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunExample: 56*4882a593Smuzhiyun axi_ethernet_eth: ethernet@40c00000 { 57*4882a593Smuzhiyun compatible = "xlnx,axi-ethernet-1.00.a"; 58*4882a593Smuzhiyun device_type = "network"; 59*4882a593Smuzhiyun interrupt-parent = <µblaze_0_axi_intc>; 60*4882a593Smuzhiyun interrupts = <2 0 1>; 61*4882a593Smuzhiyun clocks = <&axi_clk>; 62*4882a593Smuzhiyun phy-mode = "mii"; 63*4882a593Smuzhiyun reg = <0x40c00000 0x40000 0x50c00000 0x40000>; 64*4882a593Smuzhiyun xlnx,rxcsum = <0x2>; 65*4882a593Smuzhiyun xlnx,rxmem = <0x800>; 66*4882a593Smuzhiyun xlnx,txcsum = <0x2>; 67*4882a593Smuzhiyun phy-handle = <&phy0>; 68*4882a593Smuzhiyun axi_ethernetlite_0_mdio: mdio { 69*4882a593Smuzhiyun #address-cells = <1>; 70*4882a593Smuzhiyun #size-cells = <0>; 71*4882a593Smuzhiyun phy0: phy@0 { 72*4882a593Smuzhiyun device_type = "ethernet-phy"; 73*4882a593Smuzhiyun reg = <1>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun }; 77