1*4882a593SmuzhiyunHisilicon hip04 Ethernet Controller 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun* Ethernet controller node 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun- compatible: should be "hisilicon,hip04-mac". 7*4882a593Smuzhiyun- reg: address and length of the register set for the device. 8*4882a593Smuzhiyun- interrupts: interrupt for the device. 9*4882a593Smuzhiyun- port-handle: <phandle port channel> 10*4882a593Smuzhiyun phandle, specifies a reference to the syscon ppe node 11*4882a593Smuzhiyun port, port number connected to the controller 12*4882a593Smuzhiyun channel, recv channel start from channel * number (RX_DESC_NUM) 13*4882a593Smuzhiyun group, field in the pkg desc, in general, it is the same as the port. 14*4882a593Smuzhiyun- phy-mode: see ethernet.txt [1]. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunOptional properties: 17*4882a593Smuzhiyun- phy-handle: see ethernet.txt [1]. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/net/ethernet.txt 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun* Ethernet ppe node: 23*4882a593SmuzhiyunControl rx & tx fifos of all ethernet controllers. 24*4882a593SmuzhiyunHave 2048 recv channels shared by all ethernet controllers, only if no overlap. 25*4882a593SmuzhiyunEach controller's recv channel start from channel * number (RX_DESC_NUM). 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunRequired properties: 28*4882a593Smuzhiyun- compatible: "hisilicon,hip04-ppe", "syscon". 29*4882a593Smuzhiyun- reg: address and length of the register set for the device. 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun* MDIO bus node: 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunRequired properties: 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun- compatible: should be "hisilicon,mdio". 37*4882a593Smuzhiyun- Inherits from MDIO bus node binding [2] 38*4882a593Smuzhiyun[2] Documentation/devicetree/bindings/net/phy.txt 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample: 41*4882a593Smuzhiyun mdio { 42*4882a593Smuzhiyun compatible = "hisilicon,mdio"; 43*4882a593Smuzhiyun reg = <0x28f1000 0x1000>; 44*4882a593Smuzhiyun #address-cells = <1>; 45*4882a593Smuzhiyun #size-cells = <0>; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun phy0: ethernet-phy@0 { 48*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 49*4882a593Smuzhiyun reg = <0>; 50*4882a593Smuzhiyun marvell,reg-init = <18 0x14 0 0x8001>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun phy1: ethernet-phy@1 { 54*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 55*4882a593Smuzhiyun reg = <1>; 56*4882a593Smuzhiyun marvell,reg-init = <18 0x14 0 0x8001>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun ppe: ppe@28c0000 { 61*4882a593Smuzhiyun compatible = "hisilicon,hip04-ppe", "syscon"; 62*4882a593Smuzhiyun reg = <0x28c0000 0x10000>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun fe: ethernet@28b0000 { 66*4882a593Smuzhiyun compatible = "hisilicon,hip04-mac"; 67*4882a593Smuzhiyun reg = <0x28b0000 0x10000>; 68*4882a593Smuzhiyun interrupts = <0 413 4>; 69*4882a593Smuzhiyun phy-mode = "mii"; 70*4882a593Smuzhiyun port-handle = <&ppe 31 0 31>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun ge0: ethernet@2800000 { 74*4882a593Smuzhiyun compatible = "hisilicon,hip04-mac"; 75*4882a593Smuzhiyun reg = <0x2800000 0x10000>; 76*4882a593Smuzhiyun interrupts = <0 402 4>; 77*4882a593Smuzhiyun phy-mode = "sgmii"; 78*4882a593Smuzhiyun port-handle = <&ppe 0 1 0>; 79*4882a593Smuzhiyun phy-handle = <&phy0>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun ge8: ethernet@2880000 { 83*4882a593Smuzhiyun compatible = "hisilicon,hip04-mac"; 84*4882a593Smuzhiyun reg = <0x2880000 0x10000>; 85*4882a593Smuzhiyun interrupts = <0 410 4>; 86*4882a593Smuzhiyun phy-mode = "sgmii"; 87*4882a593Smuzhiyun port-handle = <&ppe 8 2 8>; 88*4882a593Smuzhiyun phy-handle = <&phy1>; 89*4882a593Smuzhiyun }; 90