1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 5*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 6*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 12*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 13*4882a593Smuzhiyun#include "orion5x-mv88f5181.dtsi" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "Netgear WNR854-t"; 17*4882a593Smuzhiyun compatible = "netgear,wnr854t", "marvell,orion5x-88f5181", 18*4882a593Smuzhiyun "marvell,orion5x"; 19*4882a593Smuzhiyun aliases { 20*4882a593Smuzhiyun serial0 = &uart0; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun memory { 24*4882a593Smuzhiyun device_type = "memory"; 25*4882a593Smuzhiyun reg = <0x00000000 0x2000000>; /* 32 MB */ 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun chosen { 29*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun soc { 33*4882a593Smuzhiyun ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, 34*4882a593Smuzhiyun <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, 35*4882a593Smuzhiyun <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun gpio-keys { 39*4882a593Smuzhiyun compatible = "gpio-keys"; 40*4882a593Smuzhiyun pinctrl-0 = <&pmx_reset_button>; 41*4882a593Smuzhiyun pinctrl-names = "default"; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun reset { 44*4882a593Smuzhiyun label = "Reset Button"; 45*4882a593Smuzhiyun linux,code = <KEY_RESTART>; 46*4882a593Smuzhiyun gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun gpio-leds { 51*4882a593Smuzhiyun compatible = "gpio-leds"; 52*4882a593Smuzhiyun pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>; 53*4882a593Smuzhiyun pinctrl-names = "default"; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun led@0 { 56*4882a593Smuzhiyun label = "wnr854t:green:power"; 57*4882a593Smuzhiyun gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun led@1 { 61*4882a593Smuzhiyun label = "wnr854t:blink:power"; 62*4882a593Smuzhiyun gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun led@2 { 66*4882a593Smuzhiyun label = "wnr854t:green:wan"; 67*4882a593Smuzhiyun gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun}; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun&devbus_bootcs { 73*4882a593Smuzhiyun status = "okay"; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun devbus,keep-config; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun flash@0 { 78*4882a593Smuzhiyun compatible = "cfi-flash"; 79*4882a593Smuzhiyun reg = <0 0x800000>; 80*4882a593Smuzhiyun bank-width = <2>; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun partitions { 83*4882a593Smuzhiyun compatible = "fixed-partitions"; 84*4882a593Smuzhiyun #address-cells = <1>; 85*4882a593Smuzhiyun #size-cells = <1>; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun partition@0 { 88*4882a593Smuzhiyun label = "kernel"; 89*4882a593Smuzhiyun reg = <0x0 0x100000>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun partition@100000 { 93*4882a593Smuzhiyun label = "rootfs"; 94*4882a593Smuzhiyun reg = <0x100000 0x660000>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun partition@760000 { 98*4882a593Smuzhiyun label = "uboot_env"; 99*4882a593Smuzhiyun reg = <0x760000 0x20000>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun partition@780000 { 103*4882a593Smuzhiyun label = "uboot"; 104*4882a593Smuzhiyun reg = <0x780000 0x80000>; 105*4882a593Smuzhiyun read-only; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun}; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun&mdio { 112*4882a593Smuzhiyun status = "okay"; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun switch: switch@0 { 115*4882a593Smuzhiyun compatible = "marvell,mv88e6085"; 116*4882a593Smuzhiyun #address-cells = <1>; 117*4882a593Smuzhiyun #size-cells = <0>; 118*4882a593Smuzhiyun reg = <0>; 119*4882a593Smuzhiyun dsa,member = <0 0>; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun ports { 122*4882a593Smuzhiyun #address-cells = <1>; 123*4882a593Smuzhiyun #size-cells = <0>; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun port@0 { 126*4882a593Smuzhiyun reg = <0>; 127*4882a593Smuzhiyun label = "lan3"; 128*4882a593Smuzhiyun phy-handle = <&lan3phy>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun port@1 { 132*4882a593Smuzhiyun reg = <1>; 133*4882a593Smuzhiyun label = "lan4"; 134*4882a593Smuzhiyun phy-handle = <&lan4phy>; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun port@2 { 138*4882a593Smuzhiyun reg = <2>; 139*4882a593Smuzhiyun label = "wan"; 140*4882a593Smuzhiyun phy-handle = <&wanphy>; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun port@3 { 144*4882a593Smuzhiyun reg = <3>; 145*4882a593Smuzhiyun label = "cpu"; 146*4882a593Smuzhiyun ethernet = <ðport>; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun port@5 { 150*4882a593Smuzhiyun reg = <5>; 151*4882a593Smuzhiyun label = "lan1"; 152*4882a593Smuzhiyun phy-handle = <&lan1phy>; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun port@7 { 156*4882a593Smuzhiyun reg = <7>; 157*4882a593Smuzhiyun label = "lan2"; 158*4882a593Smuzhiyun phy-handle = <&lan2phy>; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun mdio { 163*4882a593Smuzhiyun #address-cells = <1>; 164*4882a593Smuzhiyun #size-cells = <0>; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun lan3phy: ethernet-phy@0 { 167*4882a593Smuzhiyun /* Marvell 88E1121R (port 1) */ 168*4882a593Smuzhiyun compatible = "ethernet-phy-id0141.0cb0", 169*4882a593Smuzhiyun "ethernet-phy-ieee802.3-c22"; 170*4882a593Smuzhiyun reg = <0>; 171*4882a593Smuzhiyun marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun lan4phy: ethernet-phy@1 { 175*4882a593Smuzhiyun /* Marvell 88E1121R (port 2) */ 176*4882a593Smuzhiyun compatible = "ethernet-phy-id0141.0cb0", 177*4882a593Smuzhiyun "ethernet-phy-ieee802.3-c22"; 178*4882a593Smuzhiyun reg = <1>; 179*4882a593Smuzhiyun marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun wanphy: ethernet-phy@2 { 183*4882a593Smuzhiyun /* Marvell 88E1121R (port 1) */ 184*4882a593Smuzhiyun compatible = "ethernet-phy-id0141.0cb0", 185*4882a593Smuzhiyun "ethernet-phy-ieee802.3-c22"; 186*4882a593Smuzhiyun reg = <2>; 187*4882a593Smuzhiyun marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun lan1phy: ethernet-phy@5 { 191*4882a593Smuzhiyun /* Marvell 88E1112 */ 192*4882a593Smuzhiyun compatible = "ethernet-phy-id0141.0cb0", 193*4882a593Smuzhiyun "ethernet-phy-ieee802.3-c22"; 194*4882a593Smuzhiyun reg = <5>; 195*4882a593Smuzhiyun marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun lan2phy: ethernet-phy@7 { 199*4882a593Smuzhiyun /* Marvell 88E1112 */ 200*4882a593Smuzhiyun compatible = "ethernet-phy-id0141.0cb0", 201*4882a593Smuzhiyun "ethernet-phy-ieee802.3-c22"; 202*4882a593Smuzhiyun reg = <7>; 203*4882a593Smuzhiyun marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun}; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyunð { 210*4882a593Smuzhiyun status = "okay"; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun ethernet-port@0 { 213*4882a593Smuzhiyun /* Hardwired to DSA switch */ 214*4882a593Smuzhiyun speed = <1000>; 215*4882a593Smuzhiyun duplex = <1>; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun}; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun&pinctrl { 220*4882a593Smuzhiyun pinctrl-0 = <&pmx_pci_gpios>; 221*4882a593Smuzhiyun pinctrl-names = "default"; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun pmx_power_led: pmx-power-led { 224*4882a593Smuzhiyun marvell,pins = "mpp0"; 225*4882a593Smuzhiyun marvell,function = "gpio"; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun pmx_reset_button: pmx-reset-button { 229*4882a593Smuzhiyun marvell,pins = "mpp1"; 230*4882a593Smuzhiyun marvell,function = "gpio"; 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun pmx_power_led_blink: pmx-power-led-blink { 234*4882a593Smuzhiyun marvell,pins = "mpp2"; 235*4882a593Smuzhiyun marvell,function = "gpio"; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun pmx_wan_led: pmx-wan-led { 239*4882a593Smuzhiyun marvell,pins = "mpp3"; 240*4882a593Smuzhiyun marvell,function = "gpio"; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun pmx_pci_gpios: pmx-pci-gpios { 244*4882a593Smuzhiyun marvell,pins = "mpp4"; 245*4882a593Smuzhiyun marvell,function = "gpio"; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun}; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun&uart0 { 250*4882a593Smuzhiyun /* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */ 251*4882a593Smuzhiyun status = "okay"; 252*4882a593Smuzhiyun}; 253