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/OK3568_Linux_fs/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg7 # SPDX-License-Identifier: GPL-2.0+
9 # Refer doc/README.kwbimage for more details about how-to configure
12 # This configuration applies to COGE5 design (ARM-part)
13 # Two 8-Bit devices are connected on the 16-Bit bus on the same
14 # chip-select. The supported devices are
15 # MT47H256M8EB-3IT:C
16 # MT47H256M8EB-25EIT:C
22 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
23 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
24 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
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H A Dkwbimage_128M16_1.cfg10 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
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H A Dkwbimage-memphis.cfg8 # SPDX-License-Identifier: GPL-2.0+
10 # Refer doc/README.kwbimage for more details about how-to configure
18 # bit 3-0: MPPSel0 2, NF_IO[2]
19 # bit 7-4: MPPSel1 2, NF_IO[3]
20 # bit 12-8: MPPSel2 2, NF_IO[4]
21 # bit 15-12: MPPSel3 2, NF_IO[5]
22 # bit 19-16: MPPSel4 1, NF_IO[6]
23 # bit 23-20: MPPSel5 1, NF_IO[7]
24 # bit 27-24: MPPSel6 1, SYSRST_O
25 # bit 31-28: MPPSel7 0, GPO[7]
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/OK3568_Linux_fs/kernel/include/linux/platform_data/
H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
28 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
104 u32 clk; member
105 u32 t_bacc; /* burst access valid clock to output delay */
106 u32 t_ces; /* CS setup time to clk */
107 u32 t_avds; /* ADV setup time to clk */
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dsdhci-pxa.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: marvell,armada-380-sdhci
23 reg-names:
26 - reg-names
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/OK3568_Linux_fs/kernel/drivers/memory/
H A Dpl172.c1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
13 #include <linux/clk.h>
53 struct clk *clk; member
61 int cycles; in pl172_timing_prop() local
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
66 if (cycles < 0) { in pl172_timing_prop()
67 cycles = 0; in pl172_timing_prop()
68 } else if (cycles > max) { in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
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/OK3568_Linux_fs/u-boot/board/xes/xpedite537x/
H A Dddr.c5 * SPDX-License-Identifier: GPL-2.0+
21 * There are four board-specific SDRAM timing parameters which must be
23 * 1.) CPO (Read Capture Delay)
24 * - TIMING_CFG_2 register
26 * chip-specific internal delays.
27 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
28 * - TIMING_CFG_2 register
32 * of 1/2 clock delay.
34 * - DDR_SDRAM_CLK_CNTL register
37 * - TIMING_CFG_2 register
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/OK3568_Linux_fs/kernel/drivers/watchdog/
H A Drenesas_wdt.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 * Copyright (C) 2015-17 Renesas Electronics Corporation
9 #include <linux/clk.h>
10 #include <linux/delay.h>
36 DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
38 /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
39 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
62 writel_relaxed(val, priv->base + reg); in rwdt_write()
69 rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT); in rwdt_init_timeout()
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H A Dimgpdc_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * -----
12 * The timeout value is rounded to the next power of two clock cycles.
16 * timeout = 2^(delay + 1) clock cycles
18 * Where 'delay' is the value written in PDC_WDT_CONFIG register.
21 * as a power of two number of watchdog clock cycles. The current implementation
25 * The following table shows how the user-configured timeout relates
29 * -----------------------------------
40 #include <linux/clk.h>
84 struct clk *wdt_clk;
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/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Dtegra194-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
19 #include <soc/tegra/bpmp-abi.h>
47 u32 delay; member
67 * Read per-core Read-only system register NVFREQ_FEEDBACK_EL1.
87 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); in map_ndiv_to_freq()
97 * ref_clk_counter(32 bit counter) runs on constant clk, in tegra_read_counters()
99 * It will take = 2 ^ 32 / 408 MHz to overflow ref clk counter in tegra_read_counters()
105 * It will take = 2 ^ 32 / 2000 MHz to overflow core clk counter in tegra_read_counters()
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/OK3568_Linux_fs/kernel/drivers/char/hw_random/
H A Dks-sa-rng.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com
16 #include <linux/clk.h>
23 #include <linux/delay.h>
64 /* Number of CLK input cycles between samples */
70 /* Delay between retries (in usecs) */
86 struct clk *clk; member
93 static unsigned int cycles_to_ns(unsigned long clk_rate, unsigned int cycles) in cycles_to_ns() argument
96 cycles, clk_rate); in cycles_to_ns()
116 struct device *dev = (struct device *)rng->priv; in ks_sa_rng_init()
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/OK3568_Linux_fs/kernel/drivers/pwm/
H A Dpwm-atmel.c1 // SPDX-License-Identifier: GPL-2.0-only
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
22 #include <linux/clk.h>
23 #include <linux/delay.h>
83 struct clk *clk; member
100 return readl_relaxed(chip->base + offset); in atmel_pwm_readl()
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/OK3568_Linux_fs/kernel/drivers/iio/adc/
H A Dcc10001_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 Imagination Technologies Ltd.
6 #include <linux/clk.h>
7 #include <linux/delay.h>
48 * As per device specification, wait six clock cycles after power-up to
49 * activate START. Since adding two more clock cycles delay does not
50 * impact the performance too much, we are adding two additional cycles delay
57 struct clk *adc_clk;
70 writel(val, adc_dev->reg_base + reg); in cc10001_adc_write_reg()
76 return readl(adc_dev->reg_base + reg); in cc10001_adc_read_reg()
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/OK3568_Linux_fs/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lsxhl.cfg5 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
17 # Configure RGMII-0/1 interface pad voltage to 1.8V
30 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
31 # bit23-14: 0 required
34 # bit29-26: 0 required
35 # bit31-30: 0b01 required
39 # bit3-0: 0 required
40 # bit4: 1, T2 mode, addr/cmd are driven for two cycles
41 # bit5: 0, clk is driven during self refresh, we don't care for APX
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H A Dkwbimage-lschl.cfg5 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
17 # Configure RGMII-0/1 interface pad voltage to 1.8V
30 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
31 # bit23-14: 0 required
34 # bit29-26: 0 required
35 # bit31-30: 0b01 required
39 # bit3-0: 0 required
41 # bit5: 0, clk is driven during self refresh, we don't care for APX
42 # bit6: 0, use recommended falling edge of clk for addr/cmd
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/OK3568_Linux_fs/kernel/drivers/clk/mmp/
H A Dclk-gate.c12 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
18 #include "clk.h"
34 if (gate->lock) in mmp_clk_gate_enable()
35 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
37 tmp = readl(gate->reg); in mmp_clk_gate_enable()
38 tmp &= ~gate->mask; in mmp_clk_gate_enable()
39 tmp |= gate->val_enable; in mmp_clk_gate_enable()
40 writel(tmp, gate->reg); in mmp_clk_gate_enable()
42 if (gate->lock) in mmp_clk_gate_enable()
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/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Dtimer-fttmr010.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
18 #include <linux/clk.h>
21 #include <linux/delay.h>
81 * - aspeed timer overflow interrupt is controlled by bits in Control
83 * - aspeed timers always generate interrupt when either one of the
112 * A local singleton used by sched_clock and delay timer reads, which are
124 return readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_up()
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/OK3568_Linux_fs/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
24 # Configure RGMII-0 interface pad voltage to 1.8V
29 # bit13-0: 0xc30, 3120 DDR2 clks refresh rate
30 # bit23-14: 0 required
33 # bit29-26: 0 required
34 # bit31-30: 0b01 required
37 # bit3-0: 0 required
39 # bit5: 0, clk is driven during self refresh, we don't care for APX
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dmmp2-olpc-xo-1-75.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/linux-event-codes.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
15 model = "OLPC XO-1.75";
16 compatible = "olpc,xo-1.75", "mrvl,mmp2";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 compatible = "simple-framebuffer";
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/OK3568_Linux_fs/u-boot/drivers/spi/
H A Drk_spi.c6 * (C) Copyright 2008-2013 Rockchip Electronics
9 * SPDX-License-Identifier: GPL-2.0+
13 #include <clk.h>
15 #include <dt-structs.h>
38 s32 frequency; /* Default clock frequency, -1 for none */
40 uint deactivate_delay_us; /* Delay to wait after deactivate */
41 uint activate_delay_us; /* Delay to wait after activate */
46 struct clk clk; member
56 u32 rsd; /* Rx sample delay cycles */
67 debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0)); in rkspi_dump_regs()
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/OK3568_Linux_fs/u-boot/board/keymile/kmp204x/
H A Dddr.c5 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
28 /* automatic calibration for nb of cycles between read and DQS pre */ in fsl_ddr_board_options()
29 popts->cpo_override = 0xFF; in fsl_ddr_board_options()
31 /* 1/2 clk delay between wr command and data strobe */ in fsl_ddr_board_options()
32 popts->write_data_delay = 4; in fsl_ddr_board_options()
33 /* clk lauched 1/2 applied cylcle after address command */ in fsl_ddr_board_options()
34 popts->clk_adjust = 4; in fsl_ddr_board_options()
36 popts->twot_en = 0; in fsl_ddr_board_options()
39 popts->half_strength_driver_enable = 1; in fsl_ddr_board_options()
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/OK3568_Linux_fs/kernel/drivers/mtd/devices/
H A Dst_spi_fsm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * st_spi_fsm.c - ST Fast Sequence Mode (FSM) Serial Flash Controller
7 * Copyright (C) 2010-2014 STMicroelectronics Limited
18 #include <linux/mtd/spi-nor.h>
20 #include <linux/delay.h>
23 #include <linux/clk.h>
261 struct clk *clk; member
282 uint8_t mode_cycles; /* No. of MODE cycles */
283 uint8_t dummy_cycles; /* No. of DUMMY cycles */
318 * ST Microelectronics/Numonyx --
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/ti/
H A Dam65-cpts.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
23 #include "am65-cpts.h"
164 struct clk *refclk;
186 #define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r)
187 #define am65_cpts_read32(c, r) readl(&(c)->reg->r)
204 cpts->ts_add_val = (NSEC_PER_SEC / cpts->refclk_freq - 1) & 0x7; in am65_cpts_set_add_val()
206 am65_cpts_write32(cpts, cpts->ts_add_val, ts_add_val); in am65_cpts_set_add_val()
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/OK3568_Linux_fs/kernel/drivers/nvmem/
H A Dmxs-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale MXS On-Chip OTP driver
9 #include <linux/clk.h>
10 #include <linux/delay.h>
15 #include <linux/nvmem-provider.h>
31 struct clk *clk; member
41 while (timeout--) { in mxs_ocotp_wait()
42 status = readl(otp->base); in mxs_ocotp_wait()
51 return -EBUSY; in mxs_ocotp_wait()
53 return -EIO; in mxs_ocotp_wait()
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/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c6 * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
7 * and earlier U-Boot Allwiner A10 SPL work
9 * (C) Copyright 2007-2012
14 * SPDX-License-Identifier: GPL-2.0+
69 writel(0, &timer->cpu_cfg); in mctl_ddr3_reset()
70 reg_val = readl(&timer->cpu_cfg); in mctl_ddr3_reset()
74 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
76 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
80 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
82 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
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