Lines Matching +full:clk +full:- +full:delay +full:- +full:cycles
6 * (C) Copyright 2008-2013 Rockchip Electronics
9 * SPDX-License-Identifier: GPL-2.0+
13 #include <clk.h>
15 #include <dt-structs.h>
38 s32 frequency; /* Default clock frequency, -1 for none */
40 uint deactivate_delay_us; /* Delay to wait after deactivate */
41 uint activate_delay_us; /* Delay to wait after activate */
46 struct clk clk; member
56 u32 rsd; /* Rx sample delay cycles */
67 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0)); in rkspi_dump_regs()
68 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1)); in rkspi_dump_regs()
69 debug("ssienr: \t\t0x%08x\n", readl(®s->enr)); in rkspi_dump_regs()
70 debug("ser: \t\t0x%08x\n", readl(®s->ser)); in rkspi_dump_regs()
71 debug("baudr: \t\t0x%08x\n", readl(®s->baudr)); in rkspi_dump_regs()
72 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr)); in rkspi_dump_regs()
73 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr)); in rkspi_dump_regs()
74 debug("txflr: \t\t0x%08x\n", readl(®s->txflr)); in rkspi_dump_regs()
75 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr)); in rkspi_dump_regs()
76 debug("sr: \t\t0x%08x\n", readl(®s->sr)); in rkspi_dump_regs()
77 debug("imr: \t\t0x%08x\n", readl(®s->imr)); in rkspi_dump_regs()
78 debug("isr: \t\t0x%08x\n", readl(®s->isr)); in rkspi_dump_regs()
79 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr)); in rkspi_dump_regs()
80 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr)); in rkspi_dump_regs()
81 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr)); in rkspi_dump_regs()
86 writel(enable ? 1 : 0, ®s->enr); in rkspi_enable_chip()
95 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); in rkspi_set_clk()
107 __func__, speed, priv->input_rate / clk_div); in rkspi_set_clk()
116 if (priv->max_baud_div_in_cpha && clk_div > priv->max_baud_div_in_cpha && priv->mode & SPI_CPHA) { in rkspi_set_clk()
117 clk_div = priv->max_baud_div_in_cpha; in rkspi_set_clk()
118 clk_set_rate(&priv->clk, 4 * speed); in rkspi_set_clk()
119 speed = clk_get_rate(&priv->clk); in rkspi_set_clk()
121 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div); in rkspi_set_clk()
122 priv->last_speed_hz = speed; in rkspi_set_clk()
130 while (readl(®s->sr) & SR_BUSY) { in rkspi_wait_till_not_busy()
133 return -ETIMEDOUT; in rkspi_wait_till_not_busy()
142 struct udevice *bus = dev->parent; in spi_cs_activate()
143 struct rockchip_spi_platdata *plat = bus->platdata; in spi_cs_activate()
145 struct rockchip_spi *regs = priv->regs; in spi_cs_activate()
148 if (plat->deactivate_delay_us && priv->last_transaction_us) { in spi_cs_activate()
149 ulong delay_us; /* The delay completed so far */ in spi_cs_activate()
150 delay_us = timer_get_us() - priv->last_transaction_us; in spi_cs_activate()
151 if (delay_us < plat->deactivate_delay_us) in spi_cs_activate()
152 udelay(plat->deactivate_delay_us - delay_us); in spi_cs_activate()
156 writel(1 << cs, ®s->ser); in spi_cs_activate()
157 if (plat->activate_delay_us) in spi_cs_activate()
158 udelay(plat->activate_delay_us); in spi_cs_activate()
163 struct udevice *bus = dev->parent; in spi_cs_deactivate()
164 struct rockchip_spi_platdata *plat = bus->platdata; in spi_cs_deactivate()
166 struct rockchip_spi *regs = priv->regs; in spi_cs_deactivate()
169 writel(0, ®s->ser); in spi_cs_deactivate()
171 /* Remember time of this transaction so we can honour the bus delay */ in spi_cs_deactivate()
172 if (plat->deactivate_delay_us) in spi_cs_deactivate()
173 priv->last_transaction_us = timer_get_us(); in spi_cs_deactivate()
179 struct rockchip_spi_platdata *plat = dev->platdata; in conv_of_platdata()
180 struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat; in conv_of_platdata()
184 plat->base = dtplat->reg[0]; in conv_of_platdata()
185 plat->frequency = 20000000; in conv_of_platdata()
186 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); in conv_of_platdata()
189 dev->req_seq = 0; in conv_of_platdata()
203 plat->base = dev_read_addr(bus); in rockchip_spi_ofdata_to_platdata()
205 ret = clk_get_by_index(bus, 0, &priv->clk); in rockchip_spi_ofdata_to_platdata()
208 bus->name, ret); in rockchip_spi_ofdata_to_platdata()
212 plat->frequency = in rockchip_spi_ofdata_to_platdata()
213 dev_read_u32_default(bus, "spi-max-frequency", 50000000); in rockchip_spi_ofdata_to_platdata()
214 plat->deactivate_delay_us = in rockchip_spi_ofdata_to_platdata()
215 dev_read_u32_default(bus, "spi-deactivate-delay", 0); in rockchip_spi_ofdata_to_platdata()
216 plat->activate_delay_us = in rockchip_spi_ofdata_to_platdata()
217 dev_read_u32_default(bus, "spi-activate-delay", 0); in rockchip_spi_ofdata_to_platdata()
219 rsd_nsecs = dev_read_u32_default(bus, "rx-sample-delay-ns", 0); in rockchip_spi_ofdata_to_platdata()
223 spi_clk = clk_get_rate(&priv->clk); in rockchip_spi_ofdata_to_platdata()
224 /* rx sample delay is expressed in parent clock cycles (max 3) */ in rockchip_spi_ofdata_to_platdata()
227 pr_err("SPI spi_clk %dHz are too slow to express %u ns delay\n", spi_clk, rsd_nsecs); in rockchip_spi_ofdata_to_platdata()
230 pr_err("SPI spi_clk %dHz are too fast to express %u ns delay, clamping at %u ns\n", in rockchip_spi_ofdata_to_platdata()
233 priv->rsd = rsd; in rockchip_spi_ofdata_to_platdata()
236 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d rsd=%d\n", in rockchip_spi_ofdata_to_platdata()
237 __func__, (uint)plat->base, plat->frequency, in rockchip_spi_ofdata_to_platdata()
238 plat->deactivate_delay_us, priv->rsd); in rockchip_spi_ofdata_to_platdata()
249 * clk_set_rate(...) implementation in our clock-driver will in rockchip_spi_calc_modclk()
263 * are generated by dividing by an even 16-bit integer from in rockchip_spi_calc_modclk()
285 priv->regs = (struct rockchip_spi *)plat->base; in rockchip_spi_probe()
287 priv->last_transaction_us = timer_get_us(); in rockchip_spi_probe()
288 priv->max_freq = plat->frequency; in rockchip_spi_probe()
291 if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE) in rockchip_spi_probe()
292 priv->max_freq = ROCKCHIP_SPI_MAX_RATE; in rockchip_spi_probe()
294 /* Find a module-input clock that fits with the max_freq setting */ in rockchip_spi_probe()
295 ret = clk_set_rate(&priv->clk, in rockchip_spi_probe()
296 rockchip_spi_calc_modclk(priv->max_freq)); in rockchip_spi_probe()
301 priv->input_rate = ret; in rockchip_spi_probe()
302 debug("%s: rate = %u\n", __func__, priv->input_rate); in rockchip_spi_probe()
303 priv->bits_per_word = 8; in rockchip_spi_probe()
306 priv->max_baud_div_in_cpha = quirks_cfg->max_baud_div_in_cpha; in rockchip_spi_probe()
313 struct udevice *bus = dev->parent; in rockchip_spi_claim_bus()
315 struct rockchip_spi *regs = priv->regs; in rockchip_spi_claim_bus()
322 switch (priv->bits_per_word) { in rockchip_spi_claim_bus()
324 priv->n_bytes = 1; in rockchip_spi_claim_bus()
329 priv->n_bytes = 2; in rockchip_spi_claim_bus()
335 priv->bits_per_word); in rockchip_spi_claim_bus()
336 return -EPROTONOSUPPORT; in rockchip_spi_claim_bus()
339 if (priv->speed_hz != priv->last_speed_hz) in rockchip_spi_claim_bus()
340 rkspi_set_clk(priv, priv->speed_hz); in rockchip_spi_claim_bus()
349 if (priv->mode & SPI_CPOL) in rockchip_spi_claim_bus()
351 if (priv->mode & SPI_CPHA) in rockchip_spi_claim_bus()
357 /* SSN to Sclk_out delay */ in rockchip_spi_claim_bus()
369 /* Rxd Sample Delay */ in rockchip_spi_claim_bus()
370 ctrlr0 |= priv->rsd << RXDSD_SHIFT; in rockchip_spi_claim_bus()
376 priv->cr0 = ctrlr0; in rockchip_spi_claim_bus()
378 writel(ctrlr0, ®s->ctrlr0); in rockchip_spi_claim_bus()
385 struct rockchip_spi *regs = priv->regs; in rockchip_spi_config()
386 uint ctrlr0 = priv->cr0; in rockchip_spi_config()
395 writel(ctrlr0, ®s->ctrlr0); in rockchip_spi_config()
402 struct udevice *bus = dev->parent; in rockchip_spi_release_bus()
405 rkspi_enable_chip(priv->regs, false); in rockchip_spi_release_bus()
413 struct udevice *bus = dev->parent; in rockchip_spi_xfer()
415 struct rockchip_spi *regs = priv->regs; in rockchip_spi_xfer()
432 spi_cs_activate(dev, slave_plat->cs); in rockchip_spi_xfer()
438 writel(todo - 1, ®s->ctrlr1); in rockchip_spi_xfer()
444 u32 status = readl(®s->sr); in rockchip_spi_xfer()
448 writel(out ? *out++ : 0, regs->txdr); in rockchip_spi_xfer()
449 towrite--; in rockchip_spi_xfer()
452 u32 byte = readl(regs->rxdr); in rockchip_spi_xfer()
456 toread--; in rockchip_spi_xfer()
462 len -= todo; in rockchip_spi_xfer()
467 spi_cs_deactivate(dev, slave_plat->cs); in rockchip_spi_xfer()
479 if (speed > priv->max_freq) in rockchip_spi_set_speed()
480 speed = priv->max_freq; in rockchip_spi_set_speed()
482 priv->speed_hz = speed; in rockchip_spi_set_speed()
491 priv->mode = mode; in rockchip_spi_set_mode()
514 .compatible = "rockchip,px30-spi",
517 { .compatible = "rockchip,rk3288-spi" },
518 { .compatible = "rockchip,rk3368-spi" },
519 { .compatible = "rockchip,rk3399-spi" },
520 { .compatible = "rockchip,rk3066-spi" },
521 { .compatible = "rockchip,rk3328-spi" },