1*4882a593Smuzhiyun# 2*4882a593Smuzhiyun# Copyright (C) 2011 3*4882a593Smuzhiyun# Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net> 4*4882a593Smuzhiyun# 5*4882a593Smuzhiyun# Based on Kirkwood support: 6*4882a593Smuzhiyun# (C) Copyright 2009 7*4882a593Smuzhiyun# Marvell Semiconductor <www.marvell.com> 8*4882a593Smuzhiyun# Written-by: Prafulla Wadaskar <prafulla@marvell.com> 9*4882a593Smuzhiyun# 10*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun# 12*4882a593Smuzhiyun# Refer doc/README.kwbimage for more details about how-to configure 13*4882a593Smuzhiyun# and create kirkwood boot image 14*4882a593Smuzhiyun# 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun# Boot Media configurations 17*4882a593SmuzhiyunBOOT_FROM nand 18*4882a593SmuzhiyunNAND_ECC_MODE default 19*4882a593SmuzhiyunNAND_PAGE_SIZE 0x0800 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun# SOC registers configuration using bootrom header extension 22*4882a593Smuzhiyun# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun# Configure RGMII-0 interface pad voltage to 1.8V 25*4882a593SmuzhiyunDATA 0xFFD100e0 0x1b1b1b9b 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun#Dram initalization for SINGLE x16 CL=5 @ 400MHz 28*4882a593SmuzhiyunDATA 0xFFD01400 0x43000c30 # DDR Configuration register 29*4882a593Smuzhiyun# bit13-0: 0xc30, 3120 DDR2 clks refresh rate 30*4882a593Smuzhiyun# bit23-14: 0 required 31*4882a593Smuzhiyun# bit24: 1, enable exit self refresh mode on DDR access 32*4882a593Smuzhiyun# bit25: 1 required 33*4882a593Smuzhiyun# bit29-26: 0 required 34*4882a593Smuzhiyun# bit31-30: 0b01 required 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunDATA 0xFFD01404 0x39543000 # DDR Controller Control Low 37*4882a593Smuzhiyun# bit3-0: 0 required 38*4882a593Smuzhiyun# bit4: 0, addr/cmd in smame cycle 39*4882a593Smuzhiyun# bit5: 0, clk is driven during self refresh, we don't care for APX 40*4882a593Smuzhiyun# bit6: 0, use recommended falling edge of clk for addr/cmd 41*4882a593Smuzhiyun# bit11-7: 0 required 42*4882a593Smuzhiyun# bit12: 1 required 43*4882a593Smuzhiyun# bit13: 1 required 44*4882a593Smuzhiyun# bit14: 0, input buffer always powered up 45*4882a593Smuzhiyun# bit17-15: 0 required 46*4882a593Smuzhiyun# bit18: 1, cpu lock transaction enabled 47*4882a593Smuzhiyun# bit19: 0 required 48*4882a593Smuzhiyun# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 49*4882a593Smuzhiyun# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 50*4882a593Smuzhiyun# bit30-28: 3 required 51*4882a593Smuzhiyun# bit31: 0, no additional STARTBURST delay 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunDATA 0xFFD01408 0x22125451 # DDR Timing (Low) 54*4882a593Smuzhiyun# bit3-0: 1, 18 cycle tRAS (tRAS[3-0]) 55*4882a593Smuzhiyun# bit7-4: 5, 6 cycle tRCD 56*4882a593Smuzhiyun# bit11-8: 4, 5 cyle tRP 57*4882a593Smuzhiyun# bit15-12: 5, 6 cyle tWR 58*4882a593Smuzhiyun# bit19-16: 2, 3 cyle tWTR 59*4882a593Smuzhiyun# bit20: 1, 18 cycle tRAS (tRAS[4]) 60*4882a593Smuzhiyun# bit23-21: 0 required 61*4882a593Smuzhiyun# bit27-24: 2, 3 cycle tRRD 62*4882a593Smuzhiyun# bit31-28: 2, 3 cyle tRTP 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunDATA 0xFFD0140C 0x00000833 # DDR Timing (High) 65*4882a593Smuzhiyun# bit6-0: 0x33, 33 cycle tRFC 66*4882a593Smuzhiyun# bit8-7: 0, 1 cycle tR2R 67*4882a593Smuzhiyun# bit10-9: 0, 1 cyle tR2W 68*4882a593Smuzhiyun# bit12-11: 1, 2 cylce tW2W 69*4882a593Smuzhiyun# bit31-13: 0 required 70*4882a593Smuzhiyun 71*4882a593SmuzhiyunDATA 0xFFD01410 0x0000000c # DDR Address Control 72*4882a593Smuzhiyun# bit1-0: 0, Cs0width=x8 73*4882a593Smuzhiyun# bit3-2: 3, Cs0size=1Gb 74*4882a593Smuzhiyun# bit5-4: 0, Cs1width=nonexistent 75*4882a593Smuzhiyun# bit7-6: 0, Cs1size=nonexistent 76*4882a593Smuzhiyun# bit9-8: 0, Cs2width=nonexistent 77*4882a593Smuzhiyun# bit11-10: 0, Cs2size=nonexistent 78*4882a593Smuzhiyun# bit13-12: 0, Cs3width=nonexistent 79*4882a593Smuzhiyun# bit15-14: 0, Cs3size=nonexistent 80*4882a593Smuzhiyun# bit16: 0, Cs0AddrSel 81*4882a593Smuzhiyun# bit17: 0, Cs1AddrSel 82*4882a593Smuzhiyun# bit18: 0, Cs2AddrSel 83*4882a593Smuzhiyun# bit19: 0, Cs3AddrSel 84*4882a593Smuzhiyun# bit31-20: 0 required 85*4882a593Smuzhiyun 86*4882a593SmuzhiyunDATA 0xFFD01414 0x00000000 # DDR Open Pages Control 87*4882a593Smuzhiyun# bit0: 0, OPEn=OpenPage enabled 88*4882a593Smuzhiyun# bit31-1: 0 required 89*4882a593Smuzhiyun 90*4882a593SmuzhiyunDATA 0xFFD01418 0x00000000 # DDR Operation 91*4882a593Smuzhiyun# bit3-0: 0, Cmd=Normal SDRAM Mode 92*4882a593Smuzhiyun# bit31-4: 0 required 93*4882a593Smuzhiyun 94*4882a593SmuzhiyunDATA 0xFFD0141C 0x00000C52 # DDR Mode 95*4882a593Smuzhiyun# bit2-0: 2, Burst Length (2 required) 96*4882a593Smuzhiyun# bit3: 0, Burst Type (0 required) 97*4882a593Smuzhiyun# bit6-4: 5, CAS Latency (CL) 5 98*4882a593Smuzhiyun# bit7: 0, (Test Mode) Normal operation 99*4882a593Smuzhiyun# bit8: 0, (Reset DLL) Normal operation 100*4882a593Smuzhiyun# bit11-9: 0, Write recovery for auto-precharge (3 required ??) 101*4882a593Smuzhiyun# bit12: 0, Fast Active power down exit time (0 required) 102*4882a593Smuzhiyun# bit31-13: 0 required 103*4882a593Smuzhiyun 104*4882a593SmuzhiyunDATA 0xFFD01420 0x00000040 # DDR Extended Mode 105*4882a593Smuzhiyun# bit0: 0, DRAM DLL enabled 106*4882a593Smuzhiyun# bit1: 0, DRAM drive strength normal 107*4882a593Smuzhiyun# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination) 108*4882a593Smuzhiyun# bit5-3: 0 required 109*4882a593Smuzhiyun# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination) 110*4882a593Smuzhiyun# bit9-7: 0 required 111*4882a593Smuzhiyun# bit10: 0, differential DQS enabled 112*4882a593Smuzhiyun# bit11: 0 required 113*4882a593Smuzhiyun# bit12: 0, DRAM output buffer enabled 114*4882a593Smuzhiyun# bit31-13: 0 required 115*4882a593Smuzhiyun 116*4882a593SmuzhiyunDATA 0xFFD01424 0x0000F17F # DDR Controller Control High 117*4882a593Smuzhiyun# bit2-0: 0x7 required 118*4882a593Smuzhiyun# bit3: 1, MBUS Burst Chop disabled 119*4882a593Smuzhiyun# bit6-4: 0x7 required 120*4882a593Smuzhiyun# bit7: 0 required 121*4882a593Smuzhiyun# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz 122*4882a593Smuzhiyun# bit9: 0, no half clock cycle addition to dataout 123*4882a593Smuzhiyun# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals 124*4882a593Smuzhiyun# bit11: 0, 1/4 clock cycle skew disabled for write mesh 125*4882a593Smuzhiyun# bit15-12: 0xf required 126*4882a593Smuzhiyun# bit31-16: 0 required 127*4882a593Smuzhiyun 128*4882a593SmuzhiyunDATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing 129*4882a593Smuzhiyun# bit3-0: 0 required 130*4882a593Smuzhiyun# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal 131*4882a593Smuzhiyun# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal 132*4882a593Smuzhiyun# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal 133*4882a593Smuzhiyun# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 134*4882a593Smuzhiyun# bit31-20: 0 required 135*4882a593Smuzhiyun 136*4882a593SmuzhiyunDATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing 137*4882a593Smuzhiyun# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal 138*4882a593Smuzhiyun# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal 139*4882a593Smuzhiyun# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal 140*4882a593Smuzhiyun# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 141*4882a593Smuzhiyun# bit31-16: 0 required 142*4882a593Smuzhiyun 143*4882a593SmuzhiyunDATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 144*4882a593SmuzhiyunDATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size 145*4882a593Smuzhiyun# bit0: 1, Window enabled 146*4882a593Smuzhiyun# bit1: 0, Write Protect disabled 147*4882a593Smuzhiyun# bit3-2: 0x0, CS0 hit selected 148*4882a593Smuzhiyun# bit23-4: 0xfffff required 149*4882a593Smuzhiyun# bit31-24: 0x0f, Size (i.e. 256MB) 150*4882a593Smuzhiyun 151*4882a593SmuzhiyunDATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb 152*4882a593SmuzhiyunDATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 153*4882a593Smuzhiyun# bit0: 1, Window enabled 154*4882a593Smuzhiyun# bit1: 0, Write Protect disabled 155*4882a593Smuzhiyun# bit3-2: 1, CS1 hit selected 156*4882a593Smuzhiyun# bit23-4: 0xfffff required 157*4882a593Smuzhiyun# bit31-24: 0x0f, Size (i.e. 256MB) 158*4882a593Smuzhiyun 159*4882a593SmuzhiyunDATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 160*4882a593SmuzhiyunDATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 161*4882a593Smuzhiyun 162*4882a593SmuzhiyunDATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) 163*4882a593Smuzhiyun# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM 164*4882a593Smuzhiyun# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM 165*4882a593Smuzhiyun# bit15-8: 0 required 166*4882a593Smuzhiyun# bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1 167*4882a593Smuzhiyun# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM 168*4882a593Smuzhiyun# bit31-24: 0 required 169*4882a593Smuzhiyun 170*4882a593SmuzhiyunDATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 171*4882a593Smuzhiyun# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register 172*4882a593Smuzhiyun# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register 173*4882a593Smuzhiyun# bit31-4 0 required 174*4882a593Smuzhiyun 175*4882a593SmuzhiyunDATA 0xFFD0149C 0x0000E803 # CPU ODT Control 176*4882a593Smuzhiyun# bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1 177*4882a593Smuzhiyun# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4 178*4882a593Smuzhiyun# bit9-8: 0, Internal ODT assertion is controlled by fiels 179*4882a593Smuzhiyun# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm 180*4882a593Smuzhiyun# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm 181*4882a593Smuzhiyun# bit14: 1, M_STARTBURST_IN ODT enabled 182*4882a593Smuzhiyun# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values 183*4882a593Smuzhiyun# bit20-16: 0, Pad N channel driving strength for ODT 184*4882a593Smuzhiyun# bit25-21: 0, Pad P channel driving strength for ODT 185*4882a593Smuzhiyun# bit31-26: 0 required 186*4882a593Smuzhiyun 187*4882a593SmuzhiyunDATA 0xFFD01480 0x00000001 # DDR Initialization Control 188*4882a593Smuzhiyun# bit0: 1, enable DDR init upon this register write 189*4882a593Smuzhiyun# bit31-1: 0, required 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun# End of Header extension 192*4882a593SmuzhiyunDATA 0x0 0x0 193