1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2013 Keymile AG 3*4882a593Smuzhiyun * Valentin Longchamp <valentin.longchamp@keymile.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2009-2011 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <i2c.h> 12*4882a593Smuzhiyun #include <hwconfig.h> 13*4882a593Smuzhiyun #include <asm/mmu.h> 14*4882a593Smuzhiyun #include <fsl_ddr_sdram.h> 15*4882a593Smuzhiyun #include <fsl_ddr_dimm_params.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 18*4882a593Smuzhiyun fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)19*4882a593Smuzhiyunvoid fsl_ddr_board_options(memctl_options_t *popts, 20*4882a593Smuzhiyun dimm_params_t *pdimm, 21*4882a593Smuzhiyun unsigned int ctrl_num) 22*4882a593Smuzhiyun { 23*4882a593Smuzhiyun if (ctrl_num) { 24*4882a593Smuzhiyun printf("Wrong parameter for controller number %d", ctrl_num); 25*4882a593Smuzhiyun return; 26*4882a593Smuzhiyun } 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* automatic calibration for nb of cycles between read and DQS pre */ 29*4882a593Smuzhiyun popts->cpo_override = 0xFF; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 1/2 clk delay between wr command and data strobe */ 32*4882a593Smuzhiyun popts->write_data_delay = 4; 33*4882a593Smuzhiyun /* clk lauched 1/2 applied cylcle after address command */ 34*4882a593Smuzhiyun popts->clk_adjust = 4; 35*4882a593Smuzhiyun /* 1T timing: command/address held for only 1 cycle */ 36*4882a593Smuzhiyun popts->twot_en = 0; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* we have only one module, half str should be OK */ 39*4882a593Smuzhiyun popts->half_strength_driver_enable = 1; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* wrlvl values overridden as recommended by ddr init func */ 42*4882a593Smuzhiyun popts->wrlvl_override = 1; 43*4882a593Smuzhiyun popts->wrlvl_sample = 0xf; 44*4882a593Smuzhiyun popts->wrlvl_start = 0x6; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Enable ZQ calibration */ 47*4882a593Smuzhiyun popts->zq_en = 1; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* DHC_EN =1, ODT = 75 Ohm */ 50*4882a593Smuzhiyun popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm; 51*4882a593Smuzhiyun } 52*4882a593Smuzhiyun dram_init(void)53*4882a593Smuzhiyunint dram_init(void) 54*4882a593Smuzhiyun { 55*4882a593Smuzhiyun phys_size_t dram_size = 0; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun puts("Initializing with SPD\n"); 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun dram_size = fsl_ddr_sdram(); 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun dram_size = setup_ddr_tlbs(dram_size / 0x100000); 62*4882a593Smuzhiyun dram_size *= 0x100000; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun debug(" DDR: "); 65*4882a593Smuzhiyun gd->ram_size = dram_size; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun return 0; 68*4882a593Smuzhiyun } 69