d-link/dns325/kwbimage.cfg

8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 # SPDX-License-Identifier:	GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
24 # Configure RGMII-0 interface pad voltage to 1.8V
29 # bit13-0:  0xc30, 3120 DDR2 clks refresh rate
30 # bit23-14: 0 required
33 # bit29-26: 0 required
34 # bit31-30: 0b01 required
37 # bit3-0:   0 required
39 # bit5:     0, clk is driven during self refresh, we don't care for APX
40 # bit6:     0, use recommended falling edge of clk for addr/cmd
41 # bit11-7:  0 required
45 # bit17-15: 0 required
48 # bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
49 # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
50 # bit30-28: 3 required
51 # bit31:    0, no additional STARTBURST delay
54 # bit3-0:   1, 18 cycle tRAS (tRAS[3-0])
55 # bit7-4:   5, 6 cycle tRCD
56 # bit11-8:  4, 5 cyle tRP
57 # bit15-12: 5, 6 cyle tWR
58 # bit19-16: 2, 3 cyle tWTR
60 # bit23-21: 0 required
61 # bit27-24: 2, 3 cycle tRRD
62 # bit31-28: 2, 3 cyle tRTP
65 # bit6-0:   0x33, 33 cycle tRFC
66 # bit8-7:   0, 1 cycle tR2R
67 # bit10-9:  0, 1 cyle tR2W
68 # bit12-11: 1, 2 cylce tW2W
69 # bit31-13: 0 required
72 # bit1-0:   0, Cs0width=x8
73 # bit3-2:   3, Cs0size=1Gb
74 # bit5-4:   0, Cs1width=nonexistent
75 # bit7-6:   0, Cs1size=nonexistent
76 # bit9-8:   0, Cs2width=nonexistent
77 # bit11-10: 0, Cs2size=nonexistent
78 # bit13-12: 0, Cs3width=nonexistent
79 # bit15-14: 0, Cs3size=nonexistent
84 # bit31-20: 0 required
88 # bit31-1: 0 required
91 # bit3-0:   0, Cmd=Normal SDRAM Mode
92 # bit31-4:  0 required
95 # bit2-0:   2, Burst Length (2 required)
97 # bit6-4:   5, CAS Latency (CL) 5
100 # bit11-9:  0, Write recovery for auto-precharge (3 required ??)
102 # bit31-13: 0 required
108 # bit5-3:   0 required
110 # bit9-7:   0 required
114 # bit31-13: 0 required
117 # bit2-0:   0x7 required
119 # bit6-4:   0x7 required
125 # bit15-12: 0xf required
126 # bit31-16: 0 required
129 # bit3-0:   0 required
130 # bit7-4:   2, 2 cycles from read command to assertion of M_ODT signal
131 # bit11-8:  5, 5 cycles from read command to de-assertion of M_ODT signal
132 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
133 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
134 # bit31-20: 0 required
137 # bit3-0:   2, 2 cycles from write comand to assertion of M_ODT signal
138 # bit7-4:   5, 5 cycles from write command to de-assertion of M_ODT signal
139 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
140 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
141 # bit31-16: 0 required
147 # bit3-2:   0x0, CS0 hit selected
148 # bit23-4:  0xfffff required
149 # bit31-24: 0x0f, Size (i.e. 256MB)
155 # bit3-2:   1, CS1 hit selected
156 # bit23-4:  0xfffff required
157 # bit31-24: 0x0f, Size (i.e. 256MB)
163 # bit3-0:   0b0000, (read) M_ODT[0] is not asserted during read from DRAM
164 # bit7-4:   0b0000, (read) M_ODT[1] is not asserted during read from DRAM
165 # bit15-8:  0 required
166 # bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
167 # bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
168 # bit31-24: 0 required
171 # bit1-0:   0, M_ODT[0] assertion is controlled by ODT Control Low register
172 # bit3-2:   0, M_ODT[1] assertion is controlled by ODT Control Low register
173 # bit31-4   0 required
176 # bit3-0:   0b0011, internal ODT is asserted during read from DRAM bank 0-1
177 # bit7-4:   0b0000, internal ODT is not asserted during write to DRAM bank 0-4
178 # bit9-8:   0, Internal ODT assertion is controlled by fiels
179 # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
180 # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
183 # bit20-16: 0, Pad N channel driving strength for ODT
184 # bit25-21: 0, Pad P channel driving strength for ODT
185 # bit31-26: 0 required
189 # bit31-1:  0, required