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... DDR_UserTool_v1.41/测试文件/RK29/1GB DDR3(用1个CS且由4片256M×8bit组成)焊接检测.cfg DDR_UserTool_v1. ...
7 * DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for11 /* DDR3-800 (5-5-5) */13 /* DDR3-800 (6-6-6) */15 /* DDR3-1066 (6-6-6) */17 /* DDR3-1066 (7-7-7) */19 /* DDR3-1066 (8-8-8) */21 /* DDR3-1333 (7-7-7) */23 /* DDR3-1333 (8-8-8) */25 /* DDR3-1333 (9-9-9) */27 /* DDR3-1333 (10-10-10) */[all …]
77 printf("Set default DDR3 settings\n"); in set_default_ddr3_timings()78 settings.ddr3 = ddr3_default; in set_default_ddr3_timings()85 printf("device:\t\t%s\n", settings.ddr3.manu_name); in print_ddr3_timings()86 printf("marking:\t%s\n", settings.ddr3.manu_marking); in print_ddr3_timings()167 /* Read Siemens eeprom data (DDR3) */ in read_eeprom()169 (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) { in read_eeprom()170 …d not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n"); in read_eeprom()178 if (ddr3_default.magic == settings.ddr3.magic && in read_eeprom()179 ddr3_default.version == settings.ddr3.version) { in read_eeprom()180 printf("Using DDR3 settings from EEPROM\n"); in read_eeprom()[all …]
20 settings.ddr3.x, /* EEPROM Value */ \22 settings.ddr3.x-ddr3_default.x /* Difference */30 /* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */58 struct ddr3_data ddr3; member
4 # if CONFIG_DRAM_CLK <= 360 /* DDR3-1066F @360MHz, timings: 6-5-5-14 */10 # elif CONFIG_DRAM_CLK <= 384 /* DDR3-1066F @384MHz, timings: 6-6-6-15 */16 # elif CONFIG_DRAM_CLK <= 396 /* DDR3-1066F @396MHz, timings: 6-6-6-15 */22 # elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */28 # elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066F @432MHz, timings: 7-6-6-17 */34 # elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066F @456MHz, timings: 7-6-6-18 */40 # elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066F @468MHz, timings: 7-7-7-18 */46 # elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066F @480MHz, timings: 7-7-7-18 */52 # elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066F @504MHz, timings: 7-7-7-19 */58 # elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066F @528MHz, timings: 7-7-7-20 */[all …]
6 * from ddr3 spd, please refer to the spec78 * ddr_compute_dimm_parameters for DDR3 SPD96 printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number); in ddr_compute_dimm_parameters()132 /* These are the types defined by the JEDEC DDR3 SPD spec */ in ddr_compute_dimm_parameters()185 * but DDR3 spec has nature BL8 and BC4, in ddr_compute_dimm_parameters()211 * tck_min=15 MTB (1.875ns) ->DDR3-1066 in ddr_compute_dimm_parameters()212 * =12 MTB (1.5ns) ->DDR3-1333 in ddr_compute_dimm_parameters()213 * =10 MTB (1.25ns) ->DDR3-1600 in ddr_compute_dimm_parameters()229 * DDR3-800D 100 MTB (12.5ns) in ddr_compute_dimm_parameters()230 * DDR3-1066F 105 MTB (13.125ns) in ddr_compute_dimm_parameters()[all …]
42 /* DDR3-800D */44 /* DDR3-800E */46 /* DDR3-1066E */48 /* DDR3-1066F */50 /* DDR3-1066G */52 /* DDR3-1333F* */54 /* DDR3-1333G */56 /* DDR3-1333H */58 /* DDR3-1333J* */60 /* DDR3-1600G* */},[all …]
74 printf("DDR3 Post Run Alg - FAILED 0x%x\n", status); in ddr3_post_algo_config()99 printf("DDR3 Pre silicon Config - FAILED 0x%x\n", status); in ddr3_hws_hw_training()118 printf("DDR3 init controller - FAILED 0x%x\n", status); in ddr3_hws_hw_training()124 printf("DDR3 Post Init - FAILED 0x%x\n", status); in ddr3_hws_hw_training()130 printf("DDR3 Pre Algo Config - FAILED 0x%x\n", status); in ddr3_hws_hw_training()137 printf("DDR3 run algorithm - FAILED 0x%x\n", status); in ddr3_hws_hw_training()143 printf("DDR3 Post Algo Config - FAILED 0x%x\n", status); in ddr3_hws_hw_training()
72 * Args: dram_info ddr3 training information struct103 DEBUG_PBS_S("DDR3 - PBS TX - Starting PBS TX procedure\n"); in ddr3_pbs_tx()114 DEBUG_PBS_S("DDR3 - PBS RX - SW Override Enabled\n"); in ddr3_pbs_tx()121 DEBUG_PBS_C("DDR3 - PBS TX - Working with pattern - ", in ddr3_pbs_tx()167 DEBUG_PBS_S("DDR3 - PBS Tx - ECC Mux Enabled\n"); in ddr3_pbs_tx()169 DEBUG_PBS_S("DDR3 - PBS Tx - ECC Mux Disabled\n"); in ddr3_pbs_tx()192 DEBUG_PBS_S("DDR3 - PBS Tx - Pbs Rep Loop is "); in ddr3_pbs_tx()199 DEBUG_PBS_S("DDR3 - PBS Tx - Set all PBS values to MIN\n"); in ddr3_pbs_tx()216 DEBUG_PBS_S("DDR3 - PBS Tx - ADLL shift right one phase before fail\n"); in ddr3_pbs_tx()224 DEBUG_PBS_S("DDR3 - PBS Tx - perform PBS for each bit\n"); in ddr3_pbs_tx()[all …]
136 DEBUG_DQS_S("DDR3 - DQS Centralization RX - Starting procedure\n"); in ddr3_dqs_centralization_rx()145 DEBUG_DQS_S("DDR3 - DQS Centralization RX - SW Override Enabled\n"); in ddr3_dqs_centralization_rx()153 DEBUG_DQS_FULL_C("DDR3 - DQS Centralization RX - CS - ", in ddr3_dqs_centralization_rx()166 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - ECC Mux Enabled\n"); in ddr3_dqs_centralization_rx()168 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - ECC Mux Disabled\n"); in ddr3_dqs_centralization_rx()170 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - Find all limits\n"); in ddr3_dqs_centralization_rx()177 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - Start calculating center\n"); in ddr3_dqs_centralization_rx()218 DEBUG_DQS_S("DDR3 - DQS Centralization TX - Starting procedure\n"); in ddr3_dqs_centralization_tx()227 DEBUG_DQS_S("DDR3 - DQS Centralization TX - SW Override Enabled\n"); in ddr3_dqs_centralization_tx()235 DEBUG_DQS_FULL_C("DDR3 - DQS Centralization TX - CS - ", in ddr3_dqs_centralization_tx()[all …]
65 puts("DDR3 Training Sequence - Ver 5.7."); in ddr3_print_version()91 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 1\n"); in ddr3_hw_training()177 * Not all frequency modes support the ddr3 training sequence in ddr3_hw_training()180 * inside the ddr3 training sequence without running the training in ddr3_hw_training()185 DEBUG_MAIN_S("DDR3 Training Sequence - Run with PBS.\n"); in ddr3_hw_training()187 DEBUG_MAIN_S("DDR3 Training Sequence - Run without PBS.\n"); in ddr3_hw_training()199 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Dfs High2Low)\n"); in ddr3_hw_training()208 DEBUG_MAIN_S("DDR3 Training Sequence - Registered DIMM Low WL - SKIP\n"); in ddr3_hw_training()215 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 2\n"); in ddr3_hw_training()234 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Sw)\n"); in ddr3_hw_training()[all …]
72 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()135 DEBUG_WL_S("DDR3 - Write Leveling - Write Leveling Cs - "); in ddr3_write_leveling_hw()144 DEBUG_WL_S("DDR3 - Write Leveling - PUP: "); in ddr3_write_leveling_hw()169 DEBUG_WL_S("DDR3 - Write Leveling - HW WL Ended Successfully\n"); in ddr3_write_leveling_hw()173 DEBUG_WL_S("DDR3 - Write Leveling - HW WL Error\n"); in ddr3_write_leveling_hw()197 DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - Starting\n"); in ddr3_wl_supplement()225 DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - SW Override Enabled\n"); in ddr3_wl_supplement()417 DEBUG_WL_C("DDR3 - Write Leveling Hi-Freq Supplement - didn't work for Cs - ", in ddr3_wl_supplement()460 DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - Ended Successfully\n"); in ddr3_wl_supplement()479 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw_reg_dimm()[all …]
170 u32 min_write_recovery_time; /* DDR3/2 only */171 u32 min_write_to_read_cmd_delay; /* DDR3/2 only */172 u32 min_read_to_prech_cmd_delay; /* DDR3/2 only */174 u32 min_refresh_recovery; /* DDR3/2 only */256 /* Check if DDR3 */ in ddr3_spd_init()261 /* No byte for error check in DDR3 SPD, use DDR2 convention */ in ddr3_spd_init()330 * DDR3 device uiDensity val are: (device capacity/8) * in ddr3_spd_init()333 /* Jedec SPD DDR3 - page 7, Save spd_data in Mb - 2048=2GB */ in ddr3_spd_init()367 /* No byte for refresh interval in DDR3 SPD, use DDR2 convention */ in ddr3_spd_init()388 /* DDR3 include 2 byte of CAS support */ in ddr3_spd_init()[all …]
67 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw()128 DEBUG_RL_C("DDR3 - Read Leveling - Results for CS - ", in ddr3_read_leveling_hw()137 DEBUG_RL_S("DDR3 - Read Leveling - PUP: "); in ddr3_read_leveling_hw()158 DEBUG_RL_C("DDR3 - Read Leveling - Read Sample Delay: ", in ddr3_read_leveling_hw()160 DEBUG_RL_C("DDR3 - Read Leveling - Read Ready Delay: ", in ddr3_read_leveling_hw()162 DEBUG_RL_S("DDR3 - Read Leveling - HW RL Ended Successfully\n"); in ddr3_read_leveling_hw()167 DEBUG_RL_S("DDR3 - Read Leveling - HW RL Error\n"); in ddr3_read_leveling_hw()186 DEBUG_RL_S("DDR3 - Read Leveling - Starting SW RL procedure\n"); in ddr3_read_leveling_sw()204 DEBUG_RL_C("DDR3 - Read Leveling - CS - ", (u32) cs, 1); in ddr3_read_leveling_sw()215 DEBUG_RL_S("DDR3 - Read Leveling - ECC Mux Enabled\n"); in ddr3_read_leveling_sw()[all …]
162 DEBUG_INIT_FULL_S("DDR3 Training Sequence - Switching XBAR Window to FastPath Window\n"); in ddr3_restore_and_set_final_windows()269 * Name: ddr3_init - Main DDR3 Init function270 * Desc: This routine initialize the DDR3 MC and runs HW training.284 DEBUG_INIT_S("DDR3 Training Error: Bad sample at reset"); in ddr3_init()286 DEBUG_INIT_S("DDR3 Training Error: Bad DIMM setup"); in ddr3_init()288 DEBUG_INIT_S("DDR3 Training Error: Max CS limit"); in ddr3_init()290 DEBUG_INIT_S("DDR3 Training Error: Max enable CS limit"); in ddr3_init()292 DEBUG_INIT_S("DDR3 Training Error: Bad R-DIMM setup"); in ddr3_init()294 DEBUG_INIT_S("DDR3 Training Error: TWSI failure"); in ddr3_init()296 DEBUG_INIT_S("DDR3 Training Error: DIMM type no match"); in ddr3_init()[all …]
7 It select DDR3 cl-trp-trcd type, default value "DDR3_DEFAULT".it must selected8 according to "Speed Bin" in DDR3 datasheet, DO NOT use smaller "Speed Bin" than9 DDR3 exactly is.39 - ddr3_dll_dis_freq : It's defined the DDR3 dll bypass frequency in MHz (Mega Hz),40 when ddr freq less than or equal this setting value, DDR3 dll will bypssed.47 - ddr3_odt_dis_freq : Defined the DDR3 odt disable frequency in48 MHz (Mega Hz), when ddr frequency less then or equal ethis setting value, the DDR351 - ddr3_drv : Define the driver strength in ohm when connect DDR3.53 - ddr3_odt : Define the ODT in ohm when connect DDR3.55 - phy_ddr3_ca_drv : Define the PHY CA driver strength in ohm when connect DDR3.[all …]
3 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10.dtb4 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10-avb.dtb5 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10-linux.dtb6 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-mini-evb-ddr3-v11.dtb7 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-mini-evb-ddr3-v11-avb.dtb8 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v11-linux.dtb15 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308bs-evb-ddr3-v20-rk618-rgb2dsi.dtb35 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3358-evb-ddr3-v10-linux.dtb78 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb2-ddr3-v10.dtb103 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test1-ddr3-v10.dtb[all …]
9 #include "rk3358-evb-ddr3.dtsi"13 model = "Rockchip linux RK3358 EVB DDR3 board";14 compatible = "rockchip,rk3358-evb-ddr3-v10-linux", "rockchip,px30", "rockchip,rk3358";
27 it selects the DDR3 cl-trp-trcd type. It must be28 set according to "Speed Bin" in DDR3 datasheet,30 for the DDR3 being used.62 - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.64 DDR3 DLL will be bypassed. Note: if DLL was bypassed,72 - rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines78 - rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines82 - rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines86 - rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines91 - rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines[all …]
242 bool "DDR3 1333"272 Set the dram type, 3: DDR3, 7: LPDDR3285 (for DDR3-1600) are 312 to 792.355 Select the timings of the DDR3 chips.363 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"365 Use the timings of the standard JEDEC DDR3-1066F speed bin for366 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin367 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips368 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333369 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm[all …]
2 * Keystone2: DDR3 initialization12 #include <asm/arch/ddr3.h>30 printf("DDR3 speed %d\n", spd_cb.ddrspdclock); in ddr3_init()36 /* Reset DDR3 PHY after PLL enabled */ in ddr3_init()
2 * K2G: DDR3 initialization12 #include <asm/arch/ddr3.h>15 /* K2G GP EVM DDR3 Configuration */66 /* K2G ICE evm DDR3 Configuration */119 /* Reset DDR3 PHY after PLL enabled */ in ddr3_init()
2 * Keystone2: DDR3 initialization13 #include <asm/arch/ddr3.h>117 /* Check the DDR3 controller ID reg if the controllers in ddr3_ecc_support_rmw()159 puts("\nClear entire DDR3 memory to enable ECC\n"); in ddr3_reset_data()190 /* DDR3 size in segments (4KB seg size) */ in ddr3_reset_data()321 /* mapping DDR3 ECC system interrupt from CIC2 to GIC */ in ddr3_init_ecc()339 puts("DDR3 ECC write error interrupted\n"); in ddr3_check_ecc_int()342 puts("DDR3 ECC 2-bit error interrupted\n"); in ddr3_check_ecc_int()389 * Check for PGSR0 error bits of DDR3 PHY. in ddr3_err_reset_workaround()
39 #define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}40 #define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}41 #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}42 #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
7 #include "rv1126-evb-ddr3-v12.dts"10 model = "Rockchip RV1126 EVB DDR3 Board";11 compatible = "rockchip,rv1126-evb-ddr3-v12-spi-nand", "rockchip,rv1126";