1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * board.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2013 Siemens Schweiz AG 5*4882a593Smuzhiyun * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Based on: 8*4882a593Smuzhiyun * TI AM335x boards information header 9*4882a593Smuzhiyun * u-boot:/board/ti/am335x/board.h 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef _BOARD_H_ 17*4882a593Smuzhiyun #define _BOARD_H_ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define PARGS(x) #x , /* Parameter Name */ \ 20*4882a593Smuzhiyun settings.ddr3.x, /* EEPROM Value */ \ 21*4882a593Smuzhiyun ddr3_default.x, /* Default Value */ \ 22*4882a593Smuzhiyun settings.ddr3.x-ddr3_default.x /* Difference */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define PRINTARGS(y) printf("%-20s, %8x, %8x, %4d\n", PARGS(y)) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define MAGIC_CHIP 0x50494843 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Automatic generated definition */ 29*4882a593Smuzhiyun /* Wed, 16 Apr 2014 16:50:41 +0200 */ 30*4882a593Smuzhiyun /* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */ 31*4882a593Smuzhiyun struct ddr3_data { 32*4882a593Smuzhiyun unsigned int magic; /* 0x33524444 */ 33*4882a593Smuzhiyun unsigned int version; /* 0x56312e35 */ 34*4882a593Smuzhiyun unsigned short int ddr3_sratio; /* 0x0080 */ 35*4882a593Smuzhiyun unsigned short int iclkout; /* 0x0000 */ 36*4882a593Smuzhiyun unsigned short int dt0rdsratio0; /* 0x003A */ 37*4882a593Smuzhiyun unsigned short int dt0wdsratio0; /* 0x003F */ 38*4882a593Smuzhiyun unsigned short int dt0fwsratio0; /* 0x009F */ 39*4882a593Smuzhiyun unsigned short int dt0wrsratio0; /* 0x0079 */ 40*4882a593Smuzhiyun unsigned int sdram_tim1; /* 0x0888A39B */ 41*4882a593Smuzhiyun unsigned int sdram_tim2; /* 0x26247FDA */ 42*4882a593Smuzhiyun unsigned int sdram_tim3; /* 0x501F821F */ 43*4882a593Smuzhiyun unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */ 44*4882a593Smuzhiyun unsigned int sdram_config; /* 0x61A44A32 */ 45*4882a593Smuzhiyun unsigned int ref_ctrl; /* 0x0000093B */ 46*4882a593Smuzhiyun unsigned int ioctr_val; /* 0x0000014A */ 47*4882a593Smuzhiyun char manu_name[32]; /* "default@303MHz \0" */ 48*4882a593Smuzhiyun char manu_marking[32]; /* "default \0" */ 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct chip_data { 52*4882a593Smuzhiyun unsigned int magic; 53*4882a593Smuzhiyun char sdevname[16]; 54*4882a593Smuzhiyun char shwver[7]; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct draco_baseboard_id { 58*4882a593Smuzhiyun struct ddr3_data ddr3; 59*4882a593Smuzhiyun struct chip_data chip; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * We have three pin mux functions that must exist. We must be able to enable 64*4882a593Smuzhiyun * uart0, for initial output and i2c0 to read the main EEPROM. We then have a 65*4882a593Smuzhiyun * main pinmux function that can be overridden to enable all other pinmux that 66*4882a593Smuzhiyun * is required on the board. 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun void enable_uart0_pin_mux(void); 69*4882a593Smuzhiyun void enable_uart1_pin_mux(void); 70*4882a593Smuzhiyun void enable_uart2_pin_mux(void); 71*4882a593Smuzhiyun void enable_uart3_pin_mux(void); 72*4882a593Smuzhiyun void enable_uart4_pin_mux(void); 73*4882a593Smuzhiyun void enable_uart5_pin_mux(void); 74*4882a593Smuzhiyun void enable_i2c0_pin_mux(void); 75*4882a593Smuzhiyun void enable_board_pin_mux(void); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* Forwared declaration, defined in common board.c */ 78*4882a593Smuzhiyun void set_env_gpios(unsigned char state); 79*4882a593Smuzhiyun #endif 80