1*4882a593Smuzhiyun /* This file is automatically generated, do not edit */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #if defined(CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H) 4*4882a593Smuzhiyun # if CONFIG_DRAM_CLK <= 360 /* DDR3-1066F @360MHz, timings: 6-5-5-14 */ 5*4882a593Smuzhiyun .cas = 6, 6*4882a593Smuzhiyun .tpr0 = 0x268e5590, 7*4882a593Smuzhiyun .tpr1 = 0xa090, 8*4882a593Smuzhiyun .tpr2 = 0x22a00, 9*4882a593Smuzhiyun .emr2 = 0x0, 10*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 384 /* DDR3-1066F @384MHz, timings: 6-6-6-15 */ 11*4882a593Smuzhiyun .cas = 6, 12*4882a593Smuzhiyun .tpr0 = 0x288f6690, 13*4882a593Smuzhiyun .tpr1 = 0xa0a0, 14*4882a593Smuzhiyun .tpr2 = 0x22a00, 15*4882a593Smuzhiyun .emr2 = 0x0, 16*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 396 /* DDR3-1066F @396MHz, timings: 6-6-6-15 */ 17*4882a593Smuzhiyun .cas = 6, 18*4882a593Smuzhiyun .tpr0 = 0x2a8f6690, 19*4882a593Smuzhiyun .tpr1 = 0xa0a0, 20*4882a593Smuzhiyun .tpr2 = 0x22a00, 21*4882a593Smuzhiyun .emr2 = 0x0, 22*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */ 23*4882a593Smuzhiyun .cas = 7, 24*4882a593Smuzhiyun .tpr0 = 0x2ab06690, 25*4882a593Smuzhiyun .tpr1 = 0xa0a8, 26*4882a593Smuzhiyun .tpr2 = 0x22a00, 27*4882a593Smuzhiyun .emr2 = 0x8, 28*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066F @432MHz, timings: 7-6-6-17 */ 29*4882a593Smuzhiyun .cas = 7, 30*4882a593Smuzhiyun .tpr0 = 0x2cb16690, 31*4882a593Smuzhiyun .tpr1 = 0xa0b0, 32*4882a593Smuzhiyun .tpr2 = 0x22e00, 33*4882a593Smuzhiyun .emr2 = 0x8, 34*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066F @456MHz, timings: 7-6-6-18 */ 35*4882a593Smuzhiyun .cas = 7, 36*4882a593Smuzhiyun .tpr0 = 0x30b26690, 37*4882a593Smuzhiyun .tpr1 = 0xa0b8, 38*4882a593Smuzhiyun .tpr2 = 0x22e00, 39*4882a593Smuzhiyun .emr2 = 0x8, 40*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066F @468MHz, timings: 7-7-7-18 */ 41*4882a593Smuzhiyun .cas = 7, 42*4882a593Smuzhiyun .tpr0 = 0x30b27790, 43*4882a593Smuzhiyun .tpr1 = 0xa0c0, 44*4882a593Smuzhiyun .tpr2 = 0x23200, 45*4882a593Smuzhiyun .emr2 = 0x8, 46*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066F @480MHz, timings: 7-7-7-18 */ 47*4882a593Smuzhiyun .cas = 7, 48*4882a593Smuzhiyun .tpr0 = 0x32b27790, 49*4882a593Smuzhiyun .tpr1 = 0xa0c0, 50*4882a593Smuzhiyun .tpr2 = 0x23200, 51*4882a593Smuzhiyun .emr2 = 0x8, 52*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066F @504MHz, timings: 7-7-7-19 */ 53*4882a593Smuzhiyun .cas = 7, 54*4882a593Smuzhiyun .tpr0 = 0x34d37790, 55*4882a593Smuzhiyun .tpr1 = 0xa0d0, 56*4882a593Smuzhiyun .tpr2 = 0x23600, 57*4882a593Smuzhiyun .emr2 = 0x8, 58*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066F @528MHz, timings: 7-7-7-20 */ 59*4882a593Smuzhiyun .cas = 7, 60*4882a593Smuzhiyun .tpr0 = 0x36d47790, 61*4882a593Smuzhiyun .tpr1 = 0xa0d8, 62*4882a593Smuzhiyun .tpr2 = 0x23600, 63*4882a593Smuzhiyun .emr2 = 0x8, 64*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333H @540MHz, timings: 9-8-8-20 */ 65*4882a593Smuzhiyun .cas = 9, 66*4882a593Smuzhiyun .tpr0 = 0x36b488b4, 67*4882a593Smuzhiyun .tpr1 = 0xa0c8, 68*4882a593Smuzhiyun .tpr2 = 0x2b600, 69*4882a593Smuzhiyun .emr2 = 0x10, 70*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333H @552MHz, timings: 9-8-8-20 */ 71*4882a593Smuzhiyun .cas = 9, 72*4882a593Smuzhiyun .tpr0 = 0x38b488b4, 73*4882a593Smuzhiyun .tpr1 = 0xa0c8, 74*4882a593Smuzhiyun .tpr2 = 0x2ba00, 75*4882a593Smuzhiyun .emr2 = 0x10, 76*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333H @576MHz, timings: 9-8-8-21 */ 77*4882a593Smuzhiyun .cas = 9, 78*4882a593Smuzhiyun .tpr0 = 0x3ab588b4, 79*4882a593Smuzhiyun .tpr1 = 0xa0d0, 80*4882a593Smuzhiyun .tpr2 = 0x2ba00, 81*4882a593Smuzhiyun .emr2 = 0x10, 82*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333H @600MHz, timings: 9-9-9-22 */ 83*4882a593Smuzhiyun .cas = 9, 84*4882a593Smuzhiyun .tpr0 = 0x3cb699b4, 85*4882a593Smuzhiyun .tpr1 = 0xa0d8, 86*4882a593Smuzhiyun .tpr2 = 0x2be00, 87*4882a593Smuzhiyun .emr2 = 0x10, 88*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333H @624MHz, timings: 9-9-9-23 */ 89*4882a593Smuzhiyun .cas = 9, 90*4882a593Smuzhiyun .tpr0 = 0x3eb799b4, 91*4882a593Smuzhiyun .tpr1 = 0xa0e8, 92*4882a593Smuzhiyun .tpr2 = 0x2be00, 93*4882a593Smuzhiyun .emr2 = 0x10, 94*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333H @648MHz, timings: 9-9-9-24 */ 95*4882a593Smuzhiyun .cas = 9, 96*4882a593Smuzhiyun .tpr0 = 0x42b899b4, 97*4882a593Smuzhiyun .tpr1 = 0xa0f0, 98*4882a593Smuzhiyun .tpr2 = 0x2c200, 99*4882a593Smuzhiyun .emr2 = 0x10, 100*4882a593Smuzhiyun # else 101*4882a593Smuzhiyun # error CONFIG_DRAM_CLK is set too high 102*4882a593Smuzhiyun # endif 103*4882a593Smuzhiyun #elif defined(CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J) 104*4882a593Smuzhiyun # if CONFIG_DRAM_CLK <= 360 /* DDR3-800E @360MHz, timings: 6-6-6-14 */ 105*4882a593Smuzhiyun .cas = 6, 106*4882a593Smuzhiyun .tpr0 = 0x268e6690, 107*4882a593Smuzhiyun .tpr1 = 0xa090, 108*4882a593Smuzhiyun .tpr2 = 0x22a00, 109*4882a593Smuzhiyun .emr2 = 0x0, 110*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 384 /* DDR3-800E @384MHz, timings: 6-6-6-15 */ 111*4882a593Smuzhiyun .cas = 6, 112*4882a593Smuzhiyun .tpr0 = 0x2a8f6690, 113*4882a593Smuzhiyun .tpr1 = 0xa0a0, 114*4882a593Smuzhiyun .tpr2 = 0x22a00, 115*4882a593Smuzhiyun .emr2 = 0x0, 116*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 396 /* DDR3-800E @396MHz, timings: 6-6-6-15 */ 117*4882a593Smuzhiyun .cas = 6, 118*4882a593Smuzhiyun .tpr0 = 0x2a8f6690, 119*4882a593Smuzhiyun .tpr1 = 0xa0a0, 120*4882a593Smuzhiyun .tpr2 = 0x22a00, 121*4882a593Smuzhiyun .emr2 = 0x0, 122*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066G @408MHz, timings: 8-7-7-16 */ 123*4882a593Smuzhiyun .cas = 8, 124*4882a593Smuzhiyun .tpr0 = 0x2cb07790, 125*4882a593Smuzhiyun .tpr1 = 0xa0a8, 126*4882a593Smuzhiyun .tpr2 = 0x22a00, 127*4882a593Smuzhiyun .emr2 = 0x8, 128*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066G @432MHz, timings: 8-7-7-17 */ 129*4882a593Smuzhiyun .cas = 8, 130*4882a593Smuzhiyun .tpr0 = 0x2eb17790, 131*4882a593Smuzhiyun .tpr1 = 0xa0b0, 132*4882a593Smuzhiyun .tpr2 = 0x22e00, 133*4882a593Smuzhiyun .emr2 = 0x8, 134*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066G @456MHz, timings: 8-7-7-18 */ 135*4882a593Smuzhiyun .cas = 8, 136*4882a593Smuzhiyun .tpr0 = 0x30b27790, 137*4882a593Smuzhiyun .tpr1 = 0xa0b8, 138*4882a593Smuzhiyun .tpr2 = 0x22e00, 139*4882a593Smuzhiyun .emr2 = 0x8, 140*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066G @468MHz, timings: 8-8-8-18 */ 141*4882a593Smuzhiyun .cas = 8, 142*4882a593Smuzhiyun .tpr0 = 0x32b28890, 143*4882a593Smuzhiyun .tpr1 = 0xa0c0, 144*4882a593Smuzhiyun .tpr2 = 0x23200, 145*4882a593Smuzhiyun .emr2 = 0x8, 146*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066G @480MHz, timings: 8-8-8-18 */ 147*4882a593Smuzhiyun .cas = 8, 148*4882a593Smuzhiyun .tpr0 = 0x34b28890, 149*4882a593Smuzhiyun .tpr1 = 0xa0c0, 150*4882a593Smuzhiyun .tpr2 = 0x23200, 151*4882a593Smuzhiyun .emr2 = 0x8, 152*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066G @504MHz, timings: 8-8-8-19 */ 153*4882a593Smuzhiyun .cas = 8, 154*4882a593Smuzhiyun .tpr0 = 0x36d38890, 155*4882a593Smuzhiyun .tpr1 = 0xa0d0, 156*4882a593Smuzhiyun .tpr2 = 0x23600, 157*4882a593Smuzhiyun .emr2 = 0x8, 158*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066G @528MHz, timings: 8-8-8-20 */ 159*4882a593Smuzhiyun .cas = 8, 160*4882a593Smuzhiyun .tpr0 = 0x38d48890, 161*4882a593Smuzhiyun .tpr1 = 0xa0d8, 162*4882a593Smuzhiyun .tpr2 = 0x23600, 163*4882a593Smuzhiyun .emr2 = 0x8, 164*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333J @540MHz, timings: 10-9-9-20 */ 165*4882a593Smuzhiyun .cas = 10, 166*4882a593Smuzhiyun .tpr0 = 0x38b499b4, 167*4882a593Smuzhiyun .tpr1 = 0xa0c8, 168*4882a593Smuzhiyun .tpr2 = 0x2b600, 169*4882a593Smuzhiyun .emr2 = 0x10, 170*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333J @552MHz, timings: 10-9-9-20 */ 171*4882a593Smuzhiyun .cas = 10, 172*4882a593Smuzhiyun .tpr0 = 0x3ab499b4, 173*4882a593Smuzhiyun .tpr1 = 0xa0c8, 174*4882a593Smuzhiyun .tpr2 = 0x2ba00, 175*4882a593Smuzhiyun .emr2 = 0x10, 176*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333J @576MHz, timings: 10-9-9-21 */ 177*4882a593Smuzhiyun .cas = 10, 178*4882a593Smuzhiyun .tpr0 = 0x3cb599b4, 179*4882a593Smuzhiyun .tpr1 = 0xa0d0, 180*4882a593Smuzhiyun .tpr2 = 0x2ba00, 181*4882a593Smuzhiyun .emr2 = 0x10, 182*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333J @600MHz, timings: 10-9-9-22 */ 183*4882a593Smuzhiyun .cas = 10, 184*4882a593Smuzhiyun .tpr0 = 0x3eb699b4, 185*4882a593Smuzhiyun .tpr1 = 0xa0d8, 186*4882a593Smuzhiyun .tpr2 = 0x2be00, 187*4882a593Smuzhiyun .emr2 = 0x10, 188*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333J @624MHz, timings: 10-10-10-23 */ 189*4882a593Smuzhiyun .cas = 10, 190*4882a593Smuzhiyun .tpr0 = 0x40b7aab4, 191*4882a593Smuzhiyun .tpr1 = 0xa0e8, 192*4882a593Smuzhiyun .tpr2 = 0x2be00, 193*4882a593Smuzhiyun .emr2 = 0x10, 194*4882a593Smuzhiyun # elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333J @648MHz, timings: 10-10-10-24 */ 195*4882a593Smuzhiyun .cas = 10, 196*4882a593Smuzhiyun .tpr0 = 0x44b8aab4, 197*4882a593Smuzhiyun .tpr1 = 0xa0f0, 198*4882a593Smuzhiyun .tpr2 = 0x2c200, 199*4882a593Smuzhiyun .emr2 = 0x10, 200*4882a593Smuzhiyun # else 201*4882a593Smuzhiyun # error CONFIG_DRAM_CLK is set too high 202*4882a593Smuzhiyun # endif 203*4882a593Smuzhiyun #else 204*4882a593Smuzhiyun # error CONFIG_DRAM_TIMINGS_* is not defined 205*4882a593Smuzhiyun #endif 206