1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * K2HK: Clock management APIs 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2012-2014 5*4882a593Smuzhiyun * Texas Instruments Incorporated, <www.ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_ARCH_CLOCK_K2HK_H 11*4882a593Smuzhiyun #define __ASM_ARCH_CLOCK_K2HK_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define PLLSET_CMD_LIST "<pa|arm|ddr3a|ddr3b>" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define KS2_CLK1_6 sys_clk0_6_clk 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CORE_PLL_799 {CORE_PLL, 13, 1, 2} 18*4882a593Smuzhiyun #define CORE_PLL_983 {CORE_PLL, 16, 1, 2} 19*4882a593Smuzhiyun #define CORE_PLL_999 {CORE_PLL, 122, 15, 1} 20*4882a593Smuzhiyun #define CORE_PLL_1167 {CORE_PLL, 19, 1, 2} 21*4882a593Smuzhiyun #define CORE_PLL_1228 {CORE_PLL, 20, 1, 2} 22*4882a593Smuzhiyun #define CORE_PLL_1200 {CORE_PLL, 625, 32, 2} 23*4882a593Smuzhiyun #define PASS_PLL_1228 {PASS_PLL, 20, 1, 2} 24*4882a593Smuzhiyun #define PASS_PLL_983 {PASS_PLL, 16, 1, 2} 25*4882a593Smuzhiyun #define PASS_PLL_1050 {PASS_PLL, 205, 12, 2} 26*4882a593Smuzhiyun #define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2} 27*4882a593Smuzhiyun #define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2} 28*4882a593Smuzhiyun #define TETRIS_PLL_800 {TETRIS_PLL, 32, 5, 1} 29*4882a593Smuzhiyun #define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2} 30*4882a593Smuzhiyun #define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2} 31*4882a593Smuzhiyun #define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2} 32*4882a593Smuzhiyun #define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2} 33*4882a593Smuzhiyun #define TETRIS_PLL_1000 {TETRIS_PLL, 40, 5, 1} 34*4882a593Smuzhiyun #define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1} 35*4882a593Smuzhiyun #define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1} 36*4882a593Smuzhiyun #define TETRIS_PLL_1350 {TETRIS_PLL, 54, 5, 1} 37*4882a593Smuzhiyun #define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1} 38*4882a593Smuzhiyun #define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1} 39*4882a593Smuzhiyun #define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2} 40*4882a593Smuzhiyun #define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4} 41*4882a593Smuzhiyun #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2} 42*4882a593Smuzhiyun #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6} 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* k2h DEV supports 800, 1000, 1200 MHz */ 45*4882a593Smuzhiyun #define DEV_SUPPORTED_SPEEDS 0x383 46*4882a593Smuzhiyun /* k2h ARM supportd 800, 1000, 1200, 1350, 1400 MHz */ 47*4882a593Smuzhiyun #define ARM_SUPPORTED_SPEEDS 0x3EF 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #endif 50