1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef DT_BINDINGS_DDR_H 4*4882a593Smuzhiyun #define DT_BINDINGS_DDR_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun /* 7*4882a593Smuzhiyun * DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for 8*4882a593Smuzhiyun * each corresponding bin. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* DDR3-800 (5-5-5) */ 12*4882a593Smuzhiyun #define DDR3_800D 0 13*4882a593Smuzhiyun /* DDR3-800 (6-6-6) */ 14*4882a593Smuzhiyun #define DDR3_800E 1 15*4882a593Smuzhiyun /* DDR3-1066 (6-6-6) */ 16*4882a593Smuzhiyun #define DDR3_1066E 2 17*4882a593Smuzhiyun /* DDR3-1066 (7-7-7) */ 18*4882a593Smuzhiyun #define DDR3_1066F 3 19*4882a593Smuzhiyun /* DDR3-1066 (8-8-8) */ 20*4882a593Smuzhiyun #define DDR3_1066G 4 21*4882a593Smuzhiyun /* DDR3-1333 (7-7-7) */ 22*4882a593Smuzhiyun #define DDR3_1333F 5 23*4882a593Smuzhiyun /* DDR3-1333 (8-8-8) */ 24*4882a593Smuzhiyun #define DDR3_1333G 6 25*4882a593Smuzhiyun /* DDR3-1333 (9-9-9) */ 26*4882a593Smuzhiyun #define DDR3_1333H 7 27*4882a593Smuzhiyun /* DDR3-1333 (10-10-10) */ 28*4882a593Smuzhiyun #define DDR3_1333J 8 29*4882a593Smuzhiyun /* DDR3-1600 (8-8-8) */ 30*4882a593Smuzhiyun #define DDR3_1600G 9 31*4882a593Smuzhiyun /* DDR3-1600 (9-9-9) */ 32*4882a593Smuzhiyun #define DDR3_1600H 10 33*4882a593Smuzhiyun /* DDR3-1600 (10-10-10) */ 34*4882a593Smuzhiyun #define DDR3_1600J 11 35*4882a593Smuzhiyun /* DDR3-1600 (11-11-11) */ 36*4882a593Smuzhiyun #define DDR3_1600K 12 37*4882a593Smuzhiyun /* DDR3-1600 (10-10-10) */ 38*4882a593Smuzhiyun #define DDR3_1866J 13 39*4882a593Smuzhiyun /* DDR3-1866 (11-11-11) */ 40*4882a593Smuzhiyun #define DDR3_1866K 14 41*4882a593Smuzhiyun /* DDR3-1866 (12-12-12) */ 42*4882a593Smuzhiyun #define DDR3_1866L 15 43*4882a593Smuzhiyun /* DDR3-1866 (13-13-13) */ 44*4882a593Smuzhiyun #define DDR3_1866M 16 45*4882a593Smuzhiyun /* DDR3-2133 (11-11-11) */ 46*4882a593Smuzhiyun #define DDR3_2133K 17 47*4882a593Smuzhiyun /* DDR3-2133 (12-12-12) */ 48*4882a593Smuzhiyun #define DDR3_2133L 18 49*4882a593Smuzhiyun /* DDR3-2133 (13-13-13) */ 50*4882a593Smuzhiyun #define DDR3_2133M 19 51*4882a593Smuzhiyun /* DDR3-2133 (14-14-14) */ 52*4882a593Smuzhiyun #define DDR3_2133N 20 53*4882a593Smuzhiyun /* DDR3 ATF default */ 54*4882a593Smuzhiyun #define DDR3_DEFAULT 21 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif 57