72  * Args:     dram_info   ddr3 training information struct
103 	DEBUG_PBS_S("DDR3 - PBS TX - Starting PBS TX procedure\n");  in ddr3_pbs_tx()
114 	DEBUG_PBS_S("DDR3 - PBS RX - SW Override Enabled\n");  in ddr3_pbs_tx()
121 		DEBUG_PBS_C("DDR3 - PBS TX - Working with pattern - ",  in ddr3_pbs_tx()
167 					DEBUG_PBS_S("DDR3 - PBS Tx - ECC Mux Enabled\n");  in ddr3_pbs_tx()
169 					DEBUG_PBS_S("DDR3 - PBS Tx - ECC Mux Disabled\n");  in ddr3_pbs_tx()
192 					DEBUG_PBS_S("DDR3 - PBS Tx - Pbs Rep Loop is ");  in ddr3_pbs_tx()
199 					DEBUG_PBS_S("DDR3 - PBS Tx - Set all PBS values to MIN\n");  in ddr3_pbs_tx()
216 					DEBUG_PBS_S("DDR3 - PBS Tx - ADLL shift right one phase before fail\n");  in ddr3_pbs_tx()
224 					DEBUG_PBS_S("DDR3 - PBS Tx - perform PBS for each bit\n");  in ddr3_pbs_tx()
239 					DEBUG_PBS_S("DDR3 - PBS Tx - FAIL - Adll reach max value\n");  in ddr3_pbs_tx()
243 				DEBUG_PBS_FULL_C("DDR3 - PBS TX - values for iteration - ",  in ddr3_pbs_tx()
250 					DEBUG_PBS_S("DDR3 - PBS - PUP");  in ddr3_pbs_tx()
292 		DEBUG_PBS_C("DDR3 - PBS TX - values for current pattern - ",  in ddr3_pbs_tx()
299 			DEBUG_PBS_S("DDR3 - PBS - PUP");  in ddr3_pbs_tx()
320 		DEBUG_PBS_C("DDR3 - PBS TX - Average for pattern - ",  in ddr3_pbs_tx()
344 	DEBUG_PBS_S("DDR3 - PBS TX - Average for all patterns:\n");  in ddr3_pbs_tx()
350 		DEBUG_PBS_S("DDR3 - PBS - PUP");  in ddr3_pbs_tx()
391 	DEBUG_PBS_S("DDR3 - PBS Tx - PBS TX ended successfuly\n");  in ddr3_pbs_tx()
399  * Args:     dram_info            ddr3 training information struct
492 		DEBUG_PBS_FULL_S("DDR3 - PBS Tx - Shift DQ - Adll value reached maximum\n");  in ddr3_tx_shift_dqs_adll_step_before_fail()
516  * Args:     dram_info   ddr3 training information struct
546 	DEBUG_PBS_S("DDR3 - PBS RX - Starting PBS RX procedure\n");  in ddr3_pbs_rx()
557 	DEBUG_PBS_FULL_S("DDR3 - PBS RX - SW Override Enabled\n");  in ddr3_pbs_rx()
564 		DEBUG_PBS_FULL_C("DDR3 - PBS RX - Working with pattern - ",  in ddr3_pbs_rx()
609 					DEBUG_PBS_FULL_S("DDR3 - PBS Rx - ECC Mux Enabled\n");  in ddr3_pbs_rx()
611 					DEBUG_PBS_FULL_S("DDR3 - PBS Rx - ECC Mux Disabled\n");  in ddr3_pbs_rx()
633 					DEBUG_PBS_FULL_S("DDR3 - PBS Rx - Pbs Rep Loop is ");  in ddr3_pbs_rx()
663 					DEBUG_PBS_FULL_S("DDR3 - PBS Rx - Shift RX DQS to first fail\n");  in ddr3_pbs_rx()
669 						DEBUG_PBS_S("DDR3 - PBS Rx - ddr3_rx_shift_dqs_to_first_fail failed.\n");  in ddr3_pbs_rx()
727 					DEBUG_PBS_FULL_S("DDR3 - PBS Rx - perform PBS for each bit\n");  in ddr3_pbs_rx()
733 						DEBUG_PBS_S("DDR3 - PBS Rx - ddr3_pbs_per_bit failed.");  in ddr3_pbs_rx()
742 					DEBUG_PBS_FULL_S("DDR3 - PBS Rx - FAIL - Algorithm failed doing RX PBS\n");  in ddr3_pbs_rx()
753 				DEBUG_PBS_FULL_C("DDR3 - PBS RX - values for iteration - ",  in ddr3_pbs_rx()
760 					DEBUG_PBS_FULL_S("DDR3 - PBS - PUP");  in ddr3_pbs_rx()
809 		DEBUG_PBS_FULL_C("DDR3 - PBS RX - Average for pattern - ",  in ddr3_pbs_rx()
824 		DEBUG_PBS_C("DDR3 - PBS RX - values for current pattern - ",  in ddr3_pbs_rx()
831 			DEBUG_PBS_S("DDR3 - PBS RX - PUP");  in ddr3_pbs_rx()
860 	DEBUG_PBS_S("DDR3 - PBS RX - Average for all patterns:\n");  in ddr3_pbs_rx()
866 		DEBUG_PBS_S("DDR3 - PBS - PUP");  in ddr3_pbs_rx()
903 	DEBUG_PBS_FULL_S("DDR3 - PBS RX - ended successfuly\n");  in ddr3_pbs_rx()
911  * Args:     dram_info           ddr3 training information struct
954 	DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - Starting...\n");  in ddr3_rx_shift_dqs_to_first_fail()
957 	DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - Set DQS ADLL to Max for all PUPs\n");  in ddr3_rx_shift_dqs_to_first_fail()
972 …DEBUG_PBS_S("DDR3 - PBS Rx - Shift DQS - MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_SRAM_CMP(ddr3_sdram_co…  in ddr3_rx_shift_dqs_to_first_fail()
981 				DEBUG_PBS_S("DDR3 - PBS Rx - Shift DQS - fail on start with first deskew value\n");  in ddr3_rx_shift_dqs_to_first_fail()
998 				DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - DQS deskew reached maximum value\n");  in ddr3_rx_shift_dqs_to_first_fail()
1003 		DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - Inc DQS deskew for PUPs: ");  in ddr3_rx_shift_dqs_to_first_fail()
1018 	DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - ADLL shift one step before fail\n");  in ddr3_rx_shift_dqs_to_first_fail()
1030 …DEBUG_PBS_S("DDR3 - PBS Rx - Shift DQS - MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_SRAM_CMP(ddr3_sdram_co…  in ddr3_rx_shift_dqs_to_first_fail()
1063 			DEBUG_PBS_FULL_S("DDR3 - PBS Rx - Shift DQS - Adll reach min value\n");  in ddr3_rx_shift_dqs_to_first_fail()
1094 	DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - Lock PBS value for all remaining PUPs bits, pup ");  in lock_pups()
1174 	DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - Started\n");  in ddr3_pbs_per_bit()
1205 				DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - All pups are locked for DQ ");  in ddr3_pbs_per_bit()
1256 						DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - PbsCurrVal: ");  in ddr3_pbs_per_bit()
1289 			DEBUG_PBS_FULL_S("DDR3 - PBS Per bit -  All bit in all pups are successfully locked\n");  in ddr3_pbs_per_bit()
1295 			DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - PBS deskew elements reach max\n");  in ddr3_pbs_per_bit()
1300 			DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - StartOver: ");  in ddr3_pbs_per_bit()
1315 						DEBUG_PBS_FULL_C("DDR3 - PBS Per bit - skipping lock of pup (first loop of pbs)",  in ddr3_pbs_per_bit()
1321 …DEBUG_PBS_FULL_C("DDR3 - PBS Per bit - Locking pup %d (even though it wasn't supposed to be locked…  in ddr3_pbs_per_bit()
1327 					DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - Locking remaning DQs for pup - ");  in ddr3_pbs_per_bit()
1355 					DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - Pup ");  in ddr3_pbs_per_bit()
1364 				DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - false fail - returning to start\n");  in ddr3_pbs_per_bit()
1379 						DEBUG_PBS_FULL_C("DDR3 - PBS Per bit - First fail in pup ",  in ddr3_pbs_per_bit()
1426 	DEBUG_PBS_FULL_S("DDR3 - PBS - ddr3_set_pbs_results:\n");  in ddr3_set_pbs_results()
1451 		DEBUG_PBS_FULL_S("DDR3 - PBS - PUP");  in ddr3_set_pbs_results()