170 	u32 min_write_recovery_time;		/* DDR3/2 only */
171 	u32 min_write_to_read_cmd_delay;	/* DDR3/2 only */
172 	u32 min_read_to_prech_cmd_delay;	/* DDR3/2 only */
174 	u32 min_refresh_recovery;		/* DDR3/2 only */
256 	/* Check if DDR3 */  in ddr3_spd_init()
261 	/* No byte for error check in DDR3 SPD, use DDR2 convention */  in ddr3_spd_init()
330 	 * DDR3 device uiDensity val are: (device capacity/8) *  in ddr3_spd_init()
333 	/* Jedec SPD DDR3 - page 7, Save spd_data in Mb  - 2048=2GB */  in ddr3_spd_init()
367 	/* No byte for refresh interval in DDR3 SPD, use DDR2 convention */  in ddr3_spd_init()
388 	/* DDR3 include 2 byte of CAS support */  in ddr3_spd_init()
403 	 * For DDR3 and DDR2 includes Write Recovery Time field.  in ddr3_spd_init()
442 	 * For DDR3 and DDR2 includes Internal Write To Read Command Delay  in ddr3_spd_init()
450 	 * For DDR3 and DDR2 includes Internal Read To Precharge Command Delay  in ddr3_spd_init()
458 	 * For DDR3 includes Minimum Activate to Activate/Refresh Command  in ddr3_spd_init()
483 		DEBUG_INIT_C("DDR3 Training Sequence - Registered DIMM vendor ID 0x",  in ddr3_spd_init()
514 		DEBUG_INIT_S("DDR3 Dimm Compare - DIMM type does not match - FAIL\n");  in ddr3_spd_sum_init()
519 		DEBUG_INIT_S("DDR3 Dimm Compare - ECC does not match. ECC is disabled\n");  in ddr3_spd_sum_init()
522 		DEBUG_INIT_S("DDR3 Dimm Compare - DRAM bus width does not match - FAIL\n");  in ddr3_spd_sum_init()
616 		DEBUG_INIT_S("DDR3 Training Sequence - No DIMMs detected\n");
618 		DEBUG_INIT_S("DDR3 Training Sequence - FAILED (Wrong DIMMs Setup)\n");
622 		DEBUG_INIT_C("DDR3 Training Sequence - Number of DIMMs detected: ",
648 		DEBUG_INIT_C("DDR3 Training Sequence - Number of CS exceed limit -  ",
683 		DEBUG_INIT_C("DDR3 Training Sequence - Number of enabled CS exceed limit -  ",
688 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - Number of CS = ", cs_num, 1);
710 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - Cas Latency = ", cl, 1);
720 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - ECC Enabled\n");
722 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - ECC Disabled\n");
727 		DEBUG_INIT_S("DDR3 Training Sequence - FAIL - Illegal R-DIMM setup\n");
731 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - R-DIMM\n");
733 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - U-DIMM\n");
743 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 64Bits\n");
745 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 32Bits\n");
748 	DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 16Bits\n");
754 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 32Bits\n");
756 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 16Bits\n");
768 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - RefreshInterval/Hclk = ", tmp, 4);
795 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRAS-1 = ", tmp, 1);
804 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRCD-1 = ", tmp, 1);
812 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRP-1 = ", tmp, 1);
820 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tWR-1 = ", tmp, 1);
828 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tWTR-1 = ", tmp, 1);
836 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRRD-1 = ", tmp, 1);
844 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRTP-1 = ", tmp, 1);
861 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRFC-1 = ", tmp, 1);
876 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tFAW = ", tmp, 1);
885 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tFAW-4*tRRD = ", tmp, 1);
955 	/*{0x0000142C}  -   DDR3 Timing Register */
1043 	DEBUG_INIT_FULL_C("DDR3 - SPD-SET - Read Data Sample Delays = ", reg,
1055 	DEBUG_INIT_FULL_C("DDR3 - SPD-SET - Read Data Ready Delays = ", reg, 1);
1146 	/*{0x000015E0} - DDR3 Rank Control Register */
1162 				DEBUG_INIT_FULL_C("DDR3 - SPD-SET - Setting Address Mirroring for CS = ",
1195 		DEBUG_INIT_S("DDR3 Training Sequence - Registered DIMM detected\n");