Home
last modified time | relevance | path

Searched +full:cs +full:- +full:2 (Results 1 – 25 of 1026) sorted by relevance

12345678910>>...42

/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dgen2_engine_cs.c1 // SPDX-License-Identifier: MIT
17 u32 cmd, *cs; in gen2_emit_flush() local
23 cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); in gen2_emit_flush()
24 if (IS_ERR(cs)) in gen2_emit_flush()
25 return PTR_ERR(cs); in gen2_emit_flush()
27 *cs++ = cmd; in gen2_emit_flush()
28 while (num_store_dw--) { in gen2_emit_flush()
29 *cs++ = MI_STORE_DWORD_INDEX; in gen2_emit_flush()
30 *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); in gen2_emit_flush()
31 *cs++ = 0; in gen2_emit_flush()
[all …]
H A Dgen7_renderclear.c1 // SPDX-License-Identifier: MIT
11 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
47 * a shader on every HW thread, and clear the thread-local registers. in num_primitives()
51 return bv->max_threads; in num_primitives()
58 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
61 bv->max_threads = 70; in batch_get_defaults()
63 case 2: in batch_get_defaults()
64 bv->max_threads = 140; in batch_get_defaults()
67 bv->max_threads = 280; in batch_get_defaults()
70 bv->surface_height = 16 * 16; in batch_get_defaults()
[all …]
H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
17 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
19 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
21 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
22 * produced by non-pipelined state commands), software needs to first
23 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
26 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
27 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
32 * BEFORE the pipe-control with a post-sync op and no write-cache
[all …]
H A Dselftest_lrc.c2 * SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
26 #define NUM_GPR_DW (NUM_GPR * 2) /* each GPR is 2 dwords */
34 obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in create_scratch()
40 vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL); in create_scratch()
82 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
86 return -ETIME; in wait_for_submit()
102 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset()
108 if (READ_ONCE(rq->fence.error)) in wait_for_reset()
114 if (rq->fence.error != -EIO) { in wait_for_reset()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
79 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
80 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
81 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
82 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
83 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
84 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
85 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
86 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c4 * SPDX-License-Identifier: GPL-2.0
47 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
60 * Args: freq - current sequence frequency
61 * dram_info - main struct
67 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
71 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw()
72 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
87 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
88 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
104 * Read results to arrays - Results are required for WL in ddr3_write_leveling_hw()
[all …]
H A Dddr3_read_leveling.c4 * SPDX-License-Identifier: GPL-2.0
45 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
49 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
57 * Args: dram_info - main struct
58 * freq - current sequence frequency
66 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_hw()
67 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw()
74 /* Enable CS in the automatic process */ in ddr3_read_leveling_hw()
75 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
77 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw()
[all …]
H A Dddr3_spd.c4 * SPDX-License-Identifier: GPL-2.0
29 #define SPD_DEV_TYPE_BYTE 2
34 #define SPD_MODULE_TYPE_UDIMM 2
170 u32 min_write_recovery_time; /* DDR3/2 only */
171 u32 min_write_to_read_cmd_delay; /* DDR3/2 only */
172 u32 min_read_to_prech_cmd_delay; /* DDR3/2 only */
174 u32 min_refresh_recovery; /* DDR3/2 only */
197 * Name: ddr3_get_dimm_num - Find number of dimms and their addresses
199 * Args: dimm_addr - array of dimm addresses
212 dimm_cur_addr--) { in ddr3_get_dimm_num()
[all …]
H A Dddr3_dqs.c4 * SPDX-License-Identifier: GPL-2.0
56 /* State machine for centralization - find low & high limit */
68 int ddr3_find_adll_limits(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, int is_tx);
71 static int ddr3_center_calc(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
73 int ddr3_special_pattern_i_search(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
75 int ddr3_special_pattern_ii_search(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
77 int ddr3_set_dqs_centralization_results(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
98 switch (dram_info->ddr_width) { in ddr3_dqs_choose_pattern()
133 u32 cs, ecc, reg; in ddr3_dqs_centralization_rx() local
136 DEBUG_DQS_S("DDR3 - DQS Centralization RX - Starting procedure\n"); in ddr3_dqs_centralization_rx()
[all …]
/OK3568_Linux_fs/u-boot/drivers/rkflash/
H A Dflash.c4 * SPDX-License-Identifier: GPL-2.0
26 2,
47 static void flash_read_id_raw(u8 cs, u8 *buf) in flash_read_id_raw() argument
51 nandc_flash_reset(cs); in flash_read_id_raw()
52 nandc_flash_cs(cs); in flash_read_id_raw()
53 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); in flash_read_id_raw()
54 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); in flash_read_id_raw()
57 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
58 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
59 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
[all …]
/OK3568_Linux_fs/kernel/drivers/rkflash/
H A Dflash.c1 // SPDX-License-Identifier: GPL-2.0
27 2,
48 static void flash_read_id_raw(u8 cs, u8 *buf) in flash_read_id_raw() argument
52 nandc_flash_reset(cs); in flash_read_id_raw()
53 nandc_flash_cs(cs); in flash_read_id_raw()
54 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); in flash_read_id_raw()
55 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); in flash_read_id_raw()
58 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
59 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
60 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A Dm5307sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
20 #define MCF_BUSCLK (MCF_CLK / 2)
40 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
[all …]
H A Dm5407sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
20 #define MCF_BUSCLK (MCF_CLK / 2)
40 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
[all …]
H A Dm5206sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
27 #define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
62 #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
63 #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
65 #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
66 #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
67 #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
68 #define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
[all …]
H A Dst,stm32-fmc2-ebi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@st.com>
26 const: st,stm32mp1-fmc2-ebi
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen3.c2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
17 * regs has the to-be-set values for DDR controller registers
21 * 2 resumes from step 1 and continues to initialize
37 int csn = -1; in fsl_ddr_set_memctl_regs()
52 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) in fsl_ddr_set_memctl_regs()
53 case 2: in fsl_ddr_set_memctl_regs()
67 if (step == 2) in fsl_ddr_set_memctl_regs()
70 if (regs->ddr_eor) in fsl_ddr_set_memctl_regs()
71 out_be32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
[all …]
/OK3568_Linux_fs/u-boot/drivers/spi/
H A Domap3_spi.c8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
17 * SPDX-License-Identifier: GPL-2.0+
44 /* per-register bitmasks */
45 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
46 #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
53 #define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
58 #define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
74 #define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
105 /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
106 /* channel1: 0x40 - 0x50, bus 0 & 1 */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
52 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
84 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
149 u32 l3cc_table[GEN9_MOCS_SIZE / 2];
162 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs()
163 struct intel_uncore *uncore = engine->uncore; in load_render_mocs()
164 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
165 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
174 if (!HAS_ENGINE(engine->gt, ring_id)) in load_render_mocs()
186 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { in load_render_mocs()
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_init.c4 * SPDX-License-Identifier: GPL-2.0
16 #include "../../../../arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h"
112 * sys_env_device_rev_get - Get Marvell controller device revision number
162 * DESCRIPTION: Get bit mask of enabled CS
169 * Bit mask of enabled CS, 1 if only CS0 enabled,
187 /* Return XBAR windows 4-7 or 16-19 init configuration */ in ddr3_restore_and_set_final_windows()
191 printf("%s Training Sequence - Switching XBAR Window to FastPath Window\n", in ddr3_restore_and_set_final_windows()
198 u32 reg, cs; in ddr3_restore_and_set_final_windows() local
200 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_restore_and_set_final_windows()
201 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
[all …]
/OK3568_Linux_fs/kernel/drivers/memory/
H A Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
31 #define FMC2_BCR_MTYP GENMASK(3, 2)
146 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
170 const struct stm32_fmc2_prop *prop, int cs);
171 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
174 int cs, u32 setup);
179 int cs) in stm32_fmc2_ebi_check_mux() argument
183 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_mux()
188 return -EINVAL; in stm32_fmc2_ebi_check_mux()
193 int cs) in stm32_fmc2_ebi_check_waitcfg() argument
[all …]
/OK3568_Linux_fs/buildroot/package/botan/
H A D0001-Revert-workaround-a-miscompilation-issue-in-clang-12.patch9 Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
11 ---
12 src/lib/hash/sha3/sha3.cpp | 46 ++++++-----------------
13 src/lib/hash/sha3/sha3_bmi2/sha3_bmi2.cpp | 46 ++++++-----------------
14 2 files changed, 22 insertions(+), 70 deletions(-)
16 diff --git a/src/lib/hash/sha3/sha3.cpp b/src/lib/hash/sha3/sha3.cpp
18 --- a/src/lib/hash/sha3/sha3.cpp
20 @@ -11,47 +11,23 @@
24 -#include <tuple>
25 -
[all …]
/OK3568_Linux_fs/u-boot/board/tqc/tqm834x/
H A Dtqm834x.c5 * SPDX-License-Identifier: GPL-2.0+
45 static long int get_ddr_bank_size(short cs, long *base);
46 static void set_cs_bounds(short cs, ulong base, ulong size);
47 static void set_cs_config(short cs, long config);
59 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) in board_early_init_r()
73 int cs; in dram_init() local
76 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE; in dram_init()
77 im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G); in dram_init()
79 /* set CS bounds to maximum size */ in dram_init()
80 for(cs = 0; cs < 4; ++cs) { in dram_init()
[all …]
/OK3568_Linux_fs/u-boot/cmd/ddr_tool/ddr_dq_eye/
H A Dddr_dq_eye.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch-rockchip/sdram_common.h>
43 print_border->far_left = 0; in calc_print_border()
44 print_border->far_right = deskew_num - 1; in calc_print_border()
54 if (result->dqs[dqs].dq_min[dq] < far_left) in calc_print_border()
55 far_left = result->dqs[dqs].dq_min[dq]; in calc_print_border()
56 if (result->dqs[dqs].dq_max[dq] > far_right) in calc_print_border()
57 far_right = result->dqs[dqs].dq_max[dq]; in calc_print_border()
61 if (far_right - far_left + 1 > PRINT_RANGE) { in calc_print_border()
62 print_border->far_left = far_left & ~((u16)(PRINT_STEP * 4 - 1)); in calc_print_border()
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/syscon/
H A Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
[all …]

12345678910>>...42