1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /****************************************************************************/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * m5206sim.h -- ColdFire 5206 System Integration Module support. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) 8*4882a593Smuzhiyun * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /****************************************************************************/ 12*4882a593Smuzhiyun #ifndef m5206sim_h 13*4882a593Smuzhiyun #define m5206sim_h 14*4882a593Smuzhiyun /****************************************************************************/ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CPU_NAME "COLDFIRE(m5206)" 17*4882a593Smuzhiyun #define CPU_INSTR_PER_JIFFY 3 18*4882a593Smuzhiyun #define MCF_BUSCLK MCF_CLK 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include <asm/m52xxacr.h> 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * Define the 5206 SIM register set addresses. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */ 26*4882a593Smuzhiyun #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */ 27*4882a593Smuzhiyun #define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */ 28*4882a593Smuzhiyun #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */ 29*4882a593Smuzhiyun #define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */ 30*4882a593Smuzhiyun #define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */ 31*4882a593Smuzhiyun #define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */ 32*4882a593Smuzhiyun #define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */ 33*4882a593Smuzhiyun #define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */ 34*4882a593Smuzhiyun #define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */ 35*4882a593Smuzhiyun #define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */ 36*4882a593Smuzhiyun #define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */ 37*4882a593Smuzhiyun #define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */ 38*4882a593Smuzhiyun #define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */ 39*4882a593Smuzhiyun #ifdef CONFIG_M5206e 40*4882a593Smuzhiyun #define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */ 41*4882a593Smuzhiyun #define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */ 42*4882a593Smuzhiyun #endif 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */ 45*4882a593Smuzhiyun #define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */ 48*4882a593Smuzhiyun #define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */ 51*4882a593Smuzhiyun #define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */ 54*4882a593Smuzhiyun #define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */ 55*4882a593Smuzhiyun #define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */ 56*4882a593Smuzhiyun #define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */ 57*4882a593Smuzhiyun #define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */ 58*4882a593Smuzhiyun #define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */ 59*4882a593Smuzhiyun #define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */ 60*4882a593Smuzhiyun #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */ 63*4882a593Smuzhiyun #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */ 64*4882a593Smuzhiyun #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */ 65*4882a593Smuzhiyun #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */ 66*4882a593Smuzhiyun #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */ 67*4882a593Smuzhiyun #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */ 68*4882a593Smuzhiyun #define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */ 69*4882a593Smuzhiyun #define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */ 70*4882a593Smuzhiyun #define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */ 71*4882a593Smuzhiyun #define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */ 72*4882a593Smuzhiyun #define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */ 73*4882a593Smuzhiyun #define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */ 74*4882a593Smuzhiyun #define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */ 75*4882a593Smuzhiyun #define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */ 76*4882a593Smuzhiyun #define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */ 77*4882a593Smuzhiyun #define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */ 78*4882a593Smuzhiyun #define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */ 79*4882a593Smuzhiyun #define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */ 80*4882a593Smuzhiyun #define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */ 81*4882a593Smuzhiyun #define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */ 82*4882a593Smuzhiyun #define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */ 83*4882a593Smuzhiyun #define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */ 84*4882a593Smuzhiyun #define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */ 85*4882a593Smuzhiyun #define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */ 86*4882a593Smuzhiyun #define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #ifdef CONFIG_M5206e 89*4882a593Smuzhiyun #define MCFSIM_PAR (MCF_MBAR + 0xca) /* Pin Assignment */ 90*4882a593Smuzhiyun #else 91*4882a593Smuzhiyun #define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */ 92*4882a593Smuzhiyun #endif 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */ 95*4882a593Smuzhiyun #define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */ 98*4882a593Smuzhiyun #define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */ 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */ 101*4882a593Smuzhiyun #define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #if defined(CONFIG_NETtel) 104*4882a593Smuzhiyun #define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */ 105*4882a593Smuzhiyun #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ 106*4882a593Smuzhiyun #else 107*4882a593Smuzhiyun #define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */ 108*4882a593Smuzhiyun #define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */ 109*4882a593Smuzhiyun #endif 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* 112*4882a593Smuzhiyun * Define system peripheral IRQ usage. 113*4882a593Smuzhiyun */ 114*4882a593Smuzhiyun #define MCF_IRQ_I2C0 29 /* I2C, Level 5 */ 115*4882a593Smuzhiyun #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 116*4882a593Smuzhiyun #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 117*4882a593Smuzhiyun #define MCF_IRQ_UART0 73 /* UART0 */ 118*4882a593Smuzhiyun #define MCF_IRQ_UART1 74 /* UART1 */ 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* 121*4882a593Smuzhiyun * Generic GPIO 122*4882a593Smuzhiyun */ 123*4882a593Smuzhiyun #define MCFGPIO_PIN_MAX 8 124*4882a593Smuzhiyun #define MCFGPIO_IRQ_VECBASE -1 125*4882a593Smuzhiyun #define MCFGPIO_IRQ_MAX -1 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* 128*4882a593Smuzhiyun * Some symbol defines for the Parallel Port Pin Assignment Register 129*4882a593Smuzhiyun */ 130*4882a593Smuzhiyun #ifdef CONFIG_M5206e 131*4882a593Smuzhiyun #define MCFSIM_PAR_DREQ0 0x100 /* Set to select DREQ0 input */ 132*4882a593Smuzhiyun /* Clear to select T0 input */ 133*4882a593Smuzhiyun #define MCFSIM_PAR_DREQ1 0x200 /* Select DREQ1 input */ 134*4882a593Smuzhiyun /* Clear to select T0 output */ 135*4882a593Smuzhiyun #endif 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* 138*4882a593Smuzhiyun * Some symbol defines for the Interrupt Control Register 139*4882a593Smuzhiyun */ 140*4882a593Smuzhiyun #define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */ 141*4882a593Smuzhiyun #define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */ 142*4882a593Smuzhiyun #define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */ 143*4882a593Smuzhiyun #define MCFSIM_I2CICR MCFSIM_ICR11 /* I2C ICR */ 144*4882a593Smuzhiyun #define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */ 145*4882a593Smuzhiyun #define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */ 146*4882a593Smuzhiyun #ifdef CONFIG_M5206e 147*4882a593Smuzhiyun #define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */ 148*4882a593Smuzhiyun #define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */ 149*4882a593Smuzhiyun #endif 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* 152*4882a593Smuzhiyun * I2C Controller 153*4882a593Smuzhiyun */ 154*4882a593Smuzhiyun #define MCFI2C_BASE0 (MCF_MBAR + 0x1e0) 155*4882a593Smuzhiyun #define MCFI2C_SIZE0 0x40 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /****************************************************************************/ 158*4882a593Smuzhiyun #endif /* m5206sim_h */ 159