1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /****************************************************************************/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * m5407sim.h -- ColdFire 5407 System Integration Module support. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 2000, Lineo (www.lineo.com) 8*4882a593Smuzhiyun * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Modified by David W. Miller for the MCF5307 Eval Board. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /****************************************************************************/ 14*4882a593Smuzhiyun #ifndef m5407sim_h 15*4882a593Smuzhiyun #define m5407sim_h 16*4882a593Smuzhiyun /****************************************************************************/ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CPU_NAME "COLDFIRE(m5407)" 19*4882a593Smuzhiyun #define CPU_INSTR_PER_JIFFY 3 20*4882a593Smuzhiyun #define MCF_BUSCLK (MCF_CLK / 2) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #include <asm/m54xxacr.h> 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * Define the 5407 SIM register set addresses. 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ 28*4882a593Smuzhiyun #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ 29*4882a593Smuzhiyun #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ 30*4882a593Smuzhiyun #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/ 31*4882a593Smuzhiyun #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */ 32*4882a593Smuzhiyun #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */ 33*4882a593Smuzhiyun #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */ 34*4882a593Smuzhiyun #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ 35*4882a593Smuzhiyun #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ 36*4882a593Smuzhiyun #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ 37*4882a593Smuzhiyun #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */ 38*4882a593Smuzhiyun #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ 39*4882a593Smuzhiyun #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ 40*4882a593Smuzhiyun #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ 41*4882a593Smuzhiyun #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ 42*4882a593Smuzhiyun #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ 43*4882a593Smuzhiyun #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ 44*4882a593Smuzhiyun #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ 45*4882a593Smuzhiyun #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ 46*4882a593Smuzhiyun #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ 47*4882a593Smuzhiyun #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ 48*4882a593Smuzhiyun #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ 49*4882a593Smuzhiyun #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ 52*4882a593Smuzhiyun #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ 53*4882a593Smuzhiyun #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ 54*4882a593Smuzhiyun #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ 55*4882a593Smuzhiyun #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ 56*4882a593Smuzhiyun #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ 59*4882a593Smuzhiyun #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ 60*4882a593Smuzhiyun #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ 61*4882a593Smuzhiyun #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ 62*4882a593Smuzhiyun #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ 63*4882a593Smuzhiyun #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ 64*4882a593Smuzhiyun #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ 65*4882a593Smuzhiyun #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ 66*4882a593Smuzhiyun #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ 67*4882a593Smuzhiyun #define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */ 68*4882a593Smuzhiyun #define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */ 69*4882a593Smuzhiyun #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ 70*4882a593Smuzhiyun #define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */ 71*4882a593Smuzhiyun #define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */ 72*4882a593Smuzhiyun #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ 73*4882a593Smuzhiyun #define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */ 74*4882a593Smuzhiyun #define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */ 75*4882a593Smuzhiyun #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 78*4882a593Smuzhiyun #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ 79*4882a593Smuzhiyun #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ 80*4882a593Smuzhiyun #define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */ 81*4882a593Smuzhiyun #define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* 84*4882a593Smuzhiyun * Timer module. 85*4882a593Smuzhiyun */ 86*4882a593Smuzhiyun #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ 87*4882a593Smuzhiyun #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ 90*4882a593Smuzhiyun #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define MCFSIM_PADDR (MCF_MBAR + 0x244) 93*4882a593Smuzhiyun #define MCFSIM_PADAT (MCF_MBAR + 0x248) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* 96*4882a593Smuzhiyun * DMA unit base addresses. 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ 99*4882a593Smuzhiyun #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ 100*4882a593Smuzhiyun #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ 101*4882a593Smuzhiyun #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* 104*4882a593Smuzhiyun * Generic GPIO support 105*4882a593Smuzhiyun */ 106*4882a593Smuzhiyun #define MCFGPIO_PIN_MAX 16 107*4882a593Smuzhiyun #define MCFGPIO_IRQ_MAX -1 108*4882a593Smuzhiyun #define MCFGPIO_IRQ_VECBASE -1 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* 111*4882a593Smuzhiyun * Some symbol defines for the above... 112*4882a593Smuzhiyun */ 113*4882a593Smuzhiyun #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 114*4882a593Smuzhiyun #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ 115*4882a593Smuzhiyun #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ 116*4882a593Smuzhiyun #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */ 117*4882a593Smuzhiyun #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 118*4882a593Smuzhiyun #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ 119*4882a593Smuzhiyun #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ 120*4882a593Smuzhiyun #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ 121*4882a593Smuzhiyun #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 122*4882a593Smuzhiyun #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* 125*4882a593Smuzhiyun * Some symbol defines for the Parallel Port Pin Assignment Register 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun #define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ 128*4882a593Smuzhiyun /* Clear to select par I/O */ 129*4882a593Smuzhiyun #define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */ 130*4882a593Smuzhiyun /* Clear to select par I/O */ 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* 133*4882a593Smuzhiyun * Defines for the IRQPAR Register 134*4882a593Smuzhiyun */ 135*4882a593Smuzhiyun #define IRQ5_LEVEL4 0x80 136*4882a593Smuzhiyun #define IRQ3_LEVEL6 0x40 137*4882a593Smuzhiyun #define IRQ1_LEVEL2 0x20 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* 140*4882a593Smuzhiyun * Define system peripheral IRQ usage. 141*4882a593Smuzhiyun */ 142*4882a593Smuzhiyun #define MCF_IRQ_I2C0 29 /* I2C, Level 5 */ 143*4882a593Smuzhiyun #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 144*4882a593Smuzhiyun #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 145*4882a593Smuzhiyun #define MCF_IRQ_UART0 73 /* UART0 */ 146*4882a593Smuzhiyun #define MCF_IRQ_UART1 74 /* UART1 */ 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* 149*4882a593Smuzhiyun * I2C module 150*4882a593Smuzhiyun */ 151*4882a593Smuzhiyun #define MCFI2C_BASE0 (MCF_MBAR + 0x280) 152*4882a593Smuzhiyun #define MCFI2C_SIZE0 0x40 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /****************************************************************************/ 155*4882a593Smuzhiyun #endif /* m5407sim_h */ 156