1 // SPDX-License-Identifier: GPL-2.0
2
3 /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
4
5 #define pr_fmt(fmt) "nandc: " fmt
6
7 #include <linux/delay.h>
8 #include <linux/kernel.h>
9 #include <linux/slab.h>
10
11 #include "flash.h"
12 #include "flash_com.h"
13 #include "nandc.h"
14 #include "rkflash_debug.h"
15
16 #define FLASH_STRESS_TEST_EN 0
17
18 static u8 id_byte[MAX_FLASH_NUM][8];
19 static u8 die_cs_index[MAX_FLASH_NUM];
20 static u8 g_nand_max_die;
21 static u16 g_totle_block;
22 static u8 g_nand_flash_ecc_bits;
23 static u8 g_nand_idb_res_blk_num;
24 static u8 g_nand_ecc_en;
25
26 static struct NAND_PARA_INFO_T nand_para = {
27 2,
28 {0x98, 0xF1, 0, 0, 0, 0},
29 TOSHIBA,
30 1,
31 4,
32 64,
33 1,
34 1,
35 1024,
36 0x100,
37 LSB_0,
38 RR_NONE,
39 16,
40 40,
41 1,
42 0,
43 BBF_1,
44 MPM_0,
45 {0}
46 }; /* TC58NVG0S3HTA00 */
47
flash_read_id_raw(u8 cs,u8 * buf)48 static void flash_read_id_raw(u8 cs, u8 *buf)
49 {
50 u8 *ptr = (u8 *)buf;
51
52 nandc_flash_reset(cs);
53 nandc_flash_cs(cs);
54 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs));
55 nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
56 nandc_delayns(200);
57
58 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs));
59 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs));
60 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs));
61 ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs));
62 ptr[4] = nandc_readl(NANDC_CHIP_DATA(cs));
63 ptr[5] = nandc_readl(NANDC_CHIP_DATA(cs));
64 ptr[6] = nandc_readl(NANDC_CHIP_DATA(cs));
65 ptr[7] = nandc_readl(NANDC_CHIP_DATA(cs));
66
67 nandc_flash_de_cs(cs);
68 if (ptr[0] != 0xFF && ptr[0] && ptr[1] != 0xFF)
69 rkflash_print_error("No.%d FLASH ID:%x %x %x %x %x %x\n",
70 cs + 1, ptr[0], ptr[1], ptr[2],
71 ptr[3], ptr[4], ptr[5]);
72 }
73
flash_bch_sel(u8 bits)74 static void flash_bch_sel(u8 bits)
75 {
76 g_nand_flash_ecc_bits = bits;
77 nandc_bch_sel(bits);
78 }
79
flash_set_sector(u8 num)80 static void flash_set_sector(u8 num)
81 {
82 nand_para.sec_per_page = num;
83 }
84
flash_timing_cfg(u32 ahb_khz)85 static __maybe_unused void flash_timing_cfg(u32 ahb_khz)
86 {
87 nandc_time_cfg(nand_para.access_freq);
88 }
89
flash_read_cmd(u8 cs,u32 page_addr)90 static void flash_read_cmd(u8 cs, u32 page_addr)
91 {
92 nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs));
93 nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
94 nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
95 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
96 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs));
97 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs));
98 nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
99 }
100
flash_prog_first_cmd(u8 cs,u32 page_addr)101 static void flash_prog_first_cmd(u8 cs, u32 page_addr)
102 {
103 nandc_writel(PAGE_PROG_CMD >> 8, NANDC_CHIP_CMD(cs));
104 nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
105 nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
106 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
107 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs));
108 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs));
109 }
110
flash_erase_cmd(u8 cs,u32 page_addr)111 static void flash_erase_cmd(u8 cs, u32 page_addr)
112 {
113 nandc_writel(BLOCK_ERASE_CMD >> 8, NANDC_CHIP_CMD(cs));
114 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
115 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs));
116 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs));
117 nandc_writel(BLOCK_ERASE_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
118 }
119
flash_prog_second_cmd(u8 cs,u32 page_addr)120 static void flash_prog_second_cmd(u8 cs, u32 page_addr)
121 {
122 usleep_range(100, 120);
123 nandc_writel(PAGE_PROG_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
124 }
125
flash_read_status(u8 cs,u32 page_addr)126 static u32 flash_read_status(u8 cs, u32 page_addr)
127 {
128 nandc_writel(READ_STATUS_CMD, NANDC_CHIP_CMD(cs));
129 nandc_delayns(80);
130
131 return nandc_readl(NANDC_CHIP_DATA(cs));
132 }
133
flash_read_random_dataout_cmd(u8 cs,u32 col_addr)134 static void flash_read_random_dataout_cmd(u8 cs, u32 col_addr)
135 {
136 nandc_writel(READ_DP_OUT_CMD >> 8, NANDC_CHIP_CMD(cs));
137 nandc_writel(col_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
138 nandc_writel(col_addr >> 8, NANDC_CHIP_ADDR(cs));
139 nandc_writel(READ_DP_OUT_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
140 }
141
flash_read_ecc(u8 cs)142 static u32 flash_read_ecc(u8 cs)
143 {
144 u32 ecc0, ecc1;
145
146 nandc_writel(READ_ECC_STATUS_CMD, NANDC_CHIP_CMD(cs));
147 nandc_delayns(80);
148 ecc0 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF;
149 ecc1 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF;
150 if (ecc1 > ecc0)
151 ecc0 = ecc1;
152 ecc1 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF;
153 if (ecc1 > ecc0)
154 ecc0 = ecc1;
155 ecc1 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF;
156 if (ecc1 > ecc0)
157 ecc0 = ecc1;
158
159 return ecc0;
160 }
161
flash_read_page_raw(u8 cs,u32 page_addr,u32 * p_data,u32 * p_spare)162 static u32 flash_read_page_raw(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare)
163 {
164 u32 error_ecc_bits, ret;
165 u32 sec_per_page = nand_para.sec_per_page;
166 u32 nand_ecc = 0;
167
168 nandc_wait_flash_ready(cs);
169 nandc_flash_cs(cs);
170 flash_read_cmd(cs, page_addr);
171 nandc_wait_flash_ready(cs);
172 flash_read_random_dataout_cmd(cs, 0);
173 nandc_wait_flash_ready(cs);
174
175 error_ecc_bits = nandc_xfer_data(cs, NANDC_READ, sec_per_page,
176 p_data, p_spare);
177
178 nandc_flash_de_cs(cs);
179
180 if (error_ecc_bits != NAND_STS_ECC_ERR) {
181 if (error_ecc_bits >= (u32)nand_para.ecc_bits - 3) {
182 ret = NAND_STS_REFRESH;
183 } else {
184 ret = NAND_STS_OK;
185 if (g_nand_ecc_en) {
186 nand_ecc = flash_read_ecc(cs);
187
188 if (nand_ecc >= 6) {
189 rkflash_print_error("%s nand ecc %x ecc %d\n",
190 __func__, page_addr, nand_ecc);
191 ret = NAND_STS_REFRESH;
192 }
193 }
194 }
195 } else {
196 ret = NAND_STS_ECC_ERR;
197 }
198 if (nand_ecc > 4 || error_ecc_bits > 4)
199 rkflash_print_info("%s %x %x nandc ecc= %d, internal ecc= %d\n",
200 __func__, cs, page_addr, error_ecc_bits, nand_ecc);
201
202 return ret;
203 }
204
flash_read_page(u8 cs,u32 page_addr,u32 * p_data,u32 * p_spare)205 static u32 flash_read_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare)
206 {
207 u32 ret, i = 0;
208
209 ret = flash_read_page_raw(cs, page_addr, p_data, p_spare);
210 if (ret == NAND_STS_ECC_ERR) {
211 for (; i < 50; i++) {
212 ret = flash_read_page_raw(cs, page_addr, p_data, p_spare);
213 if (ret != NAND_STS_ECC_ERR) {
214 ret = NAND_STS_REFRESH;
215 break;
216 }
217 }
218 rkflash_print_error("%s %x err_ecc %d\n",
219 __func__, page_addr, ret);
220 }
221 rkflash_print_dio("%s %x %x retry=%x\n",
222 __func__, page_addr, p_data[0], i);
223
224 return ret;
225 }
226
flash_prog_page(u8 cs,u32 page_addr,u32 * p_data,u32 * p_spare)227 static u32 flash_prog_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare)
228 {
229 u32 status;
230 u32 sec_per_page = nand_para.sec_per_page;
231
232 rkflash_print_dio("%s %x %x\n", __func__, page_addr, p_data[0]);
233 nandc_wait_flash_ready(cs);
234 nandc_flash_cs(cs);
235 flash_prog_first_cmd(cs, page_addr);
236 nandc_xfer_data(cs, NANDC_WRITE, sec_per_page, p_data, p_spare);
237 flash_prog_second_cmd(cs, page_addr);
238 nandc_wait_flash_ready(cs);
239 status = flash_read_status(cs, page_addr);
240 nandc_flash_de_cs(cs);
241 status &= 0x01;
242 if (status)
243 rkflash_print_info("%s addr=%x status=%x\n",
244 __func__, page_addr, status);
245
246 return status;
247 }
248
flash_erase_block(u8 cs,u32 page_addr)249 static u32 flash_erase_block(u8 cs, u32 page_addr)
250 {
251 u32 status;
252
253 rkflash_print_dio("%s %x\n", __func__, page_addr);
254 nandc_wait_flash_ready(cs);
255 nandc_flash_cs(cs);
256 flash_erase_cmd(cs, page_addr);
257 nandc_wait_flash_ready(cs);
258 status = flash_read_status(cs, page_addr);
259 nandc_flash_de_cs(cs);
260 status &= 0x01;
261 if (status)
262 rkflash_print_info("%s pageadd=%x status=%x\n",
263 __func__, page_addr, status);
264
265 return status;
266 }
267
flash_read_spare(u8 cs,u32 page_addr,u8 * spare)268 static void flash_read_spare(u8 cs, u32 page_addr, u8 *spare)
269 {
270 u32 col = nand_para.sec_per_page << 9;
271
272 nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs));
273 nandc_writel(col, NANDC_CHIP_ADDR(cs));
274 nandc_writel(col >> 8, NANDC_CHIP_ADDR(cs));
275 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
276 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs));
277 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs));
278 nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
279
280 nandc_wait_flash_ready(cs);
281
282 *spare = nandc_readl(NANDC_CHIP_DATA(cs));
283 }
284
285 /*
286 * Read the 1st page's 1st spare byte of a phy_blk
287 * If not FF, it's bad blk
288 */
flash_get_bad_blk_list(u16 * table,u32 die)289 static s32 flash_get_bad_blk_list(u16 *table, u32 die)
290 {
291 u16 blk;
292 u32 bad_cnt, page_addr0, page_addr1, page_addr2;
293 u32 blk_per_die;
294 u8 bad_flag0, bad_flag1, bad_flag2;
295
296 bad_cnt = 0;
297 blk_per_die = nand_para.plane_per_die * nand_para.blk_per_plane;
298 for (blk = 0; blk < blk_per_die; blk++) {
299 bad_flag0 = 0xFF;
300 bad_flag1 = 0xFF;
301 bad_flag2 = 0xFF;
302 page_addr0 = (blk + blk_per_die * die) *
303 nand_para.page_per_blk + 0;
304 page_addr1 = page_addr0 + 1;
305 page_addr2 = page_addr0 + nand_para.page_per_blk - 1;
306 flash_read_spare(die, page_addr0, &bad_flag0);
307 flash_read_spare(die, page_addr1, &bad_flag1);
308 flash_read_spare(die, page_addr2, &bad_flag2);
309 if (bad_flag0 != 0xFF ||
310 bad_flag1 != 0xFF ||
311 bad_flag2 != 0xFF) {
312 table[bad_cnt++] = blk;
313 rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk);
314 }
315 }
316 return bad_cnt;
317 }
318
flash_die_info_init(void)319 static void flash_die_info_init(void)
320 {
321 u32 cs;
322
323 g_nand_max_die = 0;
324 for (cs = 0; cs < MAX_FLASH_NUM; cs++) {
325 if (nand_para.nand_id[1] == id_byte[cs][1]) {
326 die_cs_index[g_nand_max_die] = cs;
327 g_nand_max_die++;
328 }
329 }
330 g_totle_block = g_nand_max_die * nand_para.plane_per_die *
331 nand_para.blk_per_plane;
332 }
333
flash_show_info(void)334 static void flash_show_info(void)
335 {
336 rkflash_print_info("No.0 FLASH ID: %x %x %x %x %x %x\n",
337 nand_para.nand_id[0],
338 nand_para.nand_id[1],
339 nand_para.nand_id[2],
340 nand_para.nand_id[3],
341 nand_para.nand_id[4],
342 nand_para.nand_id[5]);
343 rkflash_print_info("die_per_chip: %x\n", nand_para.die_per_chip);
344 rkflash_print_info("sec_per_page: %x\n", nand_para.sec_per_page);
345 rkflash_print_info("page_per_blk: %x\n", nand_para.page_per_blk);
346 rkflash_print_info("cell: %x\n", nand_para.cell);
347 rkflash_print_info("plane_per_die: %x\n", nand_para.plane_per_die);
348 rkflash_print_info("blk_per_plane: %x\n", nand_para.blk_per_plane);
349 rkflash_print_info("TotleBlock: %x\n", g_totle_block);
350 rkflash_print_info("die gap: %x\n", nand_para.die_gap);
351 rkflash_print_info("lsb_mode: %x\n", nand_para.lsb_mode);
352 rkflash_print_info("read_retry_mode: %x\n", nand_para.read_retry_mode);
353 rkflash_print_info("ecc_bits: %x\n", nand_para.ecc_bits);
354 rkflash_print_info("Use ecc_bits: %x\n", g_nand_flash_ecc_bits);
355 rkflash_print_info("access_freq: %x\n", nand_para.access_freq);
356 rkflash_print_info("opt_mode: %x\n", nand_para.opt_mode);
357
358 rkflash_print_info("Cache read enable: %x\n",
359 nand_para.operation_opt & NAND_CACHE_READ_EN ? 1 : 0);
360 rkflash_print_info("Cache random read enable: %x\n",
361 nand_para.operation_opt &
362 NAND_CACHE_RANDOM_READ_EN ? 1 : 0);
363 rkflash_print_info("Cache prog enable: %x\n",
364 nand_para.operation_opt & NAND_CACHE_PROG_EN ? 1 : 0);
365 rkflash_print_info("multi read enable: %x\n",
366 nand_para.operation_opt & NAND_MULTI_READ_EN ? 1 : 0);
367
368 rkflash_print_info("multi prog enable: %x\n",
369 nand_para.operation_opt & NAND_MULTI_PROG_EN ? 1 : 0);
370 rkflash_print_info("interleave enable: %x\n",
371 nand_para.operation_opt & NAND_INTERLEAVE_EN ? 1 : 0);
372
373 rkflash_print_info("read retry enable: %x\n",
374 nand_para.operation_opt & NAND_READ_RETRY_EN ? 1 : 0);
375 rkflash_print_info("randomizer enable: %x\n",
376 nand_para.operation_opt & NAND_RANDOMIZER_EN ? 1 : 0);
377
378 rkflash_print_info("SDR enable: %x\n",
379 nand_para.operation_opt & NAND_SDR_EN ? 1 : 0);
380 rkflash_print_info("ONFI enable: %x\n",
381 nand_para.operation_opt & NAND_ONFI_EN ? 1 : 0);
382 rkflash_print_info("TOGGLE enable: %x\n",
383 nand_para.operation_opt & NAND_TOGGLE_EN ? 1 : 0);
384
385 rkflash_print_info("g_nand_idb_res_blk_num: %x\n", g_nand_idb_res_blk_num);
386 }
387
flash_ftl_ops_init(void)388 static void flash_ftl_ops_init(void)
389 {
390 u8 nandc_ver = nandc_get_version();
391
392 /* para init */
393 g_nand_phy_info.nand_type = nand_para.cell;
394 g_nand_phy_info.die_num = nand_para.die_per_chip;
395 g_nand_phy_info.plane_per_die = nand_para.plane_per_die;
396 g_nand_phy_info.blk_per_plane = nand_para.blk_per_plane;
397 g_nand_phy_info.page_per_blk = nand_para.page_per_blk;
398 g_nand_phy_info.page_per_slc_blk = nand_para.page_per_blk /
399 nand_para.cell;
400 g_nand_phy_info.byte_per_sec = 512;
401 g_nand_phy_info.sec_per_page = nand_para.sec_per_page;
402 g_nand_phy_info.sec_per_blk = nand_para.sec_per_page *
403 nand_para.page_per_blk;
404 g_nand_phy_info.reserved_blk = 8;
405 g_nand_phy_info.blk_per_die = nand_para.plane_per_die *
406 nand_para.blk_per_plane;
407 g_nand_phy_info.ecc_bits = nand_para.ecc_bits;
408
409 /* driver register */
410 g_nand_ops.get_bad_blk_list = flash_get_bad_blk_list;
411 g_nand_ops.erase_blk = flash_erase_block;
412 g_nand_ops.prog_page = flash_prog_page;
413 g_nand_ops.read_page = flash_read_page;
414 if (nandc_ver == 9) {
415 g_nand_ops.bch_sel = flash_bch_sel;
416 g_nand_ops.set_sec_num = flash_set_sector;
417 }
418 }
419
nandc_flash_reset(u8 cs)420 void nandc_flash_reset(u8 cs)
421 {
422 nandc_flash_cs(cs);
423 nandc_writel(RESET_CMD, NANDC_CHIP_CMD(cs));
424 nandc_wait_flash_ready(cs);
425 nandc_flash_de_cs(cs);
426 }
427
nandc_flash_init(void __iomem * nandc_addr)428 u32 nandc_flash_init(void __iomem *nandc_addr)
429 {
430 u32 cs;
431
432 rkflash_print_error("...%s enter...\n", __func__);
433 g_nand_idb_res_blk_num = MAX_IDB_RESERVED_BLOCK;
434 g_nand_ecc_en = 0;
435
436 nandc_init(nandc_addr);
437
438 for (cs = 0; cs < MAX_FLASH_NUM; cs++) {
439 flash_read_id_raw(cs, id_byte[cs]);
440 if (cs == 0) {
441 if (id_byte[0][0] == 0xFF ||
442 id_byte[0][0] == 0 ||
443 id_byte[0][1] == 0xFF)
444 return FTL_NO_FLASH;
445 if (id_byte[0][1] != 0xF1 &&
446 id_byte[0][1] != 0xDA &&
447 id_byte[0][1] != 0xD1 &&
448 id_byte[0][1] != 0x95 &&
449 id_byte[0][1] != 0xDC &&
450 id_byte[0][1] != 0xD3 &&
451 id_byte[0][1] != 0x48 &&
452 id_byte[0][1] != 0xA1 &&
453 id_byte[0][1] != 0xAA &&
454 id_byte[0][1] != 0xAC &&
455 id_byte[0][1] != 0x6A) {
456 pr_err("The device not support yet!\n");
457
458 return FTL_UNSUPPORTED_FLASH;
459 }
460 }
461 }
462 if (id_byte[0][0] == 0x98 && (id_byte[0][4] & 0x80))
463 g_nand_ecc_en = 1;
464 nand_para.nand_id[1] = id_byte[0][1];
465 if (id_byte[0][1] == 0xDA || id_byte[0][1] == 0xAA || id_byte[0][1] == 0x6A) {
466 nand_para.plane_per_die = 2;
467 nand_para.nand_id[1] = id_byte[0][1];
468 } else if (id_byte[0][1] == 0xDC || id_byte[0][1] == 0xAC) {
469 nand_para.nand_id[1] = id_byte[0][1];
470 if ((id_byte[0][0] == 0x2C && id_byte[0][3] == 0xA6) ||
471 (id_byte[0][0] == 0xC2 && id_byte[0][3] == 0xA2)) {
472 nand_para.plane_per_die = 2;
473 nand_para.sec_per_page = 8;
474 } else if ((id_byte[0][0] == 0x98 && id_byte[0][3] == 0x26) ||
475 (id_byte[0][0] == 0xC8 && ((id_byte[0][3] & 0x3) == 1))) {
476 nand_para.blk_per_plane = 1024;
477 nand_para.sec_per_page = 8;
478 nand_para.plane_per_die = 2;
479 } else {
480 nand_para.plane_per_die = 2;
481 nand_para.blk_per_plane = 2048;
482 }
483 } else if (id_byte[0][1] == 0x48) {
484 nand_para.sec_per_page = 8;
485 nand_para.page_per_blk = 128;
486 nand_para.plane_per_die = 2;
487 nand_para.blk_per_plane = 2048;
488 } else if (id_byte[0][1] == 0xD3) {
489 nand_para.sec_per_page = 8;
490 nand_para.page_per_blk = 64;
491 nand_para.plane_per_die = 2;
492 nand_para.blk_per_plane = 2048;
493 }
494 flash_die_info_init();
495 flash_bch_sel(nand_para.ecc_bits);
496 flash_show_info();
497 flash_ftl_ops_init();
498
499 return 0;
500 }
501
nandc_flash_get_id(u8 cs,void * buf)502 void nandc_flash_get_id(u8 cs, void *buf)
503 {
504 memcpy(buf, id_byte[cs], 5);
505 }
506
nandc_flash_deinit(void)507 u32 nandc_flash_deinit(void)
508 {
509 return 0;
510 }
511