1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Atmel SMC (Static Memory Controller) register offsets and bit definitions. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Atmel 6*4882a593Smuzhiyun * Copyright (C) 2014 Free Electrons 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Boris Brezillon <boris.brezillon@free-electrons.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _LINUX_MFD_SYSCON_ATMEL_SMC_H_ 12*4882a593Smuzhiyun #define _LINUX_MFD_SYSCON_ATMEL_SMC_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <linux/kernel.h> 15*4882a593Smuzhiyun #include <linux/of.h> 16*4882a593Smuzhiyun #include <linux/regmap.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) 19*4882a593Smuzhiyun #define ATMEL_HSMC_SETUP(layout, cs) \ 20*4882a593Smuzhiyun ((layout)->timing_regs_offset + ((cs) * 0x14)) 21*4882a593Smuzhiyun #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) 22*4882a593Smuzhiyun #define ATMEL_HSMC_PULSE(layout, cs) \ 23*4882a593Smuzhiyun ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4) 24*4882a593Smuzhiyun #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) 25*4882a593Smuzhiyun #define ATMEL_HSMC_CYCLE(layout, cs) \ 26*4882a593Smuzhiyun ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x8) 27*4882a593Smuzhiyun #define ATMEL_SMC_NWE_SHIFT 0 28*4882a593Smuzhiyun #define ATMEL_SMC_NCS_WR_SHIFT 8 29*4882a593Smuzhiyun #define ATMEL_SMC_NRD_SHIFT 16 30*4882a593Smuzhiyun #define ATMEL_SMC_NCS_RD_SHIFT 24 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define ATMEL_SMC_MODE(cs) (((cs) * 0x10) + 0xc) 33*4882a593Smuzhiyun #define ATMEL_HSMC_MODE(layout, cs) \ 34*4882a593Smuzhiyun ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x10) 35*4882a593Smuzhiyun #define ATMEL_SMC_MODE_READMODE_MASK BIT(0) 36*4882a593Smuzhiyun #define ATMEL_SMC_MODE_READMODE_NCS (0 << 0) 37*4882a593Smuzhiyun #define ATMEL_SMC_MODE_READMODE_NRD (1 << 0) 38*4882a593Smuzhiyun #define ATMEL_SMC_MODE_WRITEMODE_MASK BIT(1) 39*4882a593Smuzhiyun #define ATMEL_SMC_MODE_WRITEMODE_NCS (0 << 1) 40*4882a593Smuzhiyun #define ATMEL_SMC_MODE_WRITEMODE_NWE (1 << 1) 41*4882a593Smuzhiyun #define ATMEL_SMC_MODE_EXNWMODE_MASK GENMASK(5, 4) 42*4882a593Smuzhiyun #define ATMEL_SMC_MODE_EXNWMODE_DISABLE (0 << 4) 43*4882a593Smuzhiyun #define ATMEL_SMC_MODE_EXNWMODE_FROZEN (2 << 4) 44*4882a593Smuzhiyun #define ATMEL_SMC_MODE_EXNWMODE_READY (3 << 4) 45*4882a593Smuzhiyun #define ATMEL_SMC_MODE_BAT_MASK BIT(8) 46*4882a593Smuzhiyun #define ATMEL_SMC_MODE_BAT_SELECT (0 << 8) 47*4882a593Smuzhiyun #define ATMEL_SMC_MODE_BAT_WRITE (1 << 8) 48*4882a593Smuzhiyun #define ATMEL_SMC_MODE_DBW_MASK GENMASK(13, 12) 49*4882a593Smuzhiyun #define ATMEL_SMC_MODE_DBW_8 (0 << 12) 50*4882a593Smuzhiyun #define ATMEL_SMC_MODE_DBW_16 (1 << 12) 51*4882a593Smuzhiyun #define ATMEL_SMC_MODE_DBW_32 (2 << 12) 52*4882a593Smuzhiyun #define ATMEL_SMC_MODE_TDF_MASK GENMASK(19, 16) 53*4882a593Smuzhiyun #define ATMEL_SMC_MODE_TDF(x) (((x) - 1) << 16) 54*4882a593Smuzhiyun #define ATMEL_SMC_MODE_TDF_MAX 16 55*4882a593Smuzhiyun #define ATMEL_SMC_MODE_TDF_MIN 1 56*4882a593Smuzhiyun #define ATMEL_SMC_MODE_TDFMODE_OPTIMIZED BIT(20) 57*4882a593Smuzhiyun #define ATMEL_SMC_MODE_PMEN BIT(24) 58*4882a593Smuzhiyun #define ATMEL_SMC_MODE_PS_MASK GENMASK(29, 28) 59*4882a593Smuzhiyun #define ATMEL_SMC_MODE_PS_4 (0 << 28) 60*4882a593Smuzhiyun #define ATMEL_SMC_MODE_PS_8 (1 << 28) 61*4882a593Smuzhiyun #define ATMEL_SMC_MODE_PS_16 (2 << 28) 62*4882a593Smuzhiyun #define ATMEL_SMC_MODE_PS_32 (3 << 28) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define ATMEL_HSMC_TIMINGS(layout, cs) \ 65*4882a593Smuzhiyun ((layout)->timing_regs_offset + ((cs) * 0x14) + 0xc) 66*4882a593Smuzhiyun #define ATMEL_HSMC_TIMINGS_OCMS BIT(12) 67*4882a593Smuzhiyun #define ATMEL_HSMC_TIMINGS_RBNSEL(x) ((x) << 28) 68*4882a593Smuzhiyun #define ATMEL_HSMC_TIMINGS_NFSEL BIT(31) 69*4882a593Smuzhiyun #define ATMEL_HSMC_TIMINGS_TCLR_SHIFT 0 70*4882a593Smuzhiyun #define ATMEL_HSMC_TIMINGS_TADL_SHIFT 4 71*4882a593Smuzhiyun #define ATMEL_HSMC_TIMINGS_TAR_SHIFT 8 72*4882a593Smuzhiyun #define ATMEL_HSMC_TIMINGS_TRR_SHIFT 16 73*4882a593Smuzhiyun #define ATMEL_HSMC_TIMINGS_TWB_SHIFT 24 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun struct atmel_hsmc_reg_layout { 76*4882a593Smuzhiyun unsigned int timing_regs_offset; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /** 80*4882a593Smuzhiyun * struct atmel_smc_cs_conf - SMC CS config as described in the datasheet. 81*4882a593Smuzhiyun * @setup: NCS/NWE/NRD setup timings (not applicable to at91rm9200) 82*4882a593Smuzhiyun * @pulse: NCS/NWE/NRD pulse timings (not applicable to at91rm9200) 83*4882a593Smuzhiyun * @cycle: NWE/NRD cycle timings (not applicable to at91rm9200) 84*4882a593Smuzhiyun * @timings: advanced NAND related timings (only applicable to HSMC) 85*4882a593Smuzhiyun * @mode: all kind of config parameters (see the fields definition above). 86*4882a593Smuzhiyun * The mode fields are different on at91rm9200 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun struct atmel_smc_cs_conf { 89*4882a593Smuzhiyun u32 setup; 90*4882a593Smuzhiyun u32 pulse; 91*4882a593Smuzhiyun u32 cycle; 92*4882a593Smuzhiyun u32 timings; 93*4882a593Smuzhiyun u32 mode; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf); 97*4882a593Smuzhiyun int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf, 98*4882a593Smuzhiyun unsigned int shift, 99*4882a593Smuzhiyun unsigned int ncycles); 100*4882a593Smuzhiyun int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf, 101*4882a593Smuzhiyun unsigned int shift, unsigned int ncycles); 102*4882a593Smuzhiyun int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf, 103*4882a593Smuzhiyun unsigned int shift, unsigned int ncycles); 104*4882a593Smuzhiyun int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf, 105*4882a593Smuzhiyun unsigned int shift, unsigned int ncycles); 106*4882a593Smuzhiyun void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs, 107*4882a593Smuzhiyun const struct atmel_smc_cs_conf *conf); 108*4882a593Smuzhiyun void atmel_hsmc_cs_conf_apply(struct regmap *regmap, 109*4882a593Smuzhiyun const struct atmel_hsmc_reg_layout *reglayout, 110*4882a593Smuzhiyun int cs, const struct atmel_smc_cs_conf *conf); 111*4882a593Smuzhiyun void atmel_smc_cs_conf_get(struct regmap *regmap, int cs, 112*4882a593Smuzhiyun struct atmel_smc_cs_conf *conf); 113*4882a593Smuzhiyun void atmel_hsmc_cs_conf_get(struct regmap *regmap, 114*4882a593Smuzhiyun const struct atmel_hsmc_reg_layout *reglayout, 115*4882a593Smuzhiyun int cs, struct atmel_smc_cs_conf *conf); 116*4882a593Smuzhiyun const struct atmel_hsmc_reg_layout * 117*4882a593Smuzhiyun atmel_hsmc_get_reg_layout(struct device_node *np); 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */ 120