1 /*
2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 #include <common.h>
8 #include <linux/delay.h>
9
10 #include "flash.h"
11 #include "flash_com.h"
12 #include "nandc.h"
13 #include "rkflash_debug.h"
14
15 #define FLASH_STRESS_TEST_EN 0
16
17 static u8 id_byte[MAX_FLASH_NUM][8];
18 static u8 die_cs_index[MAX_FLASH_NUM];
19 static u8 g_nand_max_die;
20 static u16 g_totle_block;
21 static u8 g_nand_flash_ecc_bits;
22 static u8 g_nand_idb_res_blk_num;
23 static u8 g_nand_ecc_en;
24
25 static struct NAND_PARA_INFO_T nand_para = {
26 2,
27 {0x98, 0xF1, 0, 0, 0, 0},
28 TOSHIBA,
29 1,
30 4,
31 64,
32 1,
33 1,
34 1024,
35 0x100,
36 LSB_0,
37 RR_NONE,
38 16,
39 40,
40 1,
41 0,
42 BBF_1,
43 MPM_0,
44 {0}
45 }; /* TC58NVG0S3HTA00 */
46
flash_read_id_raw(u8 cs,u8 * buf)47 static void flash_read_id_raw(u8 cs, u8 *buf)
48 {
49 u8 *ptr = (u8 *)buf;
50
51 nandc_flash_reset(cs);
52 nandc_flash_cs(cs);
53 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs));
54 nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
55 nandc_delayns(200);
56
57 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs));
58 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs));
59 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs));
60 ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs));
61 ptr[4] = nandc_readl(NANDC_CHIP_DATA(cs));
62 ptr[5] = nandc_readl(NANDC_CHIP_DATA(cs));
63 ptr[6] = nandc_readl(NANDC_CHIP_DATA(cs));
64 ptr[7] = nandc_readl(NANDC_CHIP_DATA(cs));
65
66 nandc_flash_de_cs(cs);
67 if (ptr[0] != 0xFF && ptr[0] && ptr[1] != 0xFF)
68 rkflash_print_error("No.%d FLASH ID:%x %x %x %x %x %x\n",
69 cs + 1, ptr[0], ptr[1], ptr[2],
70 ptr[3], ptr[4], ptr[5]);
71 }
72
flash_bch_sel(u8 bits)73 static void flash_bch_sel(u8 bits)
74 {
75 g_nand_flash_ecc_bits = bits;
76 nandc_bch_sel(bits);
77 }
78
flash_set_sector(u8 num)79 static void flash_set_sector(u8 num)
80 {
81 nand_para.sec_per_page = num;
82 }
83
flash_timing_cfg(u32 ahb_khz)84 static __maybe_unused void flash_timing_cfg(u32 ahb_khz)
85 {
86 nandc_time_cfg(nand_para.access_freq);
87 }
88
flash_read_cmd(u8 cs,u32 page_addr)89 static void flash_read_cmd(u8 cs, u32 page_addr)
90 {
91 nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs));
92 nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
93 nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
94 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
95 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs));
96 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs));
97 nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
98 }
99
flash_prog_first_cmd(u8 cs,u32 page_addr)100 static void flash_prog_first_cmd(u8 cs, u32 page_addr)
101 {
102 nandc_writel(PAGE_PROG_CMD >> 8, NANDC_CHIP_CMD(cs));
103 nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
104 nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
105 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
106 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs));
107 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs));
108 }
109
flash_erase_cmd(u8 cs,u32 page_addr)110 static void flash_erase_cmd(u8 cs, u32 page_addr)
111 {
112 nandc_writel(BLOCK_ERASE_CMD >> 8, NANDC_CHIP_CMD(cs));
113 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
114 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs));
115 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs));
116 nandc_writel(BLOCK_ERASE_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
117 }
118
flash_prog_second_cmd(u8 cs,u32 page_addr)119 static void flash_prog_second_cmd(u8 cs, u32 page_addr)
120 {
121 udelay(100);
122 nandc_writel(PAGE_PROG_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
123 }
124
flash_read_status(u8 cs,u32 page_addr)125 static u32 flash_read_status(u8 cs, u32 page_addr)
126 {
127 nandc_writel(READ_STATUS_CMD, NANDC_CHIP_CMD(cs));
128 nandc_delayns(80);
129
130 return nandc_readl(NANDC_CHIP_DATA(cs));
131 }
132
flash_read_random_dataout_cmd(u8 cs,u32 col_addr)133 static void flash_read_random_dataout_cmd(u8 cs, u32 col_addr)
134 {
135 nandc_writel(READ_DP_OUT_CMD >> 8, NANDC_CHIP_CMD(cs));
136 nandc_writel(col_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
137 nandc_writel(col_addr >> 8, NANDC_CHIP_ADDR(cs));
138 nandc_writel(READ_DP_OUT_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
139 }
140
flash_read_ecc(u8 cs)141 static u32 flash_read_ecc(u8 cs)
142 {
143 u32 ecc0, ecc1;
144
145 nandc_writel(READ_ECC_STATUS_CMD, NANDC_CHIP_CMD(cs));
146 nandc_delayns(80);
147 ecc0 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF;
148 ecc1 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF;
149 if (ecc1 > ecc0)
150 ecc0 = ecc1;
151 ecc1 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF;
152 if (ecc1 > ecc0)
153 ecc0 = ecc1;
154 ecc1 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF;
155 if (ecc1 > ecc0)
156 ecc0 = ecc1;
157
158 return ecc0;
159 }
160
flash_read_page_raw(u8 cs,u32 page_addr,u32 * p_data,u32 * p_spare)161 static u32 flash_read_page_raw(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare)
162 {
163 u32 error_ecc_bits, ret;
164 u32 sec_per_page = nand_para.sec_per_page;
165 u32 nand_ecc = 0;
166
167 nandc_wait_flash_ready(cs);
168 nandc_flash_cs(cs);
169 flash_read_cmd(cs, page_addr);
170 nandc_wait_flash_ready(cs);
171 flash_read_random_dataout_cmd(cs, 0);
172 nandc_wait_flash_ready(cs);
173
174 error_ecc_bits = nandc_xfer_data(cs, NANDC_READ, sec_per_page,
175 p_data, p_spare);
176
177 nandc_flash_de_cs(cs);
178
179 if (error_ecc_bits != NAND_STS_ECC_ERR) {
180 if (error_ecc_bits >= (u32)nand_para.ecc_bits - 3) {
181 ret = NAND_STS_REFRESH;
182 } else {
183 ret = NAND_STS_OK;
184 if (g_nand_ecc_en) {
185 nand_ecc = flash_read_ecc(cs);
186
187 if (nand_ecc >= 6) {
188 rkflash_print_error("%s nand ecc %x ecc %d\n",
189 __func__, page_addr, nand_ecc);
190 ret = NAND_STS_REFRESH;
191 }
192 }
193 }
194 } else {
195 ret = NAND_STS_ECC_ERR;
196 }
197 if (nand_ecc > 4 || error_ecc_bits > 4)
198 rkflash_print_info("%s %x %x nandc ecc= %d, internal ecc= %d\n",
199 __func__, cs, page_addr, error_ecc_bits, nand_ecc);
200
201 return ret;
202 }
203
flash_read_page(u8 cs,u32 page_addr,u32 * p_data,u32 * p_spare)204 static u32 flash_read_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare)
205 {
206 u32 ret, i = 0;
207
208 ret = flash_read_page_raw(cs, page_addr, p_data, p_spare);
209 if (ret == NAND_STS_ECC_ERR) {
210 for (; i < 50; i++) {
211 ret = flash_read_page_raw(cs, page_addr, p_data, p_spare);
212 if (ret != NAND_STS_ECC_ERR) {
213 ret = NAND_STS_REFRESH;
214 break;
215 }
216 }
217 rkflash_print_error("%s %x err_ecc %d\n",
218 __func__, page_addr, ret);
219 }
220 rkflash_print_dio("%s %x %x retry=%x\n",
221 __func__, page_addr, p_data[0], i);
222
223 return ret;
224 }
225
flash_prog_page(u8 cs,u32 page_addr,u32 * p_data,u32 * p_spare)226 static u32 flash_prog_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare)
227 {
228 u32 status;
229 u32 sec_per_page = nand_para.sec_per_page;
230
231 rkflash_print_dio("%s %x %x\n", __func__, page_addr, p_data[0]);
232 nandc_wait_flash_ready(cs);
233 nandc_flash_cs(cs);
234 flash_prog_first_cmd(cs, page_addr);
235 nandc_xfer_data(cs, NANDC_WRITE, sec_per_page, p_data, p_spare);
236 flash_prog_second_cmd(cs, page_addr);
237 nandc_wait_flash_ready(cs);
238 status = flash_read_status(cs, page_addr);
239 nandc_flash_de_cs(cs);
240 status &= 0x01;
241 if (status)
242 rkflash_print_info("%s addr=%x status=%x\n",
243 __func__, page_addr, status);
244
245 return status;
246 }
247
flash_erase_block(u8 cs,u32 page_addr)248 static u32 flash_erase_block(u8 cs, u32 page_addr)
249 {
250 u32 status;
251
252 rkflash_print_dio("%s %x\n", __func__, page_addr);
253 nandc_wait_flash_ready(cs);
254 nandc_flash_cs(cs);
255 flash_erase_cmd(cs, page_addr);
256 nandc_wait_flash_ready(cs);
257 status = flash_read_status(cs, page_addr);
258 nandc_flash_de_cs(cs);
259 status &= 0x01;
260 if (status)
261 rkflash_print_info("%s pageadd=%x status=%x\n",
262 __func__, page_addr, status);
263
264 return status;
265 }
266
flash_read_spare(u8 cs,u32 page_addr,u8 * spare)267 static void flash_read_spare(u8 cs, u32 page_addr, u8 *spare)
268 {
269 u32 col = nand_para.sec_per_page << 9;
270
271 nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs));
272 nandc_writel(col, NANDC_CHIP_ADDR(cs));
273 nandc_writel(col >> 8, NANDC_CHIP_ADDR(cs));
274 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
275 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs));
276 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs));
277 nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
278
279 nandc_wait_flash_ready(cs);
280
281 *spare = nandc_readl(NANDC_CHIP_DATA(cs));
282 }
283
284 /*
285 * Read the 1st page's 1st spare byte of a phy_blk
286 * If not FF, it's bad blk
287 */
flash_get_bad_blk_list(u16 * table,u32 die)288 static s32 flash_get_bad_blk_list(u16 *table, u32 die)
289 {
290 u16 blk;
291 u32 bad_cnt, page_addr0, page_addr1, page_addr2;
292 u32 blk_per_die;
293 u8 bad_flag0, bad_flag1, bad_flag2;
294
295 bad_cnt = 0;
296 blk_per_die = nand_para.plane_per_die * nand_para.blk_per_plane;
297 for (blk = 0; blk < blk_per_die; blk++) {
298 bad_flag0 = 0xFF;
299 bad_flag1 = 0xFF;
300 bad_flag2 = 0xFF;
301 page_addr0 = (blk + blk_per_die * die) *
302 nand_para.page_per_blk + 0;
303 page_addr1 = page_addr0 + 1;
304 page_addr2 = page_addr0 + nand_para.page_per_blk - 1;
305 flash_read_spare(die, page_addr0, &bad_flag0);
306 flash_read_spare(die, page_addr1, &bad_flag1);
307 flash_read_spare(die, page_addr2, &bad_flag2);
308 if (bad_flag0 != 0xFF ||
309 bad_flag1 != 0xFF ||
310 bad_flag2 != 0xFF) {
311 table[bad_cnt++] = blk;
312 rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk);
313 }
314 }
315 return bad_cnt;
316 }
317
flash_die_info_init(void)318 static void flash_die_info_init(void)
319 {
320 u32 cs;
321
322 g_nand_max_die = 0;
323 for (cs = 0; cs < MAX_FLASH_NUM; cs++) {
324 if (nand_para.nand_id[1] == id_byte[cs][1]) {
325 die_cs_index[g_nand_max_die] = cs;
326 g_nand_max_die++;
327 }
328 }
329 g_totle_block = g_nand_max_die * nand_para.plane_per_die *
330 nand_para.blk_per_plane;
331 }
332
flash_show_info(void)333 static void flash_show_info(void)
334 {
335 rkflash_print_info("No.0 FLASH ID: %x %x %x %x %x %x\n",
336 nand_para.nand_id[0],
337 nand_para.nand_id[1],
338 nand_para.nand_id[2],
339 nand_para.nand_id[3],
340 nand_para.nand_id[4],
341 nand_para.nand_id[5]);
342 rkflash_print_info("die_per_chip: %x\n", nand_para.die_per_chip);
343 rkflash_print_info("sec_per_page: %x\n", nand_para.sec_per_page);
344 rkflash_print_info("page_per_blk: %x\n", nand_para.page_per_blk);
345 rkflash_print_info("cell: %x\n", nand_para.cell);
346 rkflash_print_info("plane_per_die: %x\n", nand_para.plane_per_die);
347 rkflash_print_info("blk_per_plane: %x\n", nand_para.blk_per_plane);
348 rkflash_print_info("TotleBlock: %x\n", g_totle_block);
349 rkflash_print_info("die gap: %x\n", nand_para.die_gap);
350 rkflash_print_info("lsb_mode: %x\n", nand_para.lsb_mode);
351 rkflash_print_info("read_retry_mode: %x\n", nand_para.read_retry_mode);
352 rkflash_print_info("ecc_bits: %x\n", nand_para.ecc_bits);
353 rkflash_print_info("Use ecc_bits: %x\n", g_nand_flash_ecc_bits);
354 rkflash_print_info("access_freq: %x\n", nand_para.access_freq);
355 rkflash_print_info("opt_mode: %x\n", nand_para.opt_mode);
356
357 rkflash_print_info("Cache read enable: %x\n",
358 nand_para.operation_opt & NAND_CACHE_READ_EN ? 1 : 0);
359 rkflash_print_info("Cache random read enable: %x\n",
360 nand_para.operation_opt &
361 NAND_CACHE_RANDOM_READ_EN ? 1 : 0);
362 rkflash_print_info("Cache prog enable: %x\n",
363 nand_para.operation_opt & NAND_CACHE_PROG_EN ? 1 : 0);
364 rkflash_print_info("multi read enable: %x\n",
365 nand_para.operation_opt & NAND_MULTI_READ_EN ? 1 : 0);
366
367 rkflash_print_info("multi prog enable: %x\n",
368 nand_para.operation_opt & NAND_MULTI_PROG_EN ? 1 : 0);
369 rkflash_print_info("interleave enable: %x\n",
370 nand_para.operation_opt & NAND_INTERLEAVE_EN ? 1 : 0);
371
372 rkflash_print_info("read retry enable: %x\n",
373 nand_para.operation_opt & NAND_READ_RETRY_EN ? 1 : 0);
374 rkflash_print_info("randomizer enable: %x\n",
375 nand_para.operation_opt & NAND_RANDOMIZER_EN ? 1 : 0);
376
377 rkflash_print_info("SDR enable: %x\n",
378 nand_para.operation_opt & NAND_SDR_EN ? 1 : 0);
379 rkflash_print_info("ONFI enable: %x\n",
380 nand_para.operation_opt & NAND_ONFI_EN ? 1 : 0);
381 rkflash_print_info("TOGGLE enable: %x\n",
382 nand_para.operation_opt & NAND_TOGGLE_EN ? 1 : 0);
383
384 rkflash_print_info("g_nand_idb_res_blk_num: %x\n", g_nand_idb_res_blk_num);
385 }
386
flash_ftl_ops_init(void)387 static void flash_ftl_ops_init(void)
388 {
389 u8 nandc_ver = nandc_get_version();
390
391 /* para init */
392 g_nand_phy_info.nand_type = nand_para.cell;
393 g_nand_phy_info.die_num = nand_para.die_per_chip;
394 g_nand_phy_info.plane_per_die = nand_para.plane_per_die;
395 g_nand_phy_info.blk_per_plane = nand_para.blk_per_plane;
396 g_nand_phy_info.page_per_blk = nand_para.page_per_blk;
397 g_nand_phy_info.page_per_slc_blk = nand_para.page_per_blk /
398 nand_para.cell;
399 g_nand_phy_info.byte_per_sec = 512;
400 g_nand_phy_info.sec_per_page = nand_para.sec_per_page;
401 g_nand_phy_info.sec_per_blk = nand_para.sec_per_page *
402 nand_para.page_per_blk;
403 g_nand_phy_info.reserved_blk = 8;
404 g_nand_phy_info.blk_per_die = nand_para.plane_per_die *
405 nand_para.blk_per_plane;
406 g_nand_phy_info.ecc_bits = nand_para.ecc_bits;
407
408 /* driver register */
409 g_nand_ops.get_bad_blk_list = flash_get_bad_blk_list;
410 g_nand_ops.erase_blk = flash_erase_block;
411 g_nand_ops.prog_page = flash_prog_page;
412 g_nand_ops.read_page = flash_read_page;
413 if (nandc_ver == 9) {
414 g_nand_ops.bch_sel = flash_bch_sel;
415 g_nand_ops.set_sec_num = flash_set_sector;
416 }
417 }
418
nandc_flash_reset(u8 cs)419 void nandc_flash_reset(u8 cs)
420 {
421 nandc_flash_cs(cs);
422 nandc_writel(RESET_CMD, NANDC_CHIP_CMD(cs));
423 nandc_wait_flash_ready(cs);
424 nandc_flash_de_cs(cs);
425 }
426
nandc_flash_init(void __iomem * nandc_addr)427 u32 nandc_flash_init(void __iomem *nandc_addr)
428 {
429 u32 cs;
430
431 rkflash_print_error("...%s enter...\n", __func__);
432 g_nand_idb_res_blk_num = MAX_IDB_RESERVED_BLOCK;
433 g_nand_ecc_en = 0;
434
435 nandc_init(nandc_addr);
436
437 for (cs = 0; cs < MAX_FLASH_NUM; cs++) {
438 flash_read_id_raw(cs, id_byte[cs]);
439 if (cs == 0) {
440 if (id_byte[0][0] == 0xFF ||
441 id_byte[0][0] == 0 ||
442 id_byte[0][1] == 0xFF)
443 return FTL_NO_FLASH;
444 if (id_byte[0][1] != 0xF1 &&
445 id_byte[0][1] != 0xDA &&
446 id_byte[0][1] != 0xD1 &&
447 id_byte[0][1] != 0x95 &&
448 id_byte[0][1] != 0xDC &&
449 id_byte[0][1] != 0xD3 &&
450 id_byte[0][1] != 0x48 &&
451 id_byte[0][1] != 0xA1 &&
452 id_byte[0][1] != 0xAA &&
453 id_byte[0][1] != 0xAC &&
454 id_byte[0][1] != 0x6A &&
455 id_byte[0][1] != 0xD7) {
456 pr_err("The device not support yet!\n");
457
458 return FTL_UNSUPPORTED_FLASH;
459 }
460
461 if (id_byte[0][1] == 0xD7 && nandc_get_version() != 9) {
462 pr_err("This device is not compatible, Insufficient ECC capability\n");
463
464 return FTL_UNSUPPORTED_FLASH;
465 }
466 }
467 }
468 if (id_byte[0][0] == 0x98 && (id_byte[0][4] & 0x80))
469 g_nand_ecc_en = 1;
470 nand_para.nand_id[1] = id_byte[0][1];
471 if (id_byte[0][1] == 0xDA || id_byte[0][1] == 0xAA || id_byte[0][1] == 0x6A) {
472 nand_para.plane_per_die = 2;
473 nand_para.nand_id[1] = id_byte[0][1];
474 } else if (id_byte[0][1] == 0xDC || id_byte[0][1] == 0xAC) {
475 nand_para.nand_id[1] = id_byte[0][1];
476 if ((id_byte[0][0] == 0x2C && id_byte[0][3] == 0xA6) ||
477 (id_byte[0][0] == 0xC2 && id_byte[0][3] == 0xA2)) {
478 nand_para.plane_per_die = 2;
479 nand_para.sec_per_page = 8;
480 } else if ((id_byte[0][0] == 0x98 && id_byte[0][3] == 0x26) ||
481 (id_byte[0][0] == 0xC8 && id_byte[0][2] == 0x80 && ((id_byte[0][3] & 0x3) == 1)) || /* F59L4G81KA (2R) */
482 (id_byte[0][0] == 0xC8 && id_byte[0][2] == 0x90 && ((id_byte[0][3] & 0x3) == 2))) { /* GD9F4GxF2A */
483 nand_para.blk_per_plane = 1024;
484 nand_para.sec_per_page = 8;
485 nand_para.plane_per_die = 2;
486 } else {
487 nand_para.plane_per_die = 2;
488 nand_para.blk_per_plane = 2048;
489 }
490 } else if (id_byte[0][1] == 0x48) {
491 nand_para.sec_per_page = 8;
492 nand_para.page_per_blk = 128;
493 nand_para.plane_per_die = 2;
494 nand_para.blk_per_plane = 2048;
495 } else if (id_byte[0][1] == 0xD3) {
496 if ((id_byte[0][2] == 0xD1 && id_byte[0][4] == 0x5a) || /* S34ML08G2 */
497 (id_byte[0][3] == 0x05 && id_byte[0][4] == 0x04)) { /* S34ML08G3 */
498 nand_para.sec_per_page = 4;
499 nand_para.page_per_blk = 64;
500 nand_para.plane_per_die = 2;
501 nand_para.blk_per_plane = 4096;
502 } else {
503 nand_para.sec_per_page = 8;
504 nand_para.page_per_blk = 64;
505 nand_para.plane_per_die = 2;
506 nand_para.blk_per_plane = 2048;
507 }
508 } else if (id_byte[0][1] == 0xD7 && id_byte[0][3] == 0x32) { /* TC58NVG5H2HTAI0 */
509 nand_para.ecc_bits = 70;
510 nand_para.blk_per_plane = 2048;
511 nand_para.sec_per_page = 16;
512 nand_para.page_per_blk = 128;
513 nand_para.plane_per_die = 2;
514 }
515 flash_die_info_init();
516 flash_bch_sel(nand_para.ecc_bits);
517 flash_show_info();
518 flash_ftl_ops_init();
519
520 return 0;
521 }
522
nandc_flash_get_id(u8 cs,void * buf)523 void nandc_flash_get_id(u8 cs, void *buf)
524 {
525 memcpy(buf, id_byte[cs], 5);
526 }
527
nandc_flash_deinit(void)528 u32 nandc_flash_deinit(void)
529 {
530 return 0;
531 }
532