5  * SPDX-License-Identifier:	GPL-2.0+
45 static long int get_ddr_bank_size(short cs, long *base);
46 static void set_cs_bounds(short cs, ulong base, ulong size);
47 static void set_cs_config(short cs, long config);
59 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)  in board_early_init_r()
73 	int cs;  in dram_init()  local
76 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE;  in dram_init()
77 	im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);  in dram_init()
79 	/* set CS bounds to maximum size */  in dram_init()
80 	for(cs = 0; cs < 4; ++cs) {  in dram_init()
81 		set_cs_bounds(cs,  in dram_init()
82 			CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),  in dram_init()
85 		set_cs_config(cs, INITIAL_CS_CONFIG);  in dram_init()
94 	im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |  in dram_init()
102 	for(cs = 0; cs < 4; ++cs) {  in dram_init()
103 		debug("\nDetecting Bank%d\n", cs);  in dram_init()
105 		bank_size = get_ddr_bank_size(cs,  in dram_init()
109 		debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20);  in dram_init()
115 	gd->ram_size = size;  in dram_init()
132 	if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) {  in checkboard()
139 	if (immr->reset.rcwh & HRCWH_64_BIT_PCI)  in checkboard()
143 	f = gd->pci_clk;  in checkboard()
160  * Detect the number of flash banks (1 or 2). Store it in
176 	cfi_flash_num_flash_banks = 2;	/* assume two banks */  in detect_num_flash_banks()
178 	/* Get bank 1 and 2 information */  in detect_num_flash_banks()
186 		/* Seems like we've got bank 2, but maybe it's mirrored 1 */  in detect_num_flash_banks()
192 		/* Put bank 2 into CFI command mode and read */  in detect_num_flash_banks()
208 			 * read from bank 2 in autosoelect mode.  in detect_num_flash_banks()
240 		   (-(total_size) & OR_GPCM_AM));  in detect_num_flash_banks()
248  * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
250 static long int get_ddr_bank_size(short cs, long *base)  in get_ddr_bank_size()  argument
253 	 * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).  in get_ddr_bank_size()
277 	detected = -1;  in get_ddr_bank_size()
281 		set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);  in get_ddr_bank_size()
297 	if(detected == -1){  in get_ddr_bank_size()
298 		/* disable empty cs */  in get_ddr_bank_size()
299 		debug("\nNo valid configurations for CS%d, disabling...\n", cs);  in get_ddr_bank_size()
300 		set_cs_config(cs, 0);  in get_ddr_bank_size()
307 	/* configure cs ro detected params */  in get_ddr_bank_size()
308 	set_cs_config(cs, CSCONFIG_EN | conf[detected].row |  in get_ddr_bank_size()
311 	set_cs_bounds(cs, (long)base, conf[detected].size);  in get_ddr_bank_size()
317  * Sets DDR bank CS bounds.
319 static void set_cs_bounds(short cs, ulong base, ulong size)  in set_cs_bounds()  argument
321 	debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs);  in set_cs_bounds()
323 		im->ddr.csbnds[cs].csbnds = 0x00000000;  in set_cs_bounds()
325 		im->ddr.csbnds[cs].csbnds =  in set_cs_bounds()
327 			(((base + size - 1) >> CSBNDS_EA_SHIFT) &  in set_cs_bounds()
334  * Sets DDR banks CS configuration.
335  * config == 0x00000000 disables the CS.
337 static void set_cs_config(short cs, long config)  in set_cs_config()  argument
339 	debug("Setting config %08lx for cs %d\n", config, cs);  in set_cs_config()
340 	im->ddr.cs_config[cs] = config;  in set_cs_config()
349 	im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |  in set_ddr_config()
354 	im->ddr.timing_cfg_1 =  in set_ddr_config()
364 	im->ddr.timing_cfg_2 =  in set_ddr_config()
366 		(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);  in set_ddr_config()
370 	im->ddr.sdram_cfg =  in set_ddr_config()
376 	im->ddr.sdram_mode =  in set_ddr_config()
386 	im->ddr.sdram_interval =  in set_ddr_config()
392 	 * see MPC8349E Device Errata Rev.8, 2/2006  in set_ddr_config()
402 	if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {  in set_ddr_config()