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/OK3568_Linux_fs/kernel/include/linux/mfd/da9062/
H A Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2015-2017 Dialog Semiconductor
151 * Bit fields
158 #define DA9062AA_WRITE_MODE_MASK BIT(6)
160 #define DA9062AA_REVERT_MASK BIT(7)
166 #define DA9062AA_DVC_BUSY_MASK BIT(2)
172 #define DA9062AA_GPI1_MASK BIT(1)
174 #define DA9062AA_GPI2_MASK BIT(2)
176 #define DA9062AA_GPI3_MASK BIT(3)
177 #define DA9062AA_GPI4_SHIFT 4
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/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Drk_codec_digital.h1 /* SPDX-License-Identifier: GPL-2.0 */
75 #define ACDCDIG_SYSCTRL0_SYNC_SEL_MASK BIT(1)
76 #define ACDCDIG_SYSCTRL0_SYNC_SEL_DAC BIT(1)
78 #define ACDCDIG_SYSCTRL0_GLB_CKE_MASK BIT(3)
79 #define ACDCDIG_SYSCTRL0_GLB_CKE_EN BIT(3)
81 #define ACDCDIG_SYSCTRL0_CLK_COM_SEL_MASK BIT(4)
82 #define ACDCDIG_SYSCTRL0_CLK_COM_SEL_DAC BIT(4)
84 #define ACDCDIG_SYSCTRL0_SYNC_MODE_MASK BIT(5)
85 #define ACDCDIG_SYSCTRL0_SYNC_MODE_SYNC BIT(5)
88 #define ACDCDIG_ADCVUCTL_ADC_BYPS_MASK BIT(2)
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H A Drk_dsm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Rockchip Audio Delta-sigma Digital Converter driver
55 #define DSM_DACDIGEN_DACEN_L0R1_MASK BIT(0)
56 #define DSM_DACDIGEN_DACEN_L0R1_EN BIT(0)
58 #define DSM_DACDIGEN_DAC_GLBEN_MASK BIT(4)
59 #define DSM_DACDIGEN_DAC_GLBEN_EN BIT(4)
62 #define DSM_DACCLKCTRL_DAC_MODE_ATTENU_MASK BIT(0)
63 #define DSM_DACCLKCTRL_DAC_MODE_ATTENU_EN BIT(0)
65 #define DSM_DACCLKCTRL_DAC_SYNC_STATUS_MASK BIT(1)
67 #define DSM_DACCLKCTRL_DAC_SYNC_ENA_MASK BIT(2)
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H A Drk3228_codec.h2 * rk3228_codec.h -- rk3228 ALSA Soc Audio driver
39 #define PWR_RST_BYPASS_DIS BIT(6)
40 #define PWR_RST_BYPASS_EN BIT(6)
42 #define DIG_CORE_WORK BIT(1)
44 #define SYS_WORK BIT(0)
47 #define PIN_DIRECTION_MASK BIT(5)
49 #define PIN_DIRECTION_OUT BIT(5)
50 #define DAC_I2S_MODE_MASK BIT(4)
51 #define DAC_I2S_MODE_SLAVE (0 << 4)
52 #define DAC_I2S_MODE_MASTER BIT(4)
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/OK3568_Linux_fs/kernel/include/soc/mscc/
H A Docelot_dev.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
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/OK3568_Linux_fs/u-boot/board/keymile/km_arm/
H A Dkwbimage_128M16_1.cfg10 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
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H A Dkwbimage_256M8_1.cfg7 # SPDX-License-Identifier: GPL-2.0+
9 # Refer doc/README.kwbimage for more details about how-to configure
12 # This configuration applies to COGE5 design (ARM-part)
13 # Two 8-Bit devices are connected on the 16-Bit bus on the same
14 # chip-select. The supported devices are
15 # MT47H256M8EB-3IT:C
16 # MT47H256M8EB-25EIT:C
22 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
23 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
24 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
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/OK3568_Linux_fs/kernel/include/linux/mfd/abx500/
H A Dab8500-sysctrl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) ST-Ericsson SA 2010
83 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
84 #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
85 #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
86 #define AB8500_TURNONSTATUS_RTCALARM BIT(3)
87 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
88 #define AB8500_TURNONSTATUS_VBUSDET BIT(5)
89 #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
91 #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/freescale/dpaa2/
H A Ddpkg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2015 Freescale Semiconductor Inc.
18 #define DPKG_NUM_OF_MASKS 4
25 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
37 * enum dpkg_extract_type - Enumeration for selecting extraction type
40 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
51 * struct dpkg_mask - A structure for defining a single extraction mask
63 #define NH_FLD_ETH_DA BIT(0)
64 #define NH_FLD_ETH_SA BIT(1)
65 #define NH_FLD_ETH_LENGTH BIT(2)
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/mac_ax/mac_8852b/
H A Dgpio_8852b.c23 0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)}
26 0x4F, BIT(5), BIT(5)}
29 0x66, BIT(6), BIT(6)}
32 0x4F, BIT(6), BIT(6)}
35 0x41, BIT(1), BIT(1)}
38 0x41, BIT(2), BIT(2)}
41 0x40, BIT(1) | BIT(0), BIT(0)}
44 0x40, BIT(1) | BIT(0), BIT(1)}
47 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
50 0x142, BIT(0), BIT(0)}
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/mac_ax/mac_8852b/
H A Dgpio_8852b.c23 0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)}
26 0x4F, BIT(5), BIT(5)}
29 0x66, BIT(6), BIT(6)}
32 0x4F, BIT(6), BIT(6)}
35 0x41, BIT(1), BIT(1)}
38 0x41, BIT(2), BIT(2)}
41 0x40, BIT(1) | BIT(0), BIT(0)}
44 0x40, BIT(1) | BIT(0), BIT(1)}
47 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
50 0x142, BIT(0), BIT(0)}
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/OK3568_Linux_fs/kernel/drivers/crypto/rockchip/
H A Drk_crypto_v2_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define CRYPTO_AUTO_CLKGATE_EN BIT(0)
20 #define CRYPTO_SW_PKA_RESET BIT(2)
21 #define CRYPTO_SW_RNG_RESET BIT(1)
22 #define CRYPTO_SW_CC_RESET BIT(0)
26 #define CRYPTO_ZERO_ERR_INT_EN BIT(6)
27 #define CRYPTO_LIST_ERR_INT_EN BIT(5)
28 #define CRYPTO_SRC_ERR_INT_EN BIT(4)
29 #define CRYPTO_DST_ERR_INT_EN BIT(3)
30 #define CRYPTO_SRC_ITEM_INT_EN BIT(2)
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/OK3568_Linux_fs/kernel/drivers/net/dsa/microchip/
H A Dksz8795_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
24 #define SW_CHIP_ID_S 4
34 #define SW_NEW_BACKOFF BIT(7)
35 #define SW_GLOBAL_RESET BIT(6)
36 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
37 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
38 #define SW_LINK_AUTO_AGING BIT(0)
42 #define SW_HUGE_PACKET BIT(6)
43 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
44 #define SW_RX_FLOW_CTRL_DISABLE BIT(4)
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H A Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 Microchip Technology Inc.
12 #define KS_PRIO_S 4
14 /* 0 - Operation */
39 #define SWITCH_REVISION_S 4
44 #define PME_ENABLE BIT(1)
45 #define PME_POLARITY BIT(0)
49 #define SW_GIGABIT_ABLE BIT(6)
50 #define SW_REDUNDANCY_ABLE BIT(5)
51 #define SW_AVB_ABLE BIT(4)
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/OK3568_Linux_fs/kernel/include/linux/mfd/
H A Dmax96755f.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Defining registers address and its bit definitions of MAX96752F
32 #define CFG_BLOCK BIT(0)
35 #define IIC_2_EN BIT(7)
36 #define IIC_1_EN BIT(6)
37 #define DIS_REM_CC BIT(4)
41 #define VID_TX_EN_U BIT(7)
42 #define VID_TX_EN_Z BIT(6)
43 #define VID_TX_EN_Y BIT(5)
44 #define VID_TX_EN_X BIT(4)
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H A Dlp87565.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
97 #define LP87565_BUCK_CTRL_1_EN BIT(7)
98 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6)
101 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3)
102 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2)
103 #define LP87565_BUCK_CTRL_1_FPWM BIT(1)
105 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0)
119 #define LP87565_RESET_SW_RESET BIT(0)
121 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7)
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/OK3568_Linux_fs/kernel/Documentation/input/devices/
H A Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
18 4. Hardware version 1
20 4.2 Native relative mode 4 byte packet format
21 4.3 Native absolute mode 4 byte packet format
25 5.2.1 Parity checking and packet re-synchronization
33 7. Hardware version 4
39 8. Trackpoint (for Hardware version 3 and 4)
51 and version 4. Version 1 is found in "older" laptops and uses 4 bytes per
56 of up to 3 fingers. Hardware version 4 uses 6 bytes per packet, and can
58 4 allows tracking up to 5 fingers.
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/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu-sun9i-a80.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
26 * The CPU PLLs are actually NP clocks, with P being /1 or /4. However
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
36 .enable = BIT(31),
37 .lock = BIT(0),
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
50 .enable = BIT(31),
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H A Dccu-sun6i-a31.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
29 #include "ccu-sun6i-a31.h"
31 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
34 4, 2, /* K */
36 BIT(31), /* gate */
37 BIT(28), /* lock */
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/OK3568_Linux_fs/kernel/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
18 #define TW5864_EMU_EN_DDR BIT(0)
19 /* Enable bit for Inter module */
20 #define TW5864_EMU_EN_ME BIT(1)
21 /* Enable bit for Sensor Interface module */
22 #define TW5864_EMU_EN_SEN BIT(2)
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/OK3568_Linux_fs/u-boot/include/
H A Dmax96755f.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <asm-generic/gpio.h>
19 #define CFG_BLOCK BIT(0)
22 #define IIC_2_EN BIT(7)
23 #define IIC_1_EN BIT(6)
24 #define DIS_REM_CC BIT(4)
28 #define VID_TX_EN_U BIT(7)
29 #define VID_TX_EN_Z BIT(6)
30 #define VID_TX_EN_Y BIT(5)
31 #define VID_TX_EN_X BIT(4)
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/OK3568_Linux_fs/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3308.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include "pinctrl-rockchip.h"
22 .route_val = BIT(16 + 0) | BIT(0),
29 .route_val = BIT(16 + 2) | BIT(16 + 3),
32 .bank_num = 4,
36 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
43 .route_val = BIT(16 + 4),
50 .route_val = BIT(16 + 4) | BIT(4),
52 /* i2s-8ch-1-sclktxm0 */
57 .route_val = BIT(16 + 3),
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/mediatek/
H A Dmtk_mt8173_mipi_tx.c1 // SPDX-License-Identifier: GPL-2.0
10 #define RG_DSI_LDOCORE_EN BIT(0)
11 #define RG_DSI_CKG_LDOOUT_EN BIT(1)
13 #define RG_DSI_LD_IDX_SEL (7 << 4)
15 #define RG_DSI_DSICLK_FREQ_SEL BIT(10)
16 #define RG_DSI_LPTX_CLMP_EN BIT(11)
23 #define RG_DSI_LNTx_LDOOUT_EN BIT(0)
24 #define RG_DSI_LNTx_CKLANE_EN BIT(1)
25 #define RG_DSI_LNTx_LPTX_IPLUS1 BIT(2)
26 #define RG_DSI_LNTx_LPTX_IPLUS2 BIT(3)
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/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dpwrseq.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2013 Realtek Corporation.*/
8 /* Check document WM-20110607-Paul-RTL8188EE_Power_Architecture-R02.vsd
10 * 0: POFF--Power Off
11 * 1: PDN--Power Down
12 * 2: CARDEMU--Card Emulation
13 * 3: ACT--Active Mode
14 * 4: LPS--Low Power State
15 * 5: SUS--Suspend
46 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1) \
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/OK3568_Linux_fs/kernel/sound/soc/fsl/
H A Dfsl_easrc.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/platform_data/dma-imx.h>
17 #define REG_EASRC_WRFIFO(ctx) (0x000 + 4 * (ctx))
19 #define REG_EASRC_RDFIFO(ctx) (0x010 + 4 * (ctx))
21 #define REG_EASRC_CC(ctx) (0x020 + 4 * (ctx))
23 #define REG_EASRC_CCE1(ctx) (0x030 + 4 * (ctx))
25 #define REG_EASRC_CCE2(ctx) (0x040 + 4 * (ctx))
27 #define REG_EASRC_CIA(ctx) (0x050 + 4 * (ctx))
29 #define REG_EASRC_DPCS0R0(ctx) (0x060 + 4 * (ctx))
30 #define REG_EASRC_DPCS0R1(ctx) (0x070 + 4 * (ctx))
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