1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Rockchip Audio Delta-sigma Digital Converter driver 4 * 5 * Copyright (C) 2023 Rockchip Electronics Co., Ltd 6 * 7 */ 8 9 #ifndef _RK_DSM_H 10 #define _RK_DSM_H 11 12 #define DACVUCTL 0x0000 13 #define DACVUCTIME 0x0004 14 #define DACDIGEN 0x0008 15 #define DACCLKCTRL 0x000c 16 #define DACINT_DIV 0x0014 17 #define DACSCLKRXINT_DIV 0x0020 18 #define DACPWM_DIV 0x0024 19 #define DACPWM_CTRL 0x0028 20 #define DACCFG1 0x0044 21 #define DACMUTE 0x0048 22 #define DACMUTEST 0x004c 23 #define DACVOLL0 0x0050 24 #define DACVOLL1 0x0054 25 #define DACVOLL2 0x0058 26 #define DACVOLL3 0x005c 27 #define DACVOLR0 0x0060 28 #define DACVOLR1 0x0064 29 #define DACVOLR2 0x0068 30 #define DACVOLR3 0x006c 31 #define DACVOGP 0x0070 32 #define DACRVOLL0 0x0074 33 #define DACRVOLL1 0x0078 34 #define DACRVOLL2 0x007c 35 #define DACRVOLL3 0x0080 36 #define DACRVOLR0 0x0084 37 #define DACRVOLR1 0x0088 38 #define DACRVOLR2 0x008c 39 #define DACRVOLR3 0x0090 40 #define DACLMT0 0x0094 41 #define DACLMT1 0x0098 42 #define DACLMT2 0x009c 43 #define DACMIXCTRLL 0x00a0 44 #define DACMIXCTRLR 0x00a4 45 #define DACHPF 0x00a8 46 #define I2S_RXCR0 0x010c 47 #define I2S_RXCR1 0x0110 48 #define I2S_CKR0 0x0114 49 #define I2S_CKR1 0x0118 50 #define I2S_XFER 0x011c 51 #define I2S_CLR 0x0120 52 #define VERSION 0x0140 53 54 /* DACDIGEN */ 55 #define DSM_DACDIGEN_DACEN_L0R1_MASK BIT(0) 56 #define DSM_DACDIGEN_DACEN_L0R1_EN BIT(0) 57 #define DSM_DACDIGEN_DACEN_L0R1_DIS 0 58 #define DSM_DACDIGEN_DAC_GLBEN_MASK BIT(4) 59 #define DSM_DACDIGEN_DAC_GLBEN_EN BIT(4) 60 #define DSM_DACDIGEN_DAC_GLBEN_DIS 0 61 /* DACCLKCTRL */ 62 #define DSM_DACCLKCTRL_DAC_MODE_ATTENU_MASK BIT(0) 63 #define DSM_DACCLKCTRL_DAC_MODE_ATTENU_EN BIT(0) 64 #define DSM_DACCLKCTRL_DAC_MODE_ATTENU_DIS 0 65 #define DSM_DACCLKCTRL_DAC_SYNC_STATUS_MASK BIT(1) 66 #define DSM_DACCLKCTRL_DAC_SYNC_STATUS_DONE 0 67 #define DSM_DACCLKCTRL_DAC_SYNC_ENA_MASK BIT(2) 68 #define DSM_DACCLKCTRL_DAC_SYNC_ENA_EN BIT(2) 69 #define DSM_DACCLKCTRL_DAC_SYNC_ENA_DIS 0 70 #define DSM_DACCLKCTRL_CKE_BCLKRX_MASK BIT(3) 71 #define DSM_DACCLKCTRL_CKE_BCLKRX_EN BIT(3) 72 #define DSM_DACCLKCTRL_CKE_BCLKRX_DIS 0 73 #define DSM_DACCLKCTRL_I2SRX_CKE_MASK BIT(4) 74 #define DSM_DACCLKCTRL_I2SRX_CKE_EN BIT(4) 75 #define DSM_DACCLKCTRL_I2SRX_CKE_DIS 0 76 #define DSM_DACCLKCTRL_DAC_CKE_MASK BIT(5) 77 #define DSM_DACCLKCTRL_DAC_CKE_EN BIT(5) 78 #define DSM_DACCLKCTRL_DAC_CKE_DIS 0 79 /* DACINT_DIV */ 80 #define DSM_DACINT_DIV_INT_DIV_CON_MASK GENMASK(7, 0) 81 #define DSM_DACINT_DIV_INT_DIV_CON(x) ((x) - 1) 82 /* DACSCLKRXINT_DIV */ 83 #define DSM_DACSCLKRXINT_DIV_SCKRXDIV_MASK GENMASK(7, 0) 84 #define DSM_DACSCLKRXINT_DIV_SCKRXDIV(x) ((x) - 1) 85 /* DACPWM_DIV */ 86 #define DSM_DACPWM_DIV_AUDIO_PWM_DIV_MASK GENMASK(7, 0) 87 #define DSM_DACPWM_DIV_AUDIO_PWM_DIV(x) ((x) - 1) 88 /* DACPWM_CTRL */ 89 #define DSM_DACPWM_CTRL_DITH_SEL_MASK GENMASK(2, 0) 90 #define DSM_DACPWM_CTRL_DITH_SEL(x) (x) 91 #define DSM_DACPWM_CTRL_PWM_EN_MASK BIT(3) 92 #define DSM_DACPWM_CTRL_PWM_EN BIT(3) 93 #define DSM_DACPWM_CTRL_PWM_DIS 0 94 #define DSM_DACPWM_CTRL_PWM_MODE_MASK GENMASK(5, 4) 95 #define DSM_DACPWM_CTRL_PWM_MODE_1 (0x2 << 4) 96 #define DSM_DACPWM_CTRL_PWM_MODE_0 (0x1 << 4) 97 #define DSM_DACPWM_CTRL_PWM_MODE_DAC (0x0 << 4) 98 #define DSM_DACPWM_CTRL_PWM_MODE_CKE_MASK BIT(6) 99 #define DSM_DACPWM_CTRL_PWM_MODE_CKE_EN BIT(6) 100 #define DSM_DACPWM_CTRL_PWM_MODE_CKE_DIS 0 101 /* DACCFG1 */ 102 #define DSM_DACCFG1_DACSRT_MASK GENMASK(4, 2) 103 #define DSM_DACCFG1_DACSRT(x) ((x) << 2) 104 /* DACMUTE */ 105 #define DSM_DACMUTE_DACMT_MASK BIT(0) 106 #define DSM_DACMUTE_DACUNMT_MASK BIT(1) 107 /* DACVOLL0 */ 108 #define DSM_DACVOLL0_DACLV0_MASK GENMASK(7, 0) 109 #define DSM_DACVOLL0_DACLV0(x) (x) 110 /* DACVOLR0 */ 111 #define DSM_DACVOLR0_DACRV0_MASK GENMASK(7, 0) 112 #define DSM_DACVOLR0_DACRV0(x) (x) 113 /* DACVOGP */ 114 #define DSM_DACVOGP_VOLGPL0_MASK BIT(0) 115 #define DSM_DACVOGP_VOLGPL0_POS BIT(0) 116 #define DSM_DACVOGP_VOLGPL0_NEG 0 117 #define DSM_DACVOGP_VOLGPR0_MASK BIT(1) 118 #define DSM_DACVOGP_VOLGPR0_POS BIT(1) 119 #define DSM_DACVOGP_VOLGPR0_NEG 0 120 /* DACMIXCTRLL */ 121 #define DSM_DACMIXCTRLL_MIXMODE_L0_MASK GENMASK(1, 0) 122 #define DSM_DACMIXCTRLL_MIXMODE_L0_LR 2 123 #define DSM_DACMIXCTRLL_MIXMODE_L0_R 1 124 #define DSM_DACMIXCTRLL_MIXMODE_L0_L 0 125 /* DACMIXCTRLR */ 126 #define DSM_DACMIXCTRLR_MIXMODE_R0_MASK GENMASK(1, 0) 127 #define DSM_DACMIXCTRLR_MIXMODE_R0_LR 2 128 #define DSM_DACMIXCTRLR_MIXMODE_R0_L 1 129 #define DSM_DACMIXCTRLR_MIXMODE_R0_R 0 130 /* DACHPF */ 131 #define DSM_DACHPF_HPFEN_L0R0_MASK BIT(0) 132 #define DSM_DACHPF_HPFEN_L0R0_EN BIT(0) 133 #define DSM_DACHPF_HPFCF_MASK GENMASK(5, 4) 134 #define DSM_DACHPF_HPFCF_140HZ (0x3 << 4) 135 #define DSM_DACHPF_HPFCF_120HZ (0x2 << 4) 136 #define DSM_DACHPF_HPFCF_100HZ (0x1 << 4) 137 #define DSM_DACHPF_HPFCF_80HZ (0x0 << 4) 138 /* I2S_RXCR0 */ 139 #define DSM_I2S_RXCR0_VDW_MASK GENMASK(4, 0) 140 #define DSM_I2S_RXCR0_VDW(x) ((x) - 1) 141 /* I2S_RXCR1 */ 142 #define DSM_I2S_RXCR1_CEX_MASK BIT(4) 143 #define DSM_I2S_RXCR1_CEX_EXCHANGE BIT(4) 144 #define DSM_I2S_RXCR1_RCSR_MASK GENMASK(7, 6) 145 #define DSM_I2S_RXCR1_RCSR_2CH (0x0 << 6) 146 /* I2S_CKR0 */ 147 #define DSM_I2S_CKR0_RSD_MASK GENMASK(3, 2) 148 #define DSM_I2S_CKR0_RSD_64 (0 << 2) 149 #define DSM_I2S_CKR0_RSD_128 (1 << 2) 150 #define DSM_I2S_CKR0_RSD_256 (2 << 2) 151 /* I2S_CKR1 */ 152 #define DSM_I2S_CKR1_RLP_MASK BIT(1) 153 #define DSM_I2S_CKR1_RLP_INVERTED BIT(1) 154 #define DSM_I2S_CKR1_RLP_NORMAL 0 155 #define DSM_I2S_CKR1_CKP_MASK BIT(2) 156 #define DSM_I2S_CKR1_CKP_INVERTED BIT(2) 157 #define DSM_I2S_CKR1_CKP_NORMAL 0 158 #define DSM_I2S_CKR1_MSS_MASK BIT(3) 159 #define DSM_I2S_CKR1_MSS_MASTER 0 160 /* I2S_XFER */ 161 #define DSM_I2S_XFER_RXS_MASK BIT(1) 162 #define DSM_I2S_XFER_RXS_START BIT(1) 163 #define DSM_I2S_XFER_RXS_STOP 0 164 /* I2S_CLR */ 165 #define DSM_I2S_CLR_RXC_MASK BIT(1) 166 #define DSM_I2S_CLR_RXC_CLR BIT(1) 167 168 #endif 169