1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2015-2017 Dialog Semiconductor 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DA9062_H__ 7*4882a593Smuzhiyun #define __DA9062_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define DA9062_PMIC_DEVICE_ID 0x62 10*4882a593Smuzhiyun #define DA9062_PMIC_VARIANT_MRC_AA 0x01 11*4882a593Smuzhiyun #define DA9062_PMIC_VARIANT_VRC_DA9061 0x01 12*4882a593Smuzhiyun #define DA9062_PMIC_VARIANT_VRC_DA9062 0x02 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define DA9062_I2C_PAGE_SEL_SHIFT 1 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * Registers 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define DA9062AA_PAGE_CON 0x000 21*4882a593Smuzhiyun #define DA9062AA_STATUS_A 0x001 22*4882a593Smuzhiyun #define DA9062AA_STATUS_B 0x002 23*4882a593Smuzhiyun #define DA9062AA_STATUS_D 0x004 24*4882a593Smuzhiyun #define DA9062AA_FAULT_LOG 0x005 25*4882a593Smuzhiyun #define DA9062AA_EVENT_A 0x006 26*4882a593Smuzhiyun #define DA9062AA_EVENT_B 0x007 27*4882a593Smuzhiyun #define DA9062AA_EVENT_C 0x008 28*4882a593Smuzhiyun #define DA9062AA_IRQ_MASK_A 0x00A 29*4882a593Smuzhiyun #define DA9062AA_IRQ_MASK_B 0x00B 30*4882a593Smuzhiyun #define DA9062AA_IRQ_MASK_C 0x00C 31*4882a593Smuzhiyun #define DA9062AA_CONTROL_A 0x00E 32*4882a593Smuzhiyun #define DA9062AA_CONTROL_B 0x00F 33*4882a593Smuzhiyun #define DA9062AA_CONTROL_C 0x010 34*4882a593Smuzhiyun #define DA9062AA_CONTROL_D 0x011 35*4882a593Smuzhiyun #define DA9062AA_CONTROL_E 0x012 36*4882a593Smuzhiyun #define DA9062AA_CONTROL_F 0x013 37*4882a593Smuzhiyun #define DA9062AA_PD_DIS 0x014 38*4882a593Smuzhiyun #define DA9062AA_GPIO_0_1 0x015 39*4882a593Smuzhiyun #define DA9062AA_GPIO_2_3 0x016 40*4882a593Smuzhiyun #define DA9062AA_GPIO_4 0x017 41*4882a593Smuzhiyun #define DA9062AA_GPIO_WKUP_MODE 0x01C 42*4882a593Smuzhiyun #define DA9062AA_GPIO_MODE0_4 0x01D 43*4882a593Smuzhiyun #define DA9062AA_GPIO_OUT0_2 0x01E 44*4882a593Smuzhiyun #define DA9062AA_GPIO_OUT3_4 0x01F 45*4882a593Smuzhiyun #define DA9062AA_BUCK2_CONT 0x020 46*4882a593Smuzhiyun #define DA9062AA_BUCK1_CONT 0x021 47*4882a593Smuzhiyun #define DA9062AA_BUCK4_CONT 0x022 48*4882a593Smuzhiyun #define DA9062AA_BUCK3_CONT 0x024 49*4882a593Smuzhiyun #define DA9062AA_LDO1_CONT 0x026 50*4882a593Smuzhiyun #define DA9062AA_LDO2_CONT 0x027 51*4882a593Smuzhiyun #define DA9062AA_LDO3_CONT 0x028 52*4882a593Smuzhiyun #define DA9062AA_LDO4_CONT 0x029 53*4882a593Smuzhiyun #define DA9062AA_DVC_1 0x032 54*4882a593Smuzhiyun #define DA9062AA_COUNT_S 0x040 55*4882a593Smuzhiyun #define DA9062AA_COUNT_MI 0x041 56*4882a593Smuzhiyun #define DA9062AA_COUNT_H 0x042 57*4882a593Smuzhiyun #define DA9062AA_COUNT_D 0x043 58*4882a593Smuzhiyun #define DA9062AA_COUNT_MO 0x044 59*4882a593Smuzhiyun #define DA9062AA_COUNT_Y 0x045 60*4882a593Smuzhiyun #define DA9062AA_ALARM_S 0x046 61*4882a593Smuzhiyun #define DA9062AA_ALARM_MI 0x047 62*4882a593Smuzhiyun #define DA9062AA_ALARM_H 0x048 63*4882a593Smuzhiyun #define DA9062AA_ALARM_D 0x049 64*4882a593Smuzhiyun #define DA9062AA_ALARM_MO 0x04A 65*4882a593Smuzhiyun #define DA9062AA_ALARM_Y 0x04B 66*4882a593Smuzhiyun #define DA9062AA_SECOND_A 0x04C 67*4882a593Smuzhiyun #define DA9062AA_SECOND_B 0x04D 68*4882a593Smuzhiyun #define DA9062AA_SECOND_C 0x04E 69*4882a593Smuzhiyun #define DA9062AA_SECOND_D 0x04F 70*4882a593Smuzhiyun #define DA9062AA_SEQ 0x081 71*4882a593Smuzhiyun #define DA9062AA_SEQ_TIMER 0x082 72*4882a593Smuzhiyun #define DA9062AA_ID_2_1 0x083 73*4882a593Smuzhiyun #define DA9062AA_ID_4_3 0x084 74*4882a593Smuzhiyun #define DA9062AA_ID_12_11 0x088 75*4882a593Smuzhiyun #define DA9062AA_ID_14_13 0x089 76*4882a593Smuzhiyun #define DA9062AA_ID_16_15 0x08A 77*4882a593Smuzhiyun #define DA9062AA_ID_22_21 0x08D 78*4882a593Smuzhiyun #define DA9062AA_ID_24_23 0x08E 79*4882a593Smuzhiyun #define DA9062AA_ID_26_25 0x08F 80*4882a593Smuzhiyun #define DA9062AA_ID_28_27 0x090 81*4882a593Smuzhiyun #define DA9062AA_ID_30_29 0x091 82*4882a593Smuzhiyun #define DA9062AA_ID_32_31 0x092 83*4882a593Smuzhiyun #define DA9062AA_SEQ_A 0x095 84*4882a593Smuzhiyun #define DA9062AA_SEQ_B 0x096 85*4882a593Smuzhiyun #define DA9062AA_WAIT 0x097 86*4882a593Smuzhiyun #define DA9062AA_EN_32K 0x098 87*4882a593Smuzhiyun #define DA9062AA_RESET 0x099 88*4882a593Smuzhiyun #define DA9062AA_BUCK_ILIM_A 0x09A 89*4882a593Smuzhiyun #define DA9062AA_BUCK_ILIM_B 0x09B 90*4882a593Smuzhiyun #define DA9062AA_BUCK_ILIM_C 0x09C 91*4882a593Smuzhiyun #define DA9062AA_BUCK2_CFG 0x09D 92*4882a593Smuzhiyun #define DA9062AA_BUCK1_CFG 0x09E 93*4882a593Smuzhiyun #define DA9062AA_BUCK4_CFG 0x09F 94*4882a593Smuzhiyun #define DA9062AA_BUCK3_CFG 0x0A0 95*4882a593Smuzhiyun #define DA9062AA_VBUCK2_A 0x0A3 96*4882a593Smuzhiyun #define DA9062AA_VBUCK1_A 0x0A4 97*4882a593Smuzhiyun #define DA9062AA_VBUCK4_A 0x0A5 98*4882a593Smuzhiyun #define DA9062AA_VBUCK3_A 0x0A7 99*4882a593Smuzhiyun #define DA9062AA_VLDO1_A 0x0A9 100*4882a593Smuzhiyun #define DA9062AA_VLDO2_A 0x0AA 101*4882a593Smuzhiyun #define DA9062AA_VLDO3_A 0x0AB 102*4882a593Smuzhiyun #define DA9062AA_VLDO4_A 0x0AC 103*4882a593Smuzhiyun #define DA9062AA_VBUCK2_B 0x0B4 104*4882a593Smuzhiyun #define DA9062AA_VBUCK1_B 0x0B5 105*4882a593Smuzhiyun #define DA9062AA_VBUCK4_B 0x0B6 106*4882a593Smuzhiyun #define DA9062AA_VBUCK3_B 0x0B8 107*4882a593Smuzhiyun #define DA9062AA_VLDO1_B 0x0BA 108*4882a593Smuzhiyun #define DA9062AA_VLDO2_B 0x0BB 109*4882a593Smuzhiyun #define DA9062AA_VLDO3_B 0x0BC 110*4882a593Smuzhiyun #define DA9062AA_VLDO4_B 0x0BD 111*4882a593Smuzhiyun #define DA9062AA_BBAT_CONT 0x0C5 112*4882a593Smuzhiyun #define DA9062AA_INTERFACE 0x105 113*4882a593Smuzhiyun #define DA9062AA_CONFIG_A 0x106 114*4882a593Smuzhiyun #define DA9062AA_CONFIG_B 0x107 115*4882a593Smuzhiyun #define DA9062AA_CONFIG_C 0x108 116*4882a593Smuzhiyun #define DA9062AA_CONFIG_D 0x109 117*4882a593Smuzhiyun #define DA9062AA_CONFIG_E 0x10A 118*4882a593Smuzhiyun #define DA9062AA_CONFIG_G 0x10C 119*4882a593Smuzhiyun #define DA9062AA_CONFIG_H 0x10D 120*4882a593Smuzhiyun #define DA9062AA_CONFIG_I 0x10E 121*4882a593Smuzhiyun #define DA9062AA_CONFIG_J 0x10F 122*4882a593Smuzhiyun #define DA9062AA_CONFIG_K 0x110 123*4882a593Smuzhiyun #define DA9062AA_CONFIG_M 0x112 124*4882a593Smuzhiyun #define DA9062AA_TRIM_CLDR 0x120 125*4882a593Smuzhiyun #define DA9062AA_GP_ID_0 0x121 126*4882a593Smuzhiyun #define DA9062AA_GP_ID_1 0x122 127*4882a593Smuzhiyun #define DA9062AA_GP_ID_2 0x123 128*4882a593Smuzhiyun #define DA9062AA_GP_ID_3 0x124 129*4882a593Smuzhiyun #define DA9062AA_GP_ID_4 0x125 130*4882a593Smuzhiyun #define DA9062AA_GP_ID_5 0x126 131*4882a593Smuzhiyun #define DA9062AA_GP_ID_6 0x127 132*4882a593Smuzhiyun #define DA9062AA_GP_ID_7 0x128 133*4882a593Smuzhiyun #define DA9062AA_GP_ID_8 0x129 134*4882a593Smuzhiyun #define DA9062AA_GP_ID_9 0x12A 135*4882a593Smuzhiyun #define DA9062AA_GP_ID_10 0x12B 136*4882a593Smuzhiyun #define DA9062AA_GP_ID_11 0x12C 137*4882a593Smuzhiyun #define DA9062AA_GP_ID_12 0x12D 138*4882a593Smuzhiyun #define DA9062AA_GP_ID_13 0x12E 139*4882a593Smuzhiyun #define DA9062AA_GP_ID_14 0x12F 140*4882a593Smuzhiyun #define DA9062AA_GP_ID_15 0x130 141*4882a593Smuzhiyun #define DA9062AA_GP_ID_16 0x131 142*4882a593Smuzhiyun #define DA9062AA_GP_ID_17 0x132 143*4882a593Smuzhiyun #define DA9062AA_GP_ID_18 0x133 144*4882a593Smuzhiyun #define DA9062AA_GP_ID_19 0x134 145*4882a593Smuzhiyun #define DA9062AA_DEVICE_ID 0x181 146*4882a593Smuzhiyun #define DA9062AA_VARIANT_ID 0x182 147*4882a593Smuzhiyun #define DA9062AA_CUSTOMER_ID 0x183 148*4882a593Smuzhiyun #define DA9062AA_CONFIG_ID 0x184 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* 151*4882a593Smuzhiyun * Bit fields 152*4882a593Smuzhiyun */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* DA9062AA_PAGE_CON = 0x000 */ 155*4882a593Smuzhiyun #define DA9062AA_PAGE_SHIFT 0 156*4882a593Smuzhiyun #define DA9062AA_PAGE_MASK 0x3f 157*4882a593Smuzhiyun #define DA9062AA_WRITE_MODE_SHIFT 6 158*4882a593Smuzhiyun #define DA9062AA_WRITE_MODE_MASK BIT(6) 159*4882a593Smuzhiyun #define DA9062AA_REVERT_SHIFT 7 160*4882a593Smuzhiyun #define DA9062AA_REVERT_MASK BIT(7) 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun /* DA9062AA_STATUS_A = 0x001 */ 163*4882a593Smuzhiyun #define DA9062AA_NONKEY_SHIFT 0 164*4882a593Smuzhiyun #define DA9062AA_NONKEY_MASK 0x01 165*4882a593Smuzhiyun #define DA9062AA_DVC_BUSY_SHIFT 2 166*4882a593Smuzhiyun #define DA9062AA_DVC_BUSY_MASK BIT(2) 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* DA9062AA_STATUS_B = 0x002 */ 169*4882a593Smuzhiyun #define DA9062AA_GPI0_SHIFT 0 170*4882a593Smuzhiyun #define DA9062AA_GPI0_MASK 0x01 171*4882a593Smuzhiyun #define DA9062AA_GPI1_SHIFT 1 172*4882a593Smuzhiyun #define DA9062AA_GPI1_MASK BIT(1) 173*4882a593Smuzhiyun #define DA9062AA_GPI2_SHIFT 2 174*4882a593Smuzhiyun #define DA9062AA_GPI2_MASK BIT(2) 175*4882a593Smuzhiyun #define DA9062AA_GPI3_SHIFT 3 176*4882a593Smuzhiyun #define DA9062AA_GPI3_MASK BIT(3) 177*4882a593Smuzhiyun #define DA9062AA_GPI4_SHIFT 4 178*4882a593Smuzhiyun #define DA9062AA_GPI4_MASK BIT(4) 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* DA9062AA_STATUS_D = 0x004 */ 181*4882a593Smuzhiyun #define DA9062AA_LDO1_ILIM_SHIFT 0 182*4882a593Smuzhiyun #define DA9062AA_LDO1_ILIM_MASK 0x01 183*4882a593Smuzhiyun #define DA9062AA_LDO2_ILIM_SHIFT 1 184*4882a593Smuzhiyun #define DA9062AA_LDO2_ILIM_MASK BIT(1) 185*4882a593Smuzhiyun #define DA9062AA_LDO3_ILIM_SHIFT 2 186*4882a593Smuzhiyun #define DA9062AA_LDO3_ILIM_MASK BIT(2) 187*4882a593Smuzhiyun #define DA9062AA_LDO4_ILIM_SHIFT 3 188*4882a593Smuzhiyun #define DA9062AA_LDO4_ILIM_MASK BIT(3) 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun /* DA9062AA_FAULT_LOG = 0x005 */ 191*4882a593Smuzhiyun #define DA9062AA_TWD_ERROR_SHIFT 0 192*4882a593Smuzhiyun #define DA9062AA_TWD_ERROR_MASK 0x01 193*4882a593Smuzhiyun #define DA9062AA_POR_SHIFT 1 194*4882a593Smuzhiyun #define DA9062AA_POR_MASK BIT(1) 195*4882a593Smuzhiyun #define DA9062AA_VDD_FAULT_SHIFT 2 196*4882a593Smuzhiyun #define DA9062AA_VDD_FAULT_MASK BIT(2) 197*4882a593Smuzhiyun #define DA9062AA_VDD_START_SHIFT 3 198*4882a593Smuzhiyun #define DA9062AA_VDD_START_MASK BIT(3) 199*4882a593Smuzhiyun #define DA9062AA_TEMP_CRIT_SHIFT 4 200*4882a593Smuzhiyun #define DA9062AA_TEMP_CRIT_MASK BIT(4) 201*4882a593Smuzhiyun #define DA9062AA_KEY_RESET_SHIFT 5 202*4882a593Smuzhiyun #define DA9062AA_KEY_RESET_MASK BIT(5) 203*4882a593Smuzhiyun #define DA9062AA_NSHUTDOWN_SHIFT 6 204*4882a593Smuzhiyun #define DA9062AA_NSHUTDOWN_MASK BIT(6) 205*4882a593Smuzhiyun #define DA9062AA_WAIT_SHUT_SHIFT 7 206*4882a593Smuzhiyun #define DA9062AA_WAIT_SHUT_MASK BIT(7) 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* DA9062AA_EVENT_A = 0x006 */ 209*4882a593Smuzhiyun #define DA9062AA_E_NONKEY_SHIFT 0 210*4882a593Smuzhiyun #define DA9062AA_E_NONKEY_MASK 0x01 211*4882a593Smuzhiyun #define DA9062AA_E_ALARM_SHIFT 1 212*4882a593Smuzhiyun #define DA9062AA_E_ALARM_MASK BIT(1) 213*4882a593Smuzhiyun #define DA9062AA_E_TICK_SHIFT 2 214*4882a593Smuzhiyun #define DA9062AA_E_TICK_MASK BIT(2) 215*4882a593Smuzhiyun #define DA9062AA_E_WDG_WARN_SHIFT 3 216*4882a593Smuzhiyun #define DA9062AA_E_WDG_WARN_MASK BIT(3) 217*4882a593Smuzhiyun #define DA9062AA_E_SEQ_RDY_SHIFT 4 218*4882a593Smuzhiyun #define DA9062AA_E_SEQ_RDY_MASK BIT(4) 219*4882a593Smuzhiyun #define DA9062AA_EVENTS_B_SHIFT 5 220*4882a593Smuzhiyun #define DA9062AA_EVENTS_B_MASK BIT(5) 221*4882a593Smuzhiyun #define DA9062AA_EVENTS_C_SHIFT 6 222*4882a593Smuzhiyun #define DA9062AA_EVENTS_C_MASK BIT(6) 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun /* DA9062AA_EVENT_B = 0x007 */ 225*4882a593Smuzhiyun #define DA9062AA_E_TEMP_SHIFT 1 226*4882a593Smuzhiyun #define DA9062AA_E_TEMP_MASK BIT(1) 227*4882a593Smuzhiyun #define DA9062AA_E_LDO_LIM_SHIFT 3 228*4882a593Smuzhiyun #define DA9062AA_E_LDO_LIM_MASK BIT(3) 229*4882a593Smuzhiyun #define DA9062AA_E_DVC_RDY_SHIFT 5 230*4882a593Smuzhiyun #define DA9062AA_E_DVC_RDY_MASK BIT(5) 231*4882a593Smuzhiyun #define DA9062AA_E_VDD_WARN_SHIFT 7 232*4882a593Smuzhiyun #define DA9062AA_E_VDD_WARN_MASK BIT(7) 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun /* DA9062AA_EVENT_C = 0x008 */ 235*4882a593Smuzhiyun #define DA9062AA_E_GPI0_SHIFT 0 236*4882a593Smuzhiyun #define DA9062AA_E_GPI0_MASK 0x01 237*4882a593Smuzhiyun #define DA9062AA_E_GPI1_SHIFT 1 238*4882a593Smuzhiyun #define DA9062AA_E_GPI1_MASK BIT(1) 239*4882a593Smuzhiyun #define DA9062AA_E_GPI2_SHIFT 2 240*4882a593Smuzhiyun #define DA9062AA_E_GPI2_MASK BIT(2) 241*4882a593Smuzhiyun #define DA9062AA_E_GPI3_SHIFT 3 242*4882a593Smuzhiyun #define DA9062AA_E_GPI3_MASK BIT(3) 243*4882a593Smuzhiyun #define DA9062AA_E_GPI4_SHIFT 4 244*4882a593Smuzhiyun #define DA9062AA_E_GPI4_MASK BIT(4) 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun /* DA9062AA_IRQ_MASK_A = 0x00A */ 247*4882a593Smuzhiyun #define DA9062AA_M_NONKEY_SHIFT 0 248*4882a593Smuzhiyun #define DA9062AA_M_NONKEY_MASK 0x01 249*4882a593Smuzhiyun #define DA9062AA_M_ALARM_SHIFT 1 250*4882a593Smuzhiyun #define DA9062AA_M_ALARM_MASK BIT(1) 251*4882a593Smuzhiyun #define DA9062AA_M_TICK_SHIFT 2 252*4882a593Smuzhiyun #define DA9062AA_M_TICK_MASK BIT(2) 253*4882a593Smuzhiyun #define DA9062AA_M_WDG_WARN_SHIFT 3 254*4882a593Smuzhiyun #define DA9062AA_M_WDG_WARN_MASK BIT(3) 255*4882a593Smuzhiyun #define DA9062AA_M_SEQ_RDY_SHIFT 4 256*4882a593Smuzhiyun #define DA9062AA_M_SEQ_RDY_MASK BIT(4) 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun /* DA9062AA_IRQ_MASK_B = 0x00B */ 259*4882a593Smuzhiyun #define DA9062AA_M_TEMP_SHIFT 1 260*4882a593Smuzhiyun #define DA9062AA_M_TEMP_MASK BIT(1) 261*4882a593Smuzhiyun #define DA9062AA_M_LDO_LIM_SHIFT 3 262*4882a593Smuzhiyun #define DA9062AA_M_LDO_LIM_MASK BIT(3) 263*4882a593Smuzhiyun #define DA9062AA_M_DVC_RDY_SHIFT 5 264*4882a593Smuzhiyun #define DA9062AA_M_DVC_RDY_MASK BIT(5) 265*4882a593Smuzhiyun #define DA9062AA_M_VDD_WARN_SHIFT 7 266*4882a593Smuzhiyun #define DA9062AA_M_VDD_WARN_MASK BIT(7) 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun /* DA9062AA_IRQ_MASK_C = 0x00C */ 269*4882a593Smuzhiyun #define DA9062AA_M_GPI0_SHIFT 0 270*4882a593Smuzhiyun #define DA9062AA_M_GPI0_MASK 0x01 271*4882a593Smuzhiyun #define DA9062AA_M_GPI1_SHIFT 1 272*4882a593Smuzhiyun #define DA9062AA_M_GPI1_MASK BIT(1) 273*4882a593Smuzhiyun #define DA9062AA_M_GPI2_SHIFT 2 274*4882a593Smuzhiyun #define DA9062AA_M_GPI2_MASK BIT(2) 275*4882a593Smuzhiyun #define DA9062AA_M_GPI3_SHIFT 3 276*4882a593Smuzhiyun #define DA9062AA_M_GPI3_MASK BIT(3) 277*4882a593Smuzhiyun #define DA9062AA_M_GPI4_SHIFT 4 278*4882a593Smuzhiyun #define DA9062AA_M_GPI4_MASK BIT(4) 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun /* DA9062AA_CONTROL_A = 0x00E */ 281*4882a593Smuzhiyun #define DA9062AA_SYSTEM_EN_SHIFT 0 282*4882a593Smuzhiyun #define DA9062AA_SYSTEM_EN_MASK 0x01 283*4882a593Smuzhiyun #define DA9062AA_POWER_EN_SHIFT 1 284*4882a593Smuzhiyun #define DA9062AA_POWER_EN_MASK BIT(1) 285*4882a593Smuzhiyun #define DA9062AA_POWER1_EN_SHIFT 2 286*4882a593Smuzhiyun #define DA9062AA_POWER1_EN_MASK BIT(2) 287*4882a593Smuzhiyun #define DA9062AA_STANDBY_SHIFT 3 288*4882a593Smuzhiyun #define DA9062AA_STANDBY_MASK BIT(3) 289*4882a593Smuzhiyun #define DA9062AA_M_SYSTEM_EN_SHIFT 4 290*4882a593Smuzhiyun #define DA9062AA_M_SYSTEM_EN_MASK BIT(4) 291*4882a593Smuzhiyun #define DA9062AA_M_POWER_EN_SHIFT 5 292*4882a593Smuzhiyun #define DA9062AA_M_POWER_EN_MASK BIT(5) 293*4882a593Smuzhiyun #define DA9062AA_M_POWER1_EN_SHIFT 6 294*4882a593Smuzhiyun #define DA9062AA_M_POWER1_EN_MASK BIT(6) 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun /* DA9062AA_CONTROL_B = 0x00F */ 297*4882a593Smuzhiyun #define DA9062AA_WATCHDOG_PD_SHIFT 1 298*4882a593Smuzhiyun #define DA9062AA_WATCHDOG_PD_MASK BIT(1) 299*4882a593Smuzhiyun #define DA9062AA_FREEZE_EN_SHIFT 2 300*4882a593Smuzhiyun #define DA9062AA_FREEZE_EN_MASK BIT(2) 301*4882a593Smuzhiyun #define DA9062AA_NRES_MODE_SHIFT 3 302*4882a593Smuzhiyun #define DA9062AA_NRES_MODE_MASK BIT(3) 303*4882a593Smuzhiyun #define DA9062AA_NONKEY_LOCK_SHIFT 4 304*4882a593Smuzhiyun #define DA9062AA_NONKEY_LOCK_MASK BIT(4) 305*4882a593Smuzhiyun #define DA9062AA_NFREEZE_SHIFT 5 306*4882a593Smuzhiyun #define DA9062AA_NFREEZE_MASK (0x03 << 5) 307*4882a593Smuzhiyun #define DA9062AA_BUCK_SLOWSTART_SHIFT 7 308*4882a593Smuzhiyun #define DA9062AA_BUCK_SLOWSTART_MASK BIT(7) 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun /* DA9062AA_CONTROL_C = 0x010 */ 311*4882a593Smuzhiyun #define DA9062AA_DEBOUNCING_SHIFT 0 312*4882a593Smuzhiyun #define DA9062AA_DEBOUNCING_MASK 0x07 313*4882a593Smuzhiyun #define DA9062AA_AUTO_BOOT_SHIFT 3 314*4882a593Smuzhiyun #define DA9062AA_AUTO_BOOT_MASK BIT(3) 315*4882a593Smuzhiyun #define DA9062AA_OTPREAD_EN_SHIFT 4 316*4882a593Smuzhiyun #define DA9062AA_OTPREAD_EN_MASK BIT(4) 317*4882a593Smuzhiyun #define DA9062AA_SLEW_RATE_SHIFT 5 318*4882a593Smuzhiyun #define DA9062AA_SLEW_RATE_MASK (0x03 << 5) 319*4882a593Smuzhiyun #define DA9062AA_DEF_SUPPLY_SHIFT 7 320*4882a593Smuzhiyun #define DA9062AA_DEF_SUPPLY_MASK BIT(7) 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun /* DA9062AA_CONTROL_D = 0x011 */ 323*4882a593Smuzhiyun #define DA9062AA_TWDSCALE_SHIFT 0 324*4882a593Smuzhiyun #define DA9062AA_TWDSCALE_MASK 0x07 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun /* DA9062AA_CONTROL_E = 0x012 */ 327*4882a593Smuzhiyun #define DA9062AA_RTC_MODE_PD_SHIFT 0 328*4882a593Smuzhiyun #define DA9062AA_RTC_MODE_PD_MASK 0x01 329*4882a593Smuzhiyun #define DA9062AA_RTC_MODE_SD_SHIFT 1 330*4882a593Smuzhiyun #define DA9062AA_RTC_MODE_SD_MASK BIT(1) 331*4882a593Smuzhiyun #define DA9062AA_RTC_EN_SHIFT 2 332*4882a593Smuzhiyun #define DA9062AA_RTC_EN_MASK BIT(2) 333*4882a593Smuzhiyun #define DA9062AA_V_LOCK_SHIFT 7 334*4882a593Smuzhiyun #define DA9062AA_V_LOCK_MASK BIT(7) 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun /* DA9062AA_CONTROL_F = 0x013 */ 337*4882a593Smuzhiyun #define DA9062AA_WATCHDOG_SHIFT 0 338*4882a593Smuzhiyun #define DA9062AA_WATCHDOG_MASK 0x01 339*4882a593Smuzhiyun #define DA9062AA_SHUTDOWN_SHIFT 1 340*4882a593Smuzhiyun #define DA9062AA_SHUTDOWN_MASK BIT(1) 341*4882a593Smuzhiyun #define DA9062AA_WAKE_UP_SHIFT 2 342*4882a593Smuzhiyun #define DA9062AA_WAKE_UP_MASK BIT(2) 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun /* DA9062AA_PD_DIS = 0x014 */ 345*4882a593Smuzhiyun #define DA9062AA_GPI_DIS_SHIFT 0 346*4882a593Smuzhiyun #define DA9062AA_GPI_DIS_MASK 0x01 347*4882a593Smuzhiyun #define DA9062AA_PMIF_DIS_SHIFT 2 348*4882a593Smuzhiyun #define DA9062AA_PMIF_DIS_MASK BIT(2) 349*4882a593Smuzhiyun #define DA9062AA_CLDR_PAUSE_SHIFT 4 350*4882a593Smuzhiyun #define DA9062AA_CLDR_PAUSE_MASK BIT(4) 351*4882a593Smuzhiyun #define DA9062AA_BBAT_DIS_SHIFT 5 352*4882a593Smuzhiyun #define DA9062AA_BBAT_DIS_MASK BIT(5) 353*4882a593Smuzhiyun #define DA9062AA_OUT32K_PAUSE_SHIFT 6 354*4882a593Smuzhiyun #define DA9062AA_OUT32K_PAUSE_MASK BIT(6) 355*4882a593Smuzhiyun #define DA9062AA_PMCONT_DIS_SHIFT 7 356*4882a593Smuzhiyun #define DA9062AA_PMCONT_DIS_MASK BIT(7) 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun /* DA9062AA_GPIO_0_1 = 0x015 */ 359*4882a593Smuzhiyun #define DA9062AA_GPIO0_PIN_SHIFT 0 360*4882a593Smuzhiyun #define DA9062AA_GPIO0_PIN_MASK 0x03 361*4882a593Smuzhiyun #define DA9062AA_GPIO0_TYPE_SHIFT 2 362*4882a593Smuzhiyun #define DA9062AA_GPIO0_TYPE_MASK BIT(2) 363*4882a593Smuzhiyun #define DA9062AA_GPIO0_WEN_SHIFT 3 364*4882a593Smuzhiyun #define DA9062AA_GPIO0_WEN_MASK BIT(3) 365*4882a593Smuzhiyun #define DA9062AA_GPIO1_PIN_SHIFT 4 366*4882a593Smuzhiyun #define DA9062AA_GPIO1_PIN_MASK (0x03 << 4) 367*4882a593Smuzhiyun #define DA9062AA_GPIO1_TYPE_SHIFT 6 368*4882a593Smuzhiyun #define DA9062AA_GPIO1_TYPE_MASK BIT(6) 369*4882a593Smuzhiyun #define DA9062AA_GPIO1_WEN_SHIFT 7 370*4882a593Smuzhiyun #define DA9062AA_GPIO1_WEN_MASK BIT(7) 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun /* DA9062AA_GPIO_2_3 = 0x016 */ 373*4882a593Smuzhiyun #define DA9062AA_GPIO2_PIN_SHIFT 0 374*4882a593Smuzhiyun #define DA9062AA_GPIO2_PIN_MASK 0x03 375*4882a593Smuzhiyun #define DA9062AA_GPIO2_TYPE_SHIFT 2 376*4882a593Smuzhiyun #define DA9062AA_GPIO2_TYPE_MASK BIT(2) 377*4882a593Smuzhiyun #define DA9062AA_GPIO2_WEN_SHIFT 3 378*4882a593Smuzhiyun #define DA9062AA_GPIO2_WEN_MASK BIT(3) 379*4882a593Smuzhiyun #define DA9062AA_GPIO3_PIN_SHIFT 4 380*4882a593Smuzhiyun #define DA9062AA_GPIO3_PIN_MASK (0x03 << 4) 381*4882a593Smuzhiyun #define DA9062AA_GPIO3_TYPE_SHIFT 6 382*4882a593Smuzhiyun #define DA9062AA_GPIO3_TYPE_MASK BIT(6) 383*4882a593Smuzhiyun #define DA9062AA_GPIO3_WEN_SHIFT 7 384*4882a593Smuzhiyun #define DA9062AA_GPIO3_WEN_MASK BIT(7) 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun /* DA9062AA_GPIO_4 = 0x017 */ 387*4882a593Smuzhiyun #define DA9062AA_GPIO4_PIN_SHIFT 0 388*4882a593Smuzhiyun #define DA9062AA_GPIO4_PIN_MASK 0x03 389*4882a593Smuzhiyun #define DA9062AA_GPIO4_TYPE_SHIFT 2 390*4882a593Smuzhiyun #define DA9062AA_GPIO4_TYPE_MASK BIT(2) 391*4882a593Smuzhiyun #define DA9062AA_GPIO4_WEN_SHIFT 3 392*4882a593Smuzhiyun #define DA9062AA_GPIO4_WEN_MASK BIT(3) 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun /* DA9062AA_GPIO_WKUP_MODE = 0x01C */ 395*4882a593Smuzhiyun #define DA9062AA_GPIO0_WKUP_MODE_SHIFT 0 396*4882a593Smuzhiyun #define DA9062AA_GPIO0_WKUP_MODE_MASK 0x01 397*4882a593Smuzhiyun #define DA9062AA_GPIO1_WKUP_MODE_SHIFT 1 398*4882a593Smuzhiyun #define DA9062AA_GPIO1_WKUP_MODE_MASK BIT(1) 399*4882a593Smuzhiyun #define DA9062AA_GPIO2_WKUP_MODE_SHIFT 2 400*4882a593Smuzhiyun #define DA9062AA_GPIO2_WKUP_MODE_MASK BIT(2) 401*4882a593Smuzhiyun #define DA9062AA_GPIO3_WKUP_MODE_SHIFT 3 402*4882a593Smuzhiyun #define DA9062AA_GPIO3_WKUP_MODE_MASK BIT(3) 403*4882a593Smuzhiyun #define DA9062AA_GPIO4_WKUP_MODE_SHIFT 4 404*4882a593Smuzhiyun #define DA9062AA_GPIO4_WKUP_MODE_MASK BIT(4) 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun /* DA9062AA_GPIO_MODE0_4 = 0x01D */ 407*4882a593Smuzhiyun #define DA9062AA_GPIO0_MODE_SHIFT 0 408*4882a593Smuzhiyun #define DA9062AA_GPIO0_MODE_MASK 0x01 409*4882a593Smuzhiyun #define DA9062AA_GPIO1_MODE_SHIFT 1 410*4882a593Smuzhiyun #define DA9062AA_GPIO1_MODE_MASK BIT(1) 411*4882a593Smuzhiyun #define DA9062AA_GPIO2_MODE_SHIFT 2 412*4882a593Smuzhiyun #define DA9062AA_GPIO2_MODE_MASK BIT(2) 413*4882a593Smuzhiyun #define DA9062AA_GPIO3_MODE_SHIFT 3 414*4882a593Smuzhiyun #define DA9062AA_GPIO3_MODE_MASK BIT(3) 415*4882a593Smuzhiyun #define DA9062AA_GPIO4_MODE_SHIFT 4 416*4882a593Smuzhiyun #define DA9062AA_GPIO4_MODE_MASK BIT(4) 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun /* DA9062AA_GPIO_OUT0_2 = 0x01E */ 419*4882a593Smuzhiyun #define DA9062AA_GPIO0_OUT_SHIFT 0 420*4882a593Smuzhiyun #define DA9062AA_GPIO0_OUT_MASK 0x07 421*4882a593Smuzhiyun #define DA9062AA_GPIO1_OUT_SHIFT 3 422*4882a593Smuzhiyun #define DA9062AA_GPIO1_OUT_MASK (0x07 << 3) 423*4882a593Smuzhiyun #define DA9062AA_GPIO2_OUT_SHIFT 6 424*4882a593Smuzhiyun #define DA9062AA_GPIO2_OUT_MASK (0x03 << 6) 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun /* DA9062AA_GPIO_OUT3_4 = 0x01F */ 427*4882a593Smuzhiyun #define DA9062AA_GPIO3_OUT_SHIFT 0 428*4882a593Smuzhiyun #define DA9062AA_GPIO3_OUT_MASK 0x07 429*4882a593Smuzhiyun #define DA9062AA_GPIO4_OUT_SHIFT 3 430*4882a593Smuzhiyun #define DA9062AA_GPIO4_OUT_MASK (0x03 << 3) 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun /* DA9062AA_BUCK2_CONT = 0x020 */ 433*4882a593Smuzhiyun #define DA9062AA_BUCK2_EN_SHIFT 0 434*4882a593Smuzhiyun #define DA9062AA_BUCK2_EN_MASK 0x01 435*4882a593Smuzhiyun #define DA9062AA_BUCK2_GPI_SHIFT 1 436*4882a593Smuzhiyun #define DA9062AA_BUCK2_GPI_MASK (0x03 << 1) 437*4882a593Smuzhiyun #define DA9062AA_BUCK2_CONF_SHIFT 3 438*4882a593Smuzhiyun #define DA9062AA_BUCK2_CONF_MASK BIT(3) 439*4882a593Smuzhiyun #define DA9062AA_VBUCK2_GPI_SHIFT 5 440*4882a593Smuzhiyun #define DA9062AA_VBUCK2_GPI_MASK (0x03 << 5) 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun /* DA9062AA_BUCK1_CONT = 0x021 */ 443*4882a593Smuzhiyun #define DA9062AA_BUCK1_EN_SHIFT 0 444*4882a593Smuzhiyun #define DA9062AA_BUCK1_EN_MASK 0x01 445*4882a593Smuzhiyun #define DA9062AA_BUCK1_GPI_SHIFT 1 446*4882a593Smuzhiyun #define DA9062AA_BUCK1_GPI_MASK (0x03 << 1) 447*4882a593Smuzhiyun #define DA9062AA_BUCK1_CONF_SHIFT 3 448*4882a593Smuzhiyun #define DA9062AA_BUCK1_CONF_MASK BIT(3) 449*4882a593Smuzhiyun #define DA9062AA_VBUCK1_GPI_SHIFT 5 450*4882a593Smuzhiyun #define DA9062AA_VBUCK1_GPI_MASK (0x03 << 5) 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun /* DA9062AA_BUCK4_CONT = 0x022 */ 453*4882a593Smuzhiyun #define DA9062AA_BUCK4_EN_SHIFT 0 454*4882a593Smuzhiyun #define DA9062AA_BUCK4_EN_MASK 0x01 455*4882a593Smuzhiyun #define DA9062AA_BUCK4_GPI_SHIFT 1 456*4882a593Smuzhiyun #define DA9062AA_BUCK4_GPI_MASK (0x03 << 1) 457*4882a593Smuzhiyun #define DA9062AA_BUCK4_CONF_SHIFT 3 458*4882a593Smuzhiyun #define DA9062AA_BUCK4_CONF_MASK BIT(3) 459*4882a593Smuzhiyun #define DA9062AA_VBUCK4_GPI_SHIFT 5 460*4882a593Smuzhiyun #define DA9062AA_VBUCK4_GPI_MASK (0x03 << 5) 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun /* DA9062AA_BUCK3_CONT = 0x024 */ 463*4882a593Smuzhiyun #define DA9062AA_BUCK3_EN_SHIFT 0 464*4882a593Smuzhiyun #define DA9062AA_BUCK3_EN_MASK 0x01 465*4882a593Smuzhiyun #define DA9062AA_BUCK3_GPI_SHIFT 1 466*4882a593Smuzhiyun #define DA9062AA_BUCK3_GPI_MASK (0x03 << 1) 467*4882a593Smuzhiyun #define DA9062AA_BUCK3_CONF_SHIFT 3 468*4882a593Smuzhiyun #define DA9062AA_BUCK3_CONF_MASK BIT(3) 469*4882a593Smuzhiyun #define DA9062AA_VBUCK3_GPI_SHIFT 5 470*4882a593Smuzhiyun #define DA9062AA_VBUCK3_GPI_MASK (0x03 << 5) 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun /* DA9062AA_LDO1_CONT = 0x026 */ 473*4882a593Smuzhiyun #define DA9062AA_LDO1_EN_SHIFT 0 474*4882a593Smuzhiyun #define DA9062AA_LDO1_EN_MASK 0x01 475*4882a593Smuzhiyun #define DA9062AA_LDO1_GPI_SHIFT 1 476*4882a593Smuzhiyun #define DA9062AA_LDO1_GPI_MASK (0x03 << 1) 477*4882a593Smuzhiyun #define DA9062AA_LDO1_PD_DIS_SHIFT 3 478*4882a593Smuzhiyun #define DA9062AA_LDO1_PD_DIS_MASK BIT(3) 479*4882a593Smuzhiyun #define DA9062AA_VLDO1_GPI_SHIFT 5 480*4882a593Smuzhiyun #define DA9062AA_VLDO1_GPI_MASK (0x03 << 5) 481*4882a593Smuzhiyun #define DA9062AA_LDO1_CONF_SHIFT 7 482*4882a593Smuzhiyun #define DA9062AA_LDO1_CONF_MASK BIT(7) 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun /* DA9062AA_LDO2_CONT = 0x027 */ 485*4882a593Smuzhiyun #define DA9062AA_LDO2_EN_SHIFT 0 486*4882a593Smuzhiyun #define DA9062AA_LDO2_EN_MASK 0x01 487*4882a593Smuzhiyun #define DA9062AA_LDO2_GPI_SHIFT 1 488*4882a593Smuzhiyun #define DA9062AA_LDO2_GPI_MASK (0x03 << 1) 489*4882a593Smuzhiyun #define DA9062AA_LDO2_PD_DIS_SHIFT 3 490*4882a593Smuzhiyun #define DA9062AA_LDO2_PD_DIS_MASK BIT(3) 491*4882a593Smuzhiyun #define DA9062AA_VLDO2_GPI_SHIFT 5 492*4882a593Smuzhiyun #define DA9062AA_VLDO2_GPI_MASK (0x03 << 5) 493*4882a593Smuzhiyun #define DA9062AA_LDO2_CONF_SHIFT 7 494*4882a593Smuzhiyun #define DA9062AA_LDO2_CONF_MASK BIT(7) 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun /* DA9062AA_LDO3_CONT = 0x028 */ 497*4882a593Smuzhiyun #define DA9062AA_LDO3_EN_SHIFT 0 498*4882a593Smuzhiyun #define DA9062AA_LDO3_EN_MASK 0x01 499*4882a593Smuzhiyun #define DA9062AA_LDO3_GPI_SHIFT 1 500*4882a593Smuzhiyun #define DA9062AA_LDO3_GPI_MASK (0x03 << 1) 501*4882a593Smuzhiyun #define DA9062AA_LDO3_PD_DIS_SHIFT 3 502*4882a593Smuzhiyun #define DA9062AA_LDO3_PD_DIS_MASK BIT(3) 503*4882a593Smuzhiyun #define DA9062AA_VLDO3_GPI_SHIFT 5 504*4882a593Smuzhiyun #define DA9062AA_VLDO3_GPI_MASK (0x03 << 5) 505*4882a593Smuzhiyun #define DA9062AA_LDO3_CONF_SHIFT 7 506*4882a593Smuzhiyun #define DA9062AA_LDO3_CONF_MASK BIT(7) 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun /* DA9062AA_LDO4_CONT = 0x029 */ 509*4882a593Smuzhiyun #define DA9062AA_LDO4_EN_SHIFT 0 510*4882a593Smuzhiyun #define DA9062AA_LDO4_EN_MASK 0x01 511*4882a593Smuzhiyun #define DA9062AA_LDO4_GPI_SHIFT 1 512*4882a593Smuzhiyun #define DA9062AA_LDO4_GPI_MASK (0x03 << 1) 513*4882a593Smuzhiyun #define DA9062AA_LDO4_PD_DIS_SHIFT 3 514*4882a593Smuzhiyun #define DA9062AA_LDO4_PD_DIS_MASK BIT(3) 515*4882a593Smuzhiyun #define DA9062AA_VLDO4_GPI_SHIFT 5 516*4882a593Smuzhiyun #define DA9062AA_VLDO4_GPI_MASK (0x03 << 5) 517*4882a593Smuzhiyun #define DA9062AA_LDO4_CONF_SHIFT 7 518*4882a593Smuzhiyun #define DA9062AA_LDO4_CONF_MASK BIT(7) 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun /* DA9062AA_DVC_1 = 0x032 */ 521*4882a593Smuzhiyun #define DA9062AA_VBUCK1_SEL_SHIFT 0 522*4882a593Smuzhiyun #define DA9062AA_VBUCK1_SEL_MASK 0x01 523*4882a593Smuzhiyun #define DA9062AA_VBUCK2_SEL_SHIFT 1 524*4882a593Smuzhiyun #define DA9062AA_VBUCK2_SEL_MASK BIT(1) 525*4882a593Smuzhiyun #define DA9062AA_VBUCK4_SEL_SHIFT 2 526*4882a593Smuzhiyun #define DA9062AA_VBUCK4_SEL_MASK BIT(2) 527*4882a593Smuzhiyun #define DA9062AA_VBUCK3_SEL_SHIFT 3 528*4882a593Smuzhiyun #define DA9062AA_VBUCK3_SEL_MASK BIT(3) 529*4882a593Smuzhiyun #define DA9062AA_VLDO1_SEL_SHIFT 4 530*4882a593Smuzhiyun #define DA9062AA_VLDO1_SEL_MASK BIT(4) 531*4882a593Smuzhiyun #define DA9062AA_VLDO2_SEL_SHIFT 5 532*4882a593Smuzhiyun #define DA9062AA_VLDO2_SEL_MASK BIT(5) 533*4882a593Smuzhiyun #define DA9062AA_VLDO3_SEL_SHIFT 6 534*4882a593Smuzhiyun #define DA9062AA_VLDO3_SEL_MASK BIT(6) 535*4882a593Smuzhiyun #define DA9062AA_VLDO4_SEL_SHIFT 7 536*4882a593Smuzhiyun #define DA9062AA_VLDO4_SEL_MASK BIT(7) 537*4882a593Smuzhiyun 538*4882a593Smuzhiyun /* DA9062AA_COUNT_S = 0x040 */ 539*4882a593Smuzhiyun #define DA9062AA_COUNT_SEC_SHIFT 0 540*4882a593Smuzhiyun #define DA9062AA_COUNT_SEC_MASK 0x3f 541*4882a593Smuzhiyun #define DA9062AA_RTC_READ_SHIFT 7 542*4882a593Smuzhiyun #define DA9062AA_RTC_READ_MASK BIT(7) 543*4882a593Smuzhiyun 544*4882a593Smuzhiyun /* DA9062AA_COUNT_MI = 0x041 */ 545*4882a593Smuzhiyun #define DA9062AA_COUNT_MIN_SHIFT 0 546*4882a593Smuzhiyun #define DA9062AA_COUNT_MIN_MASK 0x3f 547*4882a593Smuzhiyun 548*4882a593Smuzhiyun /* DA9062AA_COUNT_H = 0x042 */ 549*4882a593Smuzhiyun #define DA9062AA_COUNT_HOUR_SHIFT 0 550*4882a593Smuzhiyun #define DA9062AA_COUNT_HOUR_MASK 0x1f 551*4882a593Smuzhiyun 552*4882a593Smuzhiyun /* DA9062AA_COUNT_D = 0x043 */ 553*4882a593Smuzhiyun #define DA9062AA_COUNT_DAY_SHIFT 0 554*4882a593Smuzhiyun #define DA9062AA_COUNT_DAY_MASK 0x1f 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun /* DA9062AA_COUNT_MO = 0x044 */ 557*4882a593Smuzhiyun #define DA9062AA_COUNT_MONTH_SHIFT 0 558*4882a593Smuzhiyun #define DA9062AA_COUNT_MONTH_MASK 0x0f 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun /* DA9062AA_COUNT_Y = 0x045 */ 561*4882a593Smuzhiyun #define DA9062AA_COUNT_YEAR_SHIFT 0 562*4882a593Smuzhiyun #define DA9062AA_COUNT_YEAR_MASK 0x3f 563*4882a593Smuzhiyun #define DA9062AA_MONITOR_SHIFT 6 564*4882a593Smuzhiyun #define DA9062AA_MONITOR_MASK BIT(6) 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun /* DA9062AA_ALARM_S = 0x046 */ 567*4882a593Smuzhiyun #define DA9062AA_ALARM_SEC_SHIFT 0 568*4882a593Smuzhiyun #define DA9062AA_ALARM_SEC_MASK 0x3f 569*4882a593Smuzhiyun #define DA9062AA_ALARM_STATUS_SHIFT 6 570*4882a593Smuzhiyun #define DA9062AA_ALARM_STATUS_MASK (0x03 << 6) 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun /* DA9062AA_ALARM_MI = 0x047 */ 573*4882a593Smuzhiyun #define DA9062AA_ALARM_MIN_SHIFT 0 574*4882a593Smuzhiyun #define DA9062AA_ALARM_MIN_MASK 0x3f 575*4882a593Smuzhiyun 576*4882a593Smuzhiyun /* DA9062AA_ALARM_H = 0x048 */ 577*4882a593Smuzhiyun #define DA9062AA_ALARM_HOUR_SHIFT 0 578*4882a593Smuzhiyun #define DA9062AA_ALARM_HOUR_MASK 0x1f 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun /* DA9062AA_ALARM_D = 0x049 */ 581*4882a593Smuzhiyun #define DA9062AA_ALARM_DAY_SHIFT 0 582*4882a593Smuzhiyun #define DA9062AA_ALARM_DAY_MASK 0x1f 583*4882a593Smuzhiyun 584*4882a593Smuzhiyun /* DA9062AA_ALARM_MO = 0x04A */ 585*4882a593Smuzhiyun #define DA9062AA_ALARM_MONTH_SHIFT 0 586*4882a593Smuzhiyun #define DA9062AA_ALARM_MONTH_MASK 0x0f 587*4882a593Smuzhiyun #define DA9062AA_TICK_TYPE_SHIFT 4 588*4882a593Smuzhiyun #define DA9062AA_TICK_TYPE_MASK BIT(4) 589*4882a593Smuzhiyun #define DA9062AA_TICK_WAKE_SHIFT 5 590*4882a593Smuzhiyun #define DA9062AA_TICK_WAKE_MASK BIT(5) 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun /* DA9062AA_ALARM_Y = 0x04B */ 593*4882a593Smuzhiyun #define DA9062AA_ALARM_YEAR_SHIFT 0 594*4882a593Smuzhiyun #define DA9062AA_ALARM_YEAR_MASK 0x3f 595*4882a593Smuzhiyun #define DA9062AA_ALARM_ON_SHIFT 6 596*4882a593Smuzhiyun #define DA9062AA_ALARM_ON_MASK BIT(6) 597*4882a593Smuzhiyun #define DA9062AA_TICK_ON_SHIFT 7 598*4882a593Smuzhiyun #define DA9062AA_TICK_ON_MASK BIT(7) 599*4882a593Smuzhiyun 600*4882a593Smuzhiyun /* DA9062AA_SECOND_A = 0x04C */ 601*4882a593Smuzhiyun #define DA9062AA_SECONDS_A_SHIFT 0 602*4882a593Smuzhiyun #define DA9062AA_SECONDS_A_MASK 0xff 603*4882a593Smuzhiyun 604*4882a593Smuzhiyun /* DA9062AA_SECOND_B = 0x04D */ 605*4882a593Smuzhiyun #define DA9062AA_SECONDS_B_SHIFT 0 606*4882a593Smuzhiyun #define DA9062AA_SECONDS_B_MASK 0xff 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun /* DA9062AA_SECOND_C = 0x04E */ 609*4882a593Smuzhiyun #define DA9062AA_SECONDS_C_SHIFT 0 610*4882a593Smuzhiyun #define DA9062AA_SECONDS_C_MASK 0xff 611*4882a593Smuzhiyun 612*4882a593Smuzhiyun /* DA9062AA_SECOND_D = 0x04F */ 613*4882a593Smuzhiyun #define DA9062AA_SECONDS_D_SHIFT 0 614*4882a593Smuzhiyun #define DA9062AA_SECONDS_D_MASK 0xff 615*4882a593Smuzhiyun 616*4882a593Smuzhiyun /* DA9062AA_SEQ = 0x081 */ 617*4882a593Smuzhiyun #define DA9062AA_SEQ_POINTER_SHIFT 0 618*4882a593Smuzhiyun #define DA9062AA_SEQ_POINTER_MASK 0x0f 619*4882a593Smuzhiyun #define DA9062AA_NXT_SEQ_START_SHIFT 4 620*4882a593Smuzhiyun #define DA9062AA_NXT_SEQ_START_MASK (0x0f << 4) 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun /* DA9062AA_SEQ_TIMER = 0x082 */ 623*4882a593Smuzhiyun #define DA9062AA_SEQ_TIME_SHIFT 0 624*4882a593Smuzhiyun #define DA9062AA_SEQ_TIME_MASK 0x0f 625*4882a593Smuzhiyun #define DA9062AA_SEQ_DUMMY_SHIFT 4 626*4882a593Smuzhiyun #define DA9062AA_SEQ_DUMMY_MASK (0x0f << 4) 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun /* DA9062AA_ID_2_1 = 0x083 */ 629*4882a593Smuzhiyun #define DA9062AA_LDO1_STEP_SHIFT 0 630*4882a593Smuzhiyun #define DA9062AA_LDO1_STEP_MASK 0x0f 631*4882a593Smuzhiyun #define DA9062AA_LDO2_STEP_SHIFT 4 632*4882a593Smuzhiyun #define DA9062AA_LDO2_STEP_MASK (0x0f << 4) 633*4882a593Smuzhiyun 634*4882a593Smuzhiyun /* DA9062AA_ID_4_3 = 0x084 */ 635*4882a593Smuzhiyun #define DA9062AA_LDO3_STEP_SHIFT 0 636*4882a593Smuzhiyun #define DA9062AA_LDO3_STEP_MASK 0x0f 637*4882a593Smuzhiyun #define DA9062AA_LDO4_STEP_SHIFT 4 638*4882a593Smuzhiyun #define DA9062AA_LDO4_STEP_MASK (0x0f << 4) 639*4882a593Smuzhiyun 640*4882a593Smuzhiyun /* DA9062AA_ID_12_11 = 0x088 */ 641*4882a593Smuzhiyun #define DA9062AA_PD_DIS_STEP_SHIFT 4 642*4882a593Smuzhiyun #define DA9062AA_PD_DIS_STEP_MASK (0x0f << 4) 643*4882a593Smuzhiyun 644*4882a593Smuzhiyun /* DA9062AA_ID_14_13 = 0x089 */ 645*4882a593Smuzhiyun #define DA9062AA_BUCK1_STEP_SHIFT 0 646*4882a593Smuzhiyun #define DA9062AA_BUCK1_STEP_MASK 0x0f 647*4882a593Smuzhiyun #define DA9062AA_BUCK2_STEP_SHIFT 4 648*4882a593Smuzhiyun #define DA9062AA_BUCK2_STEP_MASK (0x0f << 4) 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun /* DA9062AA_ID_16_15 = 0x08A */ 651*4882a593Smuzhiyun #define DA9062AA_BUCK4_STEP_SHIFT 0 652*4882a593Smuzhiyun #define DA9062AA_BUCK4_STEP_MASK 0x0f 653*4882a593Smuzhiyun #define DA9062AA_BUCK3_STEP_SHIFT 4 654*4882a593Smuzhiyun #define DA9062AA_BUCK3_STEP_MASK (0x0f << 4) 655*4882a593Smuzhiyun 656*4882a593Smuzhiyun /* DA9062AA_ID_22_21 = 0x08D */ 657*4882a593Smuzhiyun #define DA9062AA_GP_RISE1_STEP_SHIFT 0 658*4882a593Smuzhiyun #define DA9062AA_GP_RISE1_STEP_MASK 0x0f 659*4882a593Smuzhiyun #define DA9062AA_GP_FALL1_STEP_SHIFT 4 660*4882a593Smuzhiyun #define DA9062AA_GP_FALL1_STEP_MASK (0x0f << 4) 661*4882a593Smuzhiyun 662*4882a593Smuzhiyun /* DA9062AA_ID_24_23 = 0x08E */ 663*4882a593Smuzhiyun #define DA9062AA_GP_RISE2_STEP_SHIFT 0 664*4882a593Smuzhiyun #define DA9062AA_GP_RISE2_STEP_MASK 0x0f 665*4882a593Smuzhiyun #define DA9062AA_GP_FALL2_STEP_SHIFT 4 666*4882a593Smuzhiyun #define DA9062AA_GP_FALL2_STEP_MASK (0x0f << 4) 667*4882a593Smuzhiyun 668*4882a593Smuzhiyun /* DA9062AA_ID_26_25 = 0x08F */ 669*4882a593Smuzhiyun #define DA9062AA_GP_RISE3_STEP_SHIFT 0 670*4882a593Smuzhiyun #define DA9062AA_GP_RISE3_STEP_MASK 0x0f 671*4882a593Smuzhiyun #define DA9062AA_GP_FALL3_STEP_SHIFT 4 672*4882a593Smuzhiyun #define DA9062AA_GP_FALL3_STEP_MASK (0x0f << 4) 673*4882a593Smuzhiyun 674*4882a593Smuzhiyun /* DA9062AA_ID_28_27 = 0x090 */ 675*4882a593Smuzhiyun #define DA9062AA_GP_RISE4_STEP_SHIFT 0 676*4882a593Smuzhiyun #define DA9062AA_GP_RISE4_STEP_MASK 0x0f 677*4882a593Smuzhiyun #define DA9062AA_GP_FALL4_STEP_SHIFT 4 678*4882a593Smuzhiyun #define DA9062AA_GP_FALL4_STEP_MASK (0x0f << 4) 679*4882a593Smuzhiyun 680*4882a593Smuzhiyun /* DA9062AA_ID_30_29 = 0x091 */ 681*4882a593Smuzhiyun #define DA9062AA_GP_RISE5_STEP_SHIFT 0 682*4882a593Smuzhiyun #define DA9062AA_GP_RISE5_STEP_MASK 0x0f 683*4882a593Smuzhiyun #define DA9062AA_GP_FALL5_STEP_SHIFT 4 684*4882a593Smuzhiyun #define DA9062AA_GP_FALL5_STEP_MASK (0x0f << 4) 685*4882a593Smuzhiyun 686*4882a593Smuzhiyun /* DA9062AA_ID_32_31 = 0x092 */ 687*4882a593Smuzhiyun #define DA9062AA_WAIT_STEP_SHIFT 0 688*4882a593Smuzhiyun #define DA9062AA_WAIT_STEP_MASK 0x0f 689*4882a593Smuzhiyun #define DA9062AA_EN32K_STEP_SHIFT 4 690*4882a593Smuzhiyun #define DA9062AA_EN32K_STEP_MASK (0x0f << 4) 691*4882a593Smuzhiyun 692*4882a593Smuzhiyun /* DA9062AA_SEQ_A = 0x095 */ 693*4882a593Smuzhiyun #define DA9062AA_SYSTEM_END_SHIFT 0 694*4882a593Smuzhiyun #define DA9062AA_SYSTEM_END_MASK 0x0f 695*4882a593Smuzhiyun #define DA9062AA_POWER_END_SHIFT 4 696*4882a593Smuzhiyun #define DA9062AA_POWER_END_MASK (0x0f << 4) 697*4882a593Smuzhiyun 698*4882a593Smuzhiyun /* DA9062AA_SEQ_B = 0x096 */ 699*4882a593Smuzhiyun #define DA9062AA_MAX_COUNT_SHIFT 0 700*4882a593Smuzhiyun #define DA9062AA_MAX_COUNT_MASK 0x0f 701*4882a593Smuzhiyun #define DA9062AA_PART_DOWN_SHIFT 4 702*4882a593Smuzhiyun #define DA9062AA_PART_DOWN_MASK (0x0f << 4) 703*4882a593Smuzhiyun 704*4882a593Smuzhiyun /* DA9062AA_WAIT = 0x097 */ 705*4882a593Smuzhiyun #define DA9062AA_WAIT_TIME_SHIFT 0 706*4882a593Smuzhiyun #define DA9062AA_WAIT_TIME_MASK 0x0f 707*4882a593Smuzhiyun #define DA9062AA_WAIT_MODE_SHIFT 4 708*4882a593Smuzhiyun #define DA9062AA_WAIT_MODE_MASK BIT(4) 709*4882a593Smuzhiyun #define DA9062AA_TIME_OUT_SHIFT 5 710*4882a593Smuzhiyun #define DA9062AA_TIME_OUT_MASK BIT(5) 711*4882a593Smuzhiyun #define DA9062AA_WAIT_DIR_SHIFT 6 712*4882a593Smuzhiyun #define DA9062AA_WAIT_DIR_MASK (0x03 << 6) 713*4882a593Smuzhiyun 714*4882a593Smuzhiyun /* DA9062AA_EN_32K = 0x098 */ 715*4882a593Smuzhiyun #define DA9062AA_STABILISATION_TIME_SHIFT 0 716*4882a593Smuzhiyun #define DA9062AA_STABILISATION_TIME_MASK 0x07 717*4882a593Smuzhiyun #define DA9062AA_CRYSTAL_SHIFT 3 718*4882a593Smuzhiyun #define DA9062AA_CRYSTAL_MASK BIT(3) 719*4882a593Smuzhiyun #define DA9062AA_DELAY_MODE_SHIFT 4 720*4882a593Smuzhiyun #define DA9062AA_DELAY_MODE_MASK BIT(4) 721*4882a593Smuzhiyun #define DA9062AA_OUT_CLOCK_SHIFT 5 722*4882a593Smuzhiyun #define DA9062AA_OUT_CLOCK_MASK BIT(5) 723*4882a593Smuzhiyun #define DA9062AA_RTC_CLOCK_SHIFT 6 724*4882a593Smuzhiyun #define DA9062AA_RTC_CLOCK_MASK BIT(6) 725*4882a593Smuzhiyun #define DA9062AA_EN_32KOUT_SHIFT 7 726*4882a593Smuzhiyun #define DA9062AA_EN_32KOUT_MASK BIT(7) 727*4882a593Smuzhiyun 728*4882a593Smuzhiyun /* DA9062AA_RESET = 0x099 */ 729*4882a593Smuzhiyun #define DA9062AA_RESET_TIMER_SHIFT 0 730*4882a593Smuzhiyun #define DA9062AA_RESET_TIMER_MASK 0x3f 731*4882a593Smuzhiyun #define DA9062AA_RESET_EVENT_SHIFT 6 732*4882a593Smuzhiyun #define DA9062AA_RESET_EVENT_MASK (0x03 << 6) 733*4882a593Smuzhiyun 734*4882a593Smuzhiyun /* DA9062AA_BUCK_ILIM_A = 0x09A */ 735*4882a593Smuzhiyun #define DA9062AA_BUCK3_ILIM_SHIFT 0 736*4882a593Smuzhiyun #define DA9062AA_BUCK3_ILIM_MASK 0x0f 737*4882a593Smuzhiyun 738*4882a593Smuzhiyun /* DA9062AA_BUCK_ILIM_B = 0x09B */ 739*4882a593Smuzhiyun #define DA9062AA_BUCK4_ILIM_SHIFT 0 740*4882a593Smuzhiyun #define DA9062AA_BUCK4_ILIM_MASK 0x0f 741*4882a593Smuzhiyun 742*4882a593Smuzhiyun /* DA9062AA_BUCK_ILIM_C = 0x09C */ 743*4882a593Smuzhiyun #define DA9062AA_BUCK1_ILIM_SHIFT 0 744*4882a593Smuzhiyun #define DA9062AA_BUCK1_ILIM_MASK 0x0f 745*4882a593Smuzhiyun #define DA9062AA_BUCK2_ILIM_SHIFT 4 746*4882a593Smuzhiyun #define DA9062AA_BUCK2_ILIM_MASK (0x0f << 4) 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun /* DA9062AA_BUCK2_CFG = 0x09D */ 749*4882a593Smuzhiyun #define DA9062AA_BUCK2_PD_DIS_SHIFT 5 750*4882a593Smuzhiyun #define DA9062AA_BUCK2_PD_DIS_MASK BIT(5) 751*4882a593Smuzhiyun #define DA9062AA_BUCK2_MODE_SHIFT 6 752*4882a593Smuzhiyun #define DA9062AA_BUCK2_MODE_MASK (0x03 << 6) 753*4882a593Smuzhiyun 754*4882a593Smuzhiyun /* DA9062AA_BUCK1_CFG = 0x09E */ 755*4882a593Smuzhiyun #define DA9062AA_BUCK1_PD_DIS_SHIFT 5 756*4882a593Smuzhiyun #define DA9062AA_BUCK1_PD_DIS_MASK BIT(5) 757*4882a593Smuzhiyun #define DA9062AA_BUCK1_MODE_SHIFT 6 758*4882a593Smuzhiyun #define DA9062AA_BUCK1_MODE_MASK (0x03 << 6) 759*4882a593Smuzhiyun 760*4882a593Smuzhiyun /* DA9062AA_BUCK4_CFG = 0x09F */ 761*4882a593Smuzhiyun #define DA9062AA_BUCK4_VTTR_EN_SHIFT 3 762*4882a593Smuzhiyun #define DA9062AA_BUCK4_VTTR_EN_MASK BIT(3) 763*4882a593Smuzhiyun #define DA9062AA_BUCK4_VTT_EN_SHIFT 4 764*4882a593Smuzhiyun #define DA9062AA_BUCK4_VTT_EN_MASK BIT(4) 765*4882a593Smuzhiyun #define DA9062AA_BUCK4_PD_DIS_SHIFT 5 766*4882a593Smuzhiyun #define DA9062AA_BUCK4_PD_DIS_MASK BIT(5) 767*4882a593Smuzhiyun #define DA9062AA_BUCK4_MODE_SHIFT 6 768*4882a593Smuzhiyun #define DA9062AA_BUCK4_MODE_MASK (0x03 << 6) 769*4882a593Smuzhiyun 770*4882a593Smuzhiyun /* DA9062AA_BUCK3_CFG = 0x0A0 */ 771*4882a593Smuzhiyun #define DA9062AA_BUCK3_PD_DIS_SHIFT 5 772*4882a593Smuzhiyun #define DA9062AA_BUCK3_PD_DIS_MASK BIT(5) 773*4882a593Smuzhiyun #define DA9062AA_BUCK3_MODE_SHIFT 6 774*4882a593Smuzhiyun #define DA9062AA_BUCK3_MODE_MASK (0x03 << 6) 775*4882a593Smuzhiyun 776*4882a593Smuzhiyun /* DA9062AA_VBUCK2_A = 0x0A3 */ 777*4882a593Smuzhiyun #define DA9062AA_VBUCK2_A_SHIFT 0 778*4882a593Smuzhiyun #define DA9062AA_VBUCK2_A_MASK 0x7f 779*4882a593Smuzhiyun #define DA9062AA_BUCK2_SL_A_SHIFT 7 780*4882a593Smuzhiyun #define DA9062AA_BUCK2_SL_A_MASK BIT(7) 781*4882a593Smuzhiyun 782*4882a593Smuzhiyun /* DA9062AA_VBUCK1_A = 0x0A4 */ 783*4882a593Smuzhiyun #define DA9062AA_VBUCK1_A_SHIFT 0 784*4882a593Smuzhiyun #define DA9062AA_VBUCK1_A_MASK 0x7f 785*4882a593Smuzhiyun #define DA9062AA_BUCK1_SL_A_SHIFT 7 786*4882a593Smuzhiyun #define DA9062AA_BUCK1_SL_A_MASK BIT(7) 787*4882a593Smuzhiyun 788*4882a593Smuzhiyun /* DA9062AA_VBUCK4_A = 0x0A5 */ 789*4882a593Smuzhiyun #define DA9062AA_VBUCK4_A_SHIFT 0 790*4882a593Smuzhiyun #define DA9062AA_VBUCK4_A_MASK 0x7f 791*4882a593Smuzhiyun #define DA9062AA_BUCK4_SL_A_SHIFT 7 792*4882a593Smuzhiyun #define DA9062AA_BUCK4_SL_A_MASK BIT(7) 793*4882a593Smuzhiyun 794*4882a593Smuzhiyun /* DA9062AA_VBUCK3_A = 0x0A7 */ 795*4882a593Smuzhiyun #define DA9062AA_VBUCK3_A_SHIFT 0 796*4882a593Smuzhiyun #define DA9062AA_VBUCK3_A_MASK 0x7f 797*4882a593Smuzhiyun #define DA9062AA_BUCK3_SL_A_SHIFT 7 798*4882a593Smuzhiyun #define DA9062AA_BUCK3_SL_A_MASK BIT(7) 799*4882a593Smuzhiyun 800*4882a593Smuzhiyun /* DA9062AA_VLDO[1-4]_A common */ 801*4882a593Smuzhiyun #define DA9062AA_VLDO_A_MIN_SEL 2 802*4882a593Smuzhiyun 803*4882a593Smuzhiyun /* DA9062AA_VLDO1_A = 0x0A9 */ 804*4882a593Smuzhiyun #define DA9062AA_VLDO1_A_SHIFT 0 805*4882a593Smuzhiyun #define DA9062AA_VLDO1_A_MASK 0x3f 806*4882a593Smuzhiyun #define DA9062AA_LDO1_SL_A_SHIFT 7 807*4882a593Smuzhiyun #define DA9062AA_LDO1_SL_A_MASK BIT(7) 808*4882a593Smuzhiyun 809*4882a593Smuzhiyun /* DA9062AA_VLDO2_A = 0x0AA */ 810*4882a593Smuzhiyun #define DA9062AA_VLDO2_A_SHIFT 0 811*4882a593Smuzhiyun #define DA9062AA_VLDO2_A_MASK 0x3f 812*4882a593Smuzhiyun #define DA9062AA_LDO2_SL_A_SHIFT 7 813*4882a593Smuzhiyun #define DA9062AA_LDO2_SL_A_MASK BIT(7) 814*4882a593Smuzhiyun 815*4882a593Smuzhiyun /* DA9062AA_VLDO3_A = 0x0AB */ 816*4882a593Smuzhiyun #define DA9062AA_VLDO3_A_SHIFT 0 817*4882a593Smuzhiyun #define DA9062AA_VLDO3_A_MASK 0x3f 818*4882a593Smuzhiyun #define DA9062AA_LDO3_SL_A_SHIFT 7 819*4882a593Smuzhiyun #define DA9062AA_LDO3_SL_A_MASK BIT(7) 820*4882a593Smuzhiyun 821*4882a593Smuzhiyun /* DA9062AA_VLDO4_A = 0x0AC */ 822*4882a593Smuzhiyun #define DA9062AA_VLDO4_A_SHIFT 0 823*4882a593Smuzhiyun #define DA9062AA_VLDO4_A_MASK 0x3f 824*4882a593Smuzhiyun #define DA9062AA_LDO4_SL_A_SHIFT 7 825*4882a593Smuzhiyun #define DA9062AA_LDO4_SL_A_MASK BIT(7) 826*4882a593Smuzhiyun 827*4882a593Smuzhiyun /* DA9062AA_VBUCK2_B = 0x0B4 */ 828*4882a593Smuzhiyun #define DA9062AA_VBUCK2_B_SHIFT 0 829*4882a593Smuzhiyun #define DA9062AA_VBUCK2_B_MASK 0x7f 830*4882a593Smuzhiyun #define DA9062AA_BUCK2_SL_B_SHIFT 7 831*4882a593Smuzhiyun #define DA9062AA_BUCK2_SL_B_MASK BIT(7) 832*4882a593Smuzhiyun 833*4882a593Smuzhiyun /* DA9062AA_VBUCK1_B = 0x0B5 */ 834*4882a593Smuzhiyun #define DA9062AA_VBUCK1_B_SHIFT 0 835*4882a593Smuzhiyun #define DA9062AA_VBUCK1_B_MASK 0x7f 836*4882a593Smuzhiyun #define DA9062AA_BUCK1_SL_B_SHIFT 7 837*4882a593Smuzhiyun #define DA9062AA_BUCK1_SL_B_MASK BIT(7) 838*4882a593Smuzhiyun 839*4882a593Smuzhiyun /* DA9062AA_VBUCK4_B = 0x0B6 */ 840*4882a593Smuzhiyun #define DA9062AA_VBUCK4_B_SHIFT 0 841*4882a593Smuzhiyun #define DA9062AA_VBUCK4_B_MASK 0x7f 842*4882a593Smuzhiyun #define DA9062AA_BUCK4_SL_B_SHIFT 7 843*4882a593Smuzhiyun #define DA9062AA_BUCK4_SL_B_MASK BIT(7) 844*4882a593Smuzhiyun 845*4882a593Smuzhiyun /* DA9062AA_VBUCK3_B = 0x0B8 */ 846*4882a593Smuzhiyun #define DA9062AA_VBUCK3_B_SHIFT 0 847*4882a593Smuzhiyun #define DA9062AA_VBUCK3_B_MASK 0x7f 848*4882a593Smuzhiyun #define DA9062AA_BUCK3_SL_B_SHIFT 7 849*4882a593Smuzhiyun #define DA9062AA_BUCK3_SL_B_MASK BIT(7) 850*4882a593Smuzhiyun 851*4882a593Smuzhiyun /* DA9062AA_VLDO1_B = 0x0BA */ 852*4882a593Smuzhiyun #define DA9062AA_VLDO1_B_SHIFT 0 853*4882a593Smuzhiyun #define DA9062AA_VLDO1_B_MASK 0x3f 854*4882a593Smuzhiyun #define DA9062AA_LDO1_SL_B_SHIFT 7 855*4882a593Smuzhiyun #define DA9062AA_LDO1_SL_B_MASK BIT(7) 856*4882a593Smuzhiyun 857*4882a593Smuzhiyun /* DA9062AA_VLDO2_B = 0x0BB */ 858*4882a593Smuzhiyun #define DA9062AA_VLDO2_B_SHIFT 0 859*4882a593Smuzhiyun #define DA9062AA_VLDO2_B_MASK 0x3f 860*4882a593Smuzhiyun #define DA9062AA_LDO2_SL_B_SHIFT 7 861*4882a593Smuzhiyun #define DA9062AA_LDO2_SL_B_MASK BIT(7) 862*4882a593Smuzhiyun 863*4882a593Smuzhiyun /* DA9062AA_VLDO3_B = 0x0BC */ 864*4882a593Smuzhiyun #define DA9062AA_VLDO3_B_SHIFT 0 865*4882a593Smuzhiyun #define DA9062AA_VLDO3_B_MASK 0x3f 866*4882a593Smuzhiyun #define DA9062AA_LDO3_SL_B_SHIFT 7 867*4882a593Smuzhiyun #define DA9062AA_LDO3_SL_B_MASK BIT(7) 868*4882a593Smuzhiyun 869*4882a593Smuzhiyun /* DA9062AA_VLDO4_B = 0x0BD */ 870*4882a593Smuzhiyun #define DA9062AA_VLDO4_B_SHIFT 0 871*4882a593Smuzhiyun #define DA9062AA_VLDO4_B_MASK 0x3f 872*4882a593Smuzhiyun #define DA9062AA_LDO4_SL_B_SHIFT 7 873*4882a593Smuzhiyun #define DA9062AA_LDO4_SL_B_MASK BIT(7) 874*4882a593Smuzhiyun 875*4882a593Smuzhiyun /* DA9062AA_BBAT_CONT = 0x0C5 */ 876*4882a593Smuzhiyun #define DA9062AA_BCHG_VSET_SHIFT 0 877*4882a593Smuzhiyun #define DA9062AA_BCHG_VSET_MASK 0x0f 878*4882a593Smuzhiyun #define DA9062AA_BCHG_ISET_SHIFT 4 879*4882a593Smuzhiyun #define DA9062AA_BCHG_ISET_MASK (0x0f << 4) 880*4882a593Smuzhiyun 881*4882a593Smuzhiyun /* DA9062AA_INTERFACE = 0x105 */ 882*4882a593Smuzhiyun #define DA9062AA_IF_BASE_ADDR_SHIFT 4 883*4882a593Smuzhiyun #define DA9062AA_IF_BASE_ADDR_MASK (0x0f << 4) 884*4882a593Smuzhiyun 885*4882a593Smuzhiyun /* DA9062AA_CONFIG_A = 0x106 */ 886*4882a593Smuzhiyun #define DA9062AA_PM_I_V_SHIFT 0 887*4882a593Smuzhiyun #define DA9062AA_PM_I_V_MASK 0x01 888*4882a593Smuzhiyun #define DA9062AA_PM_O_TYPE_SHIFT 2 889*4882a593Smuzhiyun #define DA9062AA_PM_O_TYPE_MASK BIT(2) 890*4882a593Smuzhiyun #define DA9062AA_IRQ_TYPE_SHIFT 3 891*4882a593Smuzhiyun #define DA9062AA_IRQ_TYPE_MASK BIT(3) 892*4882a593Smuzhiyun #define DA9062AA_PM_IF_V_SHIFT 4 893*4882a593Smuzhiyun #define DA9062AA_PM_IF_V_MASK BIT(4) 894*4882a593Smuzhiyun #define DA9062AA_PM_IF_FMP_SHIFT 5 895*4882a593Smuzhiyun #define DA9062AA_PM_IF_FMP_MASK BIT(5) 896*4882a593Smuzhiyun #define DA9062AA_PM_IF_HSM_SHIFT 6 897*4882a593Smuzhiyun #define DA9062AA_PM_IF_HSM_MASK BIT(6) 898*4882a593Smuzhiyun 899*4882a593Smuzhiyun /* DA9062AA_CONFIG_B = 0x107 */ 900*4882a593Smuzhiyun #define DA9062AA_VDD_FAULT_ADJ_SHIFT 0 901*4882a593Smuzhiyun #define DA9062AA_VDD_FAULT_ADJ_MASK 0x0f 902*4882a593Smuzhiyun #define DA9062AA_VDD_HYST_ADJ_SHIFT 4 903*4882a593Smuzhiyun #define DA9062AA_VDD_HYST_ADJ_MASK (0x07 << 4) 904*4882a593Smuzhiyun 905*4882a593Smuzhiyun /* DA9062AA_CONFIG_C = 0x108 */ 906*4882a593Smuzhiyun #define DA9062AA_BUCK_ACTV_DISCHRG_SHIFT 2 907*4882a593Smuzhiyun #define DA9062AA_BUCK_ACTV_DISCHRG_MASK BIT(2) 908*4882a593Smuzhiyun #define DA9062AA_BUCK1_CLK_INV_SHIFT 3 909*4882a593Smuzhiyun #define DA9062AA_BUCK1_CLK_INV_MASK BIT(3) 910*4882a593Smuzhiyun #define DA9062AA_BUCK4_CLK_INV_SHIFT 4 911*4882a593Smuzhiyun #define DA9062AA_BUCK4_CLK_INV_MASK BIT(4) 912*4882a593Smuzhiyun #define DA9062AA_BUCK3_CLK_INV_SHIFT 6 913*4882a593Smuzhiyun #define DA9062AA_BUCK3_CLK_INV_MASK BIT(6) 914*4882a593Smuzhiyun 915*4882a593Smuzhiyun /* DA9062AA_CONFIG_D = 0x109 */ 916*4882a593Smuzhiyun #define DA9062AA_GPI_V_SHIFT 0 917*4882a593Smuzhiyun #define DA9062AA_GPI_V_MASK 0x01 918*4882a593Smuzhiyun #define DA9062AA_NIRQ_MODE_SHIFT 1 919*4882a593Smuzhiyun #define DA9062AA_NIRQ_MODE_MASK BIT(1) 920*4882a593Smuzhiyun #define DA9062AA_SYSTEM_EN_RD_SHIFT 2 921*4882a593Smuzhiyun #define DA9062AA_SYSTEM_EN_RD_MASK BIT(2) 922*4882a593Smuzhiyun #define DA9062AA_FORCE_RESET_SHIFT 5 923*4882a593Smuzhiyun #define DA9062AA_FORCE_RESET_MASK BIT(5) 924*4882a593Smuzhiyun 925*4882a593Smuzhiyun /* DA9062AA_CONFIG_E = 0x10A */ 926*4882a593Smuzhiyun #define DA9062AA_BUCK1_AUTO_SHIFT 0 927*4882a593Smuzhiyun #define DA9062AA_BUCK1_AUTO_MASK 0x01 928*4882a593Smuzhiyun #define DA9062AA_BUCK2_AUTO_SHIFT 1 929*4882a593Smuzhiyun #define DA9062AA_BUCK2_AUTO_MASK BIT(1) 930*4882a593Smuzhiyun #define DA9062AA_BUCK4_AUTO_SHIFT 2 931*4882a593Smuzhiyun #define DA9062AA_BUCK4_AUTO_MASK BIT(2) 932*4882a593Smuzhiyun #define DA9062AA_BUCK3_AUTO_SHIFT 4 933*4882a593Smuzhiyun #define DA9062AA_BUCK3_AUTO_MASK BIT(4) 934*4882a593Smuzhiyun 935*4882a593Smuzhiyun /* DA9062AA_CONFIG_G = 0x10C */ 936*4882a593Smuzhiyun #define DA9062AA_LDO1_AUTO_SHIFT 0 937*4882a593Smuzhiyun #define DA9062AA_LDO1_AUTO_MASK 0x01 938*4882a593Smuzhiyun #define DA9062AA_LDO2_AUTO_SHIFT 1 939*4882a593Smuzhiyun #define DA9062AA_LDO2_AUTO_MASK BIT(1) 940*4882a593Smuzhiyun #define DA9062AA_LDO3_AUTO_SHIFT 2 941*4882a593Smuzhiyun #define DA9062AA_LDO3_AUTO_MASK BIT(2) 942*4882a593Smuzhiyun #define DA9062AA_LDO4_AUTO_SHIFT 3 943*4882a593Smuzhiyun #define DA9062AA_LDO4_AUTO_MASK BIT(3) 944*4882a593Smuzhiyun 945*4882a593Smuzhiyun /* DA9062AA_CONFIG_H = 0x10D */ 946*4882a593Smuzhiyun #define DA9062AA_BUCK1_2_MERGE_SHIFT 3 947*4882a593Smuzhiyun #define DA9062AA_BUCK1_2_MERGE_MASK BIT(3) 948*4882a593Smuzhiyun #define DA9062AA_BUCK2_OD_SHIFT 5 949*4882a593Smuzhiyun #define DA9062AA_BUCK2_OD_MASK BIT(5) 950*4882a593Smuzhiyun #define DA9062AA_BUCK1_OD_SHIFT 6 951*4882a593Smuzhiyun #define DA9062AA_BUCK1_OD_MASK BIT(6) 952*4882a593Smuzhiyun 953*4882a593Smuzhiyun /* DA9062AA_CONFIG_I = 0x10E */ 954*4882a593Smuzhiyun #define DA9062AA_NONKEY_PIN_SHIFT 0 955*4882a593Smuzhiyun #define DA9062AA_NONKEY_PIN_MASK 0x03 956*4882a593Smuzhiyun #define DA9062AA_nONKEY_SD_SHIFT 2 957*4882a593Smuzhiyun #define DA9062AA_nONKEY_SD_MASK BIT(2) 958*4882a593Smuzhiyun #define DA9062AA_WATCHDOG_SD_SHIFT 3 959*4882a593Smuzhiyun #define DA9062AA_WATCHDOG_SD_MASK BIT(3) 960*4882a593Smuzhiyun #define DA9062AA_KEY_SD_MODE_SHIFT 4 961*4882a593Smuzhiyun #define DA9062AA_KEY_SD_MODE_MASK BIT(4) 962*4882a593Smuzhiyun #define DA9062AA_HOST_SD_MODE_SHIFT 5 963*4882a593Smuzhiyun #define DA9062AA_HOST_SD_MODE_MASK BIT(5) 964*4882a593Smuzhiyun #define DA9062AA_INT_SD_MODE_SHIFT 6 965*4882a593Smuzhiyun #define DA9062AA_INT_SD_MODE_MASK BIT(6) 966*4882a593Smuzhiyun #define DA9062AA_LDO_SD_SHIFT 7 967*4882a593Smuzhiyun #define DA9062AA_LDO_SD_MASK BIT(7) 968*4882a593Smuzhiyun 969*4882a593Smuzhiyun /* DA9062AA_CONFIG_J = 0x10F */ 970*4882a593Smuzhiyun #define DA9062AA_KEY_DELAY_SHIFT 0 971*4882a593Smuzhiyun #define DA9062AA_KEY_DELAY_MASK 0x03 972*4882a593Smuzhiyun #define DA9062AA_SHUT_DELAY_SHIFT 2 973*4882a593Smuzhiyun #define DA9062AA_SHUT_DELAY_MASK (0x03 << 2) 974*4882a593Smuzhiyun #define DA9062AA_RESET_DURATION_SHIFT 4 975*4882a593Smuzhiyun #define DA9062AA_RESET_DURATION_MASK (0x03 << 4) 976*4882a593Smuzhiyun #define DA9062AA_TWOWIRE_TO_SHIFT 6 977*4882a593Smuzhiyun #define DA9062AA_TWOWIRE_TO_MASK BIT(6) 978*4882a593Smuzhiyun #define DA9062AA_IF_RESET_SHIFT 7 979*4882a593Smuzhiyun #define DA9062AA_IF_RESET_MASK BIT(7) 980*4882a593Smuzhiyun 981*4882a593Smuzhiyun /* DA9062AA_CONFIG_K = 0x110 */ 982*4882a593Smuzhiyun #define DA9062AA_GPIO0_PUPD_SHIFT 0 983*4882a593Smuzhiyun #define DA9062AA_GPIO0_PUPD_MASK 0x01 984*4882a593Smuzhiyun #define DA9062AA_GPIO1_PUPD_SHIFT 1 985*4882a593Smuzhiyun #define DA9062AA_GPIO1_PUPD_MASK BIT(1) 986*4882a593Smuzhiyun #define DA9062AA_GPIO2_PUPD_SHIFT 2 987*4882a593Smuzhiyun #define DA9062AA_GPIO2_PUPD_MASK BIT(2) 988*4882a593Smuzhiyun #define DA9062AA_GPIO3_PUPD_SHIFT 3 989*4882a593Smuzhiyun #define DA9062AA_GPIO3_PUPD_MASK BIT(3) 990*4882a593Smuzhiyun #define DA9062AA_GPIO4_PUPD_SHIFT 4 991*4882a593Smuzhiyun #define DA9062AA_GPIO4_PUPD_MASK BIT(4) 992*4882a593Smuzhiyun 993*4882a593Smuzhiyun /* DA9062AA_CONFIG_M = 0x112 */ 994*4882a593Smuzhiyun #define DA9062AA_NSHUTDOWN_PU_SHIFT 1 995*4882a593Smuzhiyun #define DA9062AA_NSHUTDOWN_PU_MASK BIT(1) 996*4882a593Smuzhiyun #define DA9062AA_WDG_MODE_SHIFT 3 997*4882a593Smuzhiyun #define DA9062AA_WDG_MODE_MASK BIT(3) 998*4882a593Smuzhiyun #define DA9062AA_OSC_FRQ_SHIFT 4 999*4882a593Smuzhiyun #define DA9062AA_OSC_FRQ_MASK (0x0f << 4) 1000*4882a593Smuzhiyun 1001*4882a593Smuzhiyun /* DA9062AA_TRIM_CLDR = 0x120 */ 1002*4882a593Smuzhiyun #define DA9062AA_TRIM_CLDR_SHIFT 0 1003*4882a593Smuzhiyun #define DA9062AA_TRIM_CLDR_MASK 0xff 1004*4882a593Smuzhiyun 1005*4882a593Smuzhiyun /* DA9062AA_GP_ID_0 = 0x121 */ 1006*4882a593Smuzhiyun #define DA9062AA_GP_0_SHIFT 0 1007*4882a593Smuzhiyun #define DA9062AA_GP_0_MASK 0xff 1008*4882a593Smuzhiyun 1009*4882a593Smuzhiyun /* DA9062AA_GP_ID_1 = 0x122 */ 1010*4882a593Smuzhiyun #define DA9062AA_GP_1_SHIFT 0 1011*4882a593Smuzhiyun #define DA9062AA_GP_1_MASK 0xff 1012*4882a593Smuzhiyun 1013*4882a593Smuzhiyun /* DA9062AA_GP_ID_2 = 0x123 */ 1014*4882a593Smuzhiyun #define DA9062AA_GP_2_SHIFT 0 1015*4882a593Smuzhiyun #define DA9062AA_GP_2_MASK 0xff 1016*4882a593Smuzhiyun 1017*4882a593Smuzhiyun /* DA9062AA_GP_ID_3 = 0x124 */ 1018*4882a593Smuzhiyun #define DA9062AA_GP_3_SHIFT 0 1019*4882a593Smuzhiyun #define DA9062AA_GP_3_MASK 0xff 1020*4882a593Smuzhiyun 1021*4882a593Smuzhiyun /* DA9062AA_GP_ID_4 = 0x125 */ 1022*4882a593Smuzhiyun #define DA9062AA_GP_4_SHIFT 0 1023*4882a593Smuzhiyun #define DA9062AA_GP_4_MASK 0xff 1024*4882a593Smuzhiyun 1025*4882a593Smuzhiyun /* DA9062AA_GP_ID_5 = 0x126 */ 1026*4882a593Smuzhiyun #define DA9062AA_GP_5_SHIFT 0 1027*4882a593Smuzhiyun #define DA9062AA_GP_5_MASK 0xff 1028*4882a593Smuzhiyun 1029*4882a593Smuzhiyun /* DA9062AA_GP_ID_6 = 0x127 */ 1030*4882a593Smuzhiyun #define DA9062AA_GP_6_SHIFT 0 1031*4882a593Smuzhiyun #define DA9062AA_GP_6_MASK 0xff 1032*4882a593Smuzhiyun 1033*4882a593Smuzhiyun /* DA9062AA_GP_ID_7 = 0x128 */ 1034*4882a593Smuzhiyun #define DA9062AA_GP_7_SHIFT 0 1035*4882a593Smuzhiyun #define DA9062AA_GP_7_MASK 0xff 1036*4882a593Smuzhiyun 1037*4882a593Smuzhiyun /* DA9062AA_GP_ID_8 = 0x129 */ 1038*4882a593Smuzhiyun #define DA9062AA_GP_8_SHIFT 0 1039*4882a593Smuzhiyun #define DA9062AA_GP_8_MASK 0xff 1040*4882a593Smuzhiyun 1041*4882a593Smuzhiyun /* DA9062AA_GP_ID_9 = 0x12A */ 1042*4882a593Smuzhiyun #define DA9062AA_GP_9_SHIFT 0 1043*4882a593Smuzhiyun #define DA9062AA_GP_9_MASK 0xff 1044*4882a593Smuzhiyun 1045*4882a593Smuzhiyun /* DA9062AA_GP_ID_10 = 0x12B */ 1046*4882a593Smuzhiyun #define DA9062AA_GP_10_SHIFT 0 1047*4882a593Smuzhiyun #define DA9062AA_GP_10_MASK 0xff 1048*4882a593Smuzhiyun 1049*4882a593Smuzhiyun /* DA9062AA_GP_ID_11 = 0x12C */ 1050*4882a593Smuzhiyun #define DA9062AA_GP_11_SHIFT 0 1051*4882a593Smuzhiyun #define DA9062AA_GP_11_MASK 0xff 1052*4882a593Smuzhiyun 1053*4882a593Smuzhiyun /* DA9062AA_GP_ID_12 = 0x12D */ 1054*4882a593Smuzhiyun #define DA9062AA_GP_12_SHIFT 0 1055*4882a593Smuzhiyun #define DA9062AA_GP_12_MASK 0xff 1056*4882a593Smuzhiyun 1057*4882a593Smuzhiyun /* DA9062AA_GP_ID_13 = 0x12E */ 1058*4882a593Smuzhiyun #define DA9062AA_GP_13_SHIFT 0 1059*4882a593Smuzhiyun #define DA9062AA_GP_13_MASK 0xff 1060*4882a593Smuzhiyun 1061*4882a593Smuzhiyun /* DA9062AA_GP_ID_14 = 0x12F */ 1062*4882a593Smuzhiyun #define DA9062AA_GP_14_SHIFT 0 1063*4882a593Smuzhiyun #define DA9062AA_GP_14_MASK 0xff 1064*4882a593Smuzhiyun 1065*4882a593Smuzhiyun /* DA9062AA_GP_ID_15 = 0x130 */ 1066*4882a593Smuzhiyun #define DA9062AA_GP_15_SHIFT 0 1067*4882a593Smuzhiyun #define DA9062AA_GP_15_MASK 0xff 1068*4882a593Smuzhiyun 1069*4882a593Smuzhiyun /* DA9062AA_GP_ID_16 = 0x131 */ 1070*4882a593Smuzhiyun #define DA9062AA_GP_16_SHIFT 0 1071*4882a593Smuzhiyun #define DA9062AA_GP_16_MASK 0xff 1072*4882a593Smuzhiyun 1073*4882a593Smuzhiyun /* DA9062AA_GP_ID_17 = 0x132 */ 1074*4882a593Smuzhiyun #define DA9062AA_GP_17_SHIFT 0 1075*4882a593Smuzhiyun #define DA9062AA_GP_17_MASK 0xff 1076*4882a593Smuzhiyun 1077*4882a593Smuzhiyun /* DA9062AA_GP_ID_18 = 0x133 */ 1078*4882a593Smuzhiyun #define DA9062AA_GP_18_SHIFT 0 1079*4882a593Smuzhiyun #define DA9062AA_GP_18_MASK 0xff 1080*4882a593Smuzhiyun 1081*4882a593Smuzhiyun /* DA9062AA_GP_ID_19 = 0x134 */ 1082*4882a593Smuzhiyun #define DA9062AA_GP_19_SHIFT 0 1083*4882a593Smuzhiyun #define DA9062AA_GP_19_MASK 0xff 1084*4882a593Smuzhiyun 1085*4882a593Smuzhiyun /* DA9062AA_DEVICE_ID = 0x181 */ 1086*4882a593Smuzhiyun #define DA9062AA_DEV_ID_SHIFT 0 1087*4882a593Smuzhiyun #define DA9062AA_DEV_ID_MASK 0xff 1088*4882a593Smuzhiyun 1089*4882a593Smuzhiyun /* DA9062AA_VARIANT_ID = 0x182 */ 1090*4882a593Smuzhiyun #define DA9062AA_VRC_SHIFT 0 1091*4882a593Smuzhiyun #define DA9062AA_VRC_MASK 0x0f 1092*4882a593Smuzhiyun #define DA9062AA_MRC_SHIFT 4 1093*4882a593Smuzhiyun #define DA9062AA_MRC_MASK (0x0f << 4) 1094*4882a593Smuzhiyun 1095*4882a593Smuzhiyun /* DA9062AA_CUSTOMER_ID = 0x183 */ 1096*4882a593Smuzhiyun #define DA9062AA_CUST_ID_SHIFT 0 1097*4882a593Smuzhiyun #define DA9062AA_CUST_ID_MASK 0xff 1098*4882a593Smuzhiyun 1099*4882a593Smuzhiyun /* DA9062AA_CONFIG_ID = 0x184 */ 1100*4882a593Smuzhiyun #define DA9062AA_CONFIG_REV_SHIFT 0 1101*4882a593Smuzhiyun #define DA9062AA_CONFIG_REV_MASK 0xff 1102*4882a593Smuzhiyun 1103*4882a593Smuzhiyun #endif /* __DA9062_H__ */ 1104