soc/codecs/rk_dsm.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Rockchip Audio Delta-sigma Digital Converter driver
55 #define DSM_DACDIGEN_DACEN_L0R1_MASK		BIT(0)
56 #define DSM_DACDIGEN_DACEN_L0R1_EN		BIT(0)
58 #define DSM_DACDIGEN_DAC_GLBEN_MASK		BIT(4)
59 #define DSM_DACDIGEN_DAC_GLBEN_EN		BIT(4)
62 #define DSM_DACCLKCTRL_DAC_MODE_ATTENU_MASK	BIT(0)
63 #define DSM_DACCLKCTRL_DAC_MODE_ATTENU_EN	BIT(0)
65 #define DSM_DACCLKCTRL_DAC_SYNC_STATUS_MASK	BIT(1)
67 #define DSM_DACCLKCTRL_DAC_SYNC_ENA_MASK	BIT(2)
68 #define DSM_DACCLKCTRL_DAC_SYNC_ENA_EN		BIT(2)
70 #define DSM_DACCLKCTRL_CKE_BCLKRX_MASK		BIT(3)
71 #define DSM_DACCLKCTRL_CKE_BCLKRX_EN		BIT(3)
73 #define DSM_DACCLKCTRL_I2SRX_CKE_MASK		BIT(4)
74 #define DSM_DACCLKCTRL_I2SRX_CKE_EN		BIT(4)
76 #define DSM_DACCLKCTRL_DAC_CKE_MASK		BIT(5)
77 #define DSM_DACCLKCTRL_DAC_CKE_EN		BIT(5)
81 #define DSM_DACINT_DIV_INT_DIV_CON(x)		((x) - 1)
84 #define DSM_DACSCLKRXINT_DIV_SCKRXDIV(x)	((x) - 1)
87 #define DSM_DACPWM_DIV_AUDIO_PWM_DIV(x)		((x) - 1)
91 #define DSM_DACPWM_CTRL_PWM_EN_MASK		BIT(3)
92 #define DSM_DACPWM_CTRL_PWM_EN			BIT(3)
94 #define DSM_DACPWM_CTRL_PWM_MODE_MASK		GENMASK(5, 4)
95 #define DSM_DACPWM_CTRL_PWM_MODE_1		(0x2 << 4)
96 #define DSM_DACPWM_CTRL_PWM_MODE_0		(0x1 << 4)
97 #define DSM_DACPWM_CTRL_PWM_MODE_DAC		(0x0 << 4)
98 #define DSM_DACPWM_CTRL_PWM_MODE_CKE_MASK	BIT(6)
99 #define DSM_DACPWM_CTRL_PWM_MODE_CKE_EN		BIT(6)
102 #define DSM_DACCFG1_DACSRT_MASK			GENMASK(4, 2)
105 #define DSM_DACMUTE_DACMT_MASK			BIT(0)
106 #define DSM_DACMUTE_DACUNMT_MASK		BIT(1)
114 #define DSM_DACVOGP_VOLGPL0_MASK		BIT(0)
115 #define DSM_DACVOGP_VOLGPL0_POS			BIT(0)
117 #define DSM_DACVOGP_VOLGPR0_MASK		BIT(1)
118 #define DSM_DACVOGP_VOLGPR0_POS			BIT(1)
131 #define DSM_DACHPF_HPFEN_L0R0_MASK		BIT(0)
132 #define DSM_DACHPF_HPFEN_L0R0_EN		BIT(0)
133 #define DSM_DACHPF_HPFCF_MASK			GENMASK(5, 4)
134 #define DSM_DACHPF_HPFCF_140HZ			(0x3 << 4)
135 #define DSM_DACHPF_HPFCF_120HZ			(0x2 << 4)
136 #define DSM_DACHPF_HPFCF_100HZ			(0x1 << 4)
137 #define DSM_DACHPF_HPFCF_80HZ			(0x0 << 4)
139 #define DSM_I2S_RXCR0_VDW_MASK			GENMASK(4, 0)
140 #define DSM_I2S_RXCR0_VDW(x)			((x) - 1)
142 #define DSM_I2S_RXCR1_CEX_MASK			BIT(4)
143 #define DSM_I2S_RXCR1_CEX_EXCHANGE		BIT(4)
152 #define DSM_I2S_CKR1_RLP_MASK			BIT(1)
153 #define DSM_I2S_CKR1_RLP_INVERTED		BIT(1)
155 #define DSM_I2S_CKR1_CKP_MASK			BIT(2)
156 #define DSM_I2S_CKR1_CKP_INVERTED		BIT(2)
158 #define DSM_I2S_CKR1_MSS_MASK			BIT(3)
161 #define DSM_I2S_XFER_RXS_MASK			BIT(1)
162 #define DSM_I2S_XFER_RXS_START			BIT(1)
165 #define DSM_I2S_CLR_RXC_MASK			BIT(1)
166 #define DSM_I2S_CLR_RXC_CLR			BIT(1)