1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * rk3228_codec.h -- rk3228 ALSA Soc Audio driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 7*4882a593Smuzhiyun * under the terms and conditions of the GNU General Public License, 8*4882a593Smuzhiyun * version 2, as published by the Free Software Foundation. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This program is distributed in the hope it will be useful, but WITHOUT 11*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13*4882a593Smuzhiyun * more details. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License 16*4882a593Smuzhiyun * along with this program. If not, see <http://www.gnu.org/licenses/>. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #ifndef _RK3228_CODEC_H 21*4882a593Smuzhiyun #define _RK3228_CODEC_H 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* codec register */ 24*4882a593Smuzhiyun #define CODEC_RESET (0x00 << 2) 25*4882a593Smuzhiyun #define DAC_INIT_CTRL1 (0x03 << 2) 26*4882a593Smuzhiyun #define DAC_INIT_CTRL2 (0x04 << 2) 27*4882a593Smuzhiyun #define DAC_INIT_CTRL3 (0x05 << 2) 28*4882a593Smuzhiyun #define DAC_PRECHARGE_CTRL (0x22 << 2) 29*4882a593Smuzhiyun #define DAC_PWR_CTRL (0x23 << 2) 30*4882a593Smuzhiyun #define DAC_CLK_CTRL (0x24 << 2) 31*4882a593Smuzhiyun #define HPMIX_CTRL (0x25 << 2) 32*4882a593Smuzhiyun #define DAC_SELECT (0x26 << 2) 33*4882a593Smuzhiyun #define HPOUT_CTRL (0x27 << 2) 34*4882a593Smuzhiyun #define HPOUTL_GAIN_CTRL (0x28 << 2) 35*4882a593Smuzhiyun #define HPOUTR_GAIN_CTRL (0x29 << 2) 36*4882a593Smuzhiyun #define HPOUT_POP_CTRL (0x2a << 2) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* REG00: CODEC_RESET */ 39*4882a593Smuzhiyun #define PWR_RST_BYPASS_DIS BIT(6) 40*4882a593Smuzhiyun #define PWR_RST_BYPASS_EN BIT(6) 41*4882a593Smuzhiyun #define DIG_CORE_RST (0 << 1) 42*4882a593Smuzhiyun #define DIG_CORE_WORK BIT(1) 43*4882a593Smuzhiyun #define SYS_RST (0) 44*4882a593Smuzhiyun #define SYS_WORK BIT(0) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* REG03: DAC_INIT_CTRL1 */ 47*4882a593Smuzhiyun #define PIN_DIRECTION_MASK BIT(5) 48*4882a593Smuzhiyun #define PIN_DIRECTION_IN (0 << 5) 49*4882a593Smuzhiyun #define PIN_DIRECTION_OUT BIT(5) 50*4882a593Smuzhiyun #define DAC_I2S_MODE_MASK BIT(4) 51*4882a593Smuzhiyun #define DAC_I2S_MODE_SLAVE (0 << 4) 52*4882a593Smuzhiyun #define DAC_I2S_MODE_MASTER BIT(4) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* REG04: DAC_INIT_CTRL2 */ 55*4882a593Smuzhiyun #define DAC_I2S_LRP_MASK BIT(7) 56*4882a593Smuzhiyun #define DAC_I2S_LRP_NORMAL (0 << 7) 57*4882a593Smuzhiyun #define DAC_I2S_LRP_REVERSAL BIT(7) 58*4882a593Smuzhiyun #define DAC_VDL_MASK (3 << 5) 59*4882a593Smuzhiyun #define DAC_VDL_16BITS (0 << 5) 60*4882a593Smuzhiyun #define DAC_VDL_20BITS BIT(5) 61*4882a593Smuzhiyun #define DAC_VDL_24BITS (2 << 5) 62*4882a593Smuzhiyun #define DAC_VDL_32BITS (3 << 5) 63*4882a593Smuzhiyun #define DAC_MODE_MASK (3 << 3) 64*4882a593Smuzhiyun #define DAC_MODE_RJM (0 << 3) 65*4882a593Smuzhiyun #define DAC_MODE_LJM BIT(3) 66*4882a593Smuzhiyun #define DAC_MODE_I2S (2 << 3) 67*4882a593Smuzhiyun #define DAC_MODE_PCM (3 << 3) 68*4882a593Smuzhiyun #define DAC_LR_SWAP_MASK BIT(2) 69*4882a593Smuzhiyun #define DAC_LR_SWAP_DIS (0 << 2) 70*4882a593Smuzhiyun #define DAC_LR_SWAP_EN BIT(2) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* REG05: DAC_INIT_CTRL3 */ 73*4882a593Smuzhiyun #define DAC_WL_MASK (3 << 2) 74*4882a593Smuzhiyun #define DAC_WL_16BITS (0 << 2) 75*4882a593Smuzhiyun #define DAC_WL_20BITS BIT(2) 76*4882a593Smuzhiyun #define DAC_WL_24BITS (2 << 2) 77*4882a593Smuzhiyun #define DAC_WL_32BITS (3 << 2) 78*4882a593Smuzhiyun #define DAC_RST_MASK BIT(1) 79*4882a593Smuzhiyun #define DAC_RST_EN (0 << 1) 80*4882a593Smuzhiyun #define DAC_RST_DIS BIT(1) 81*4882a593Smuzhiyun #define DAC_BCP_MASK BIT(0) 82*4882a593Smuzhiyun #define DAC_BCP_NORMAL (0 << 0) 83*4882a593Smuzhiyun #define DAC_BCP_REVERSAL BIT(0) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* REG22: DAC_PRECHARGE_CTRL */ 86*4882a593Smuzhiyun #define DAC_CHARGE_PRECHARGE BIT(7) 87*4882a593Smuzhiyun #define DAC_CHARGE_DISCHARGE (0 << 7) 88*4882a593Smuzhiyun #define DAC_CHARGE_XCHARGE_MASK BIT(7) 89*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_64I BIT(6) 90*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_64I_MASK BIT(6) 91*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_32I BIT(5) 92*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_32I_MASK BIT(5) 93*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_16I BIT(4) 94*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_16I_MASK BIT(4) 95*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_08I BIT(3) 96*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_08I_MASK BIT(3) 97*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_04I BIT(2) 98*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_04I_MASK BIT(2) 99*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_02I BIT(1) 100*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_02I_MASK BIT(1) 101*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_I BIT(0) 102*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_I_MASK BIT(0) 103*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_ALL_MASK (0x7f) 104*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_ALL_OFF (0x0) 105*4882a593Smuzhiyun #define DAC_CHARGE_CURRENT_ALL_ON (0x7f) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* REG23: DAC_PWR_CTRL */ 108*4882a593Smuzhiyun #define DAC_PWR_OFF (0 << 6) 109*4882a593Smuzhiyun #define DAC_PWR_ON BIT(6) 110*4882a593Smuzhiyun #define DAC_PWR_MASK BIT(6) 111*4882a593Smuzhiyun #define DACL_PATH_REFV_OFF (0 << 5) 112*4882a593Smuzhiyun #define DACL_PATH_REFV_ON BIT(5) 113*4882a593Smuzhiyun #define DACL_PATH_REFV_MASK BIT(5) 114*4882a593Smuzhiyun #define HPOUTL_ZERO_CROSSING_OFF (0 << 4) 115*4882a593Smuzhiyun #define HPOUTL_ZERO_CROSSING_ON BIT(4) 116*4882a593Smuzhiyun #define DACR_PATH_REFV_OFF (0 << 1) 117*4882a593Smuzhiyun #define DACR_PATH_REFV_ON BIT(1) 118*4882a593Smuzhiyun #define DACR_PATH_REFV_MASK BIT(1) 119*4882a593Smuzhiyun #define HPOUTR_ZERO_CROSSING_OFF (0 << 0) 120*4882a593Smuzhiyun #define HPOUTR_ZERO_CROSSING_ON BIT(0) 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* REG24: DAC_CLK_CTRL */ 123*4882a593Smuzhiyun #define DACL_REFV_OFF (0 << 7) 124*4882a593Smuzhiyun #define DACL_REFV_ON BIT(7) 125*4882a593Smuzhiyun #define DACL_REFV_MASK BIT(7) 126*4882a593Smuzhiyun #define DACL_CLK_OFF (0 << 6) 127*4882a593Smuzhiyun #define DACL_CLK_ON BIT(6) 128*4882a593Smuzhiyun #define DACL_CLK_MASK BIT(6) 129*4882a593Smuzhiyun #define DACL_OFF (0 << 5) 130*4882a593Smuzhiyun #define DACL_ON BIT(5) 131*4882a593Smuzhiyun #define DACL_MASK BIT(5) 132*4882a593Smuzhiyun #define DACL_INIT_OFF (0 << 4) 133*4882a593Smuzhiyun #define DACL_INIT_ON BIT(4) 134*4882a593Smuzhiyun #define DACL_INIT_MASK BIT(4) 135*4882a593Smuzhiyun #define DACR_REFV_OFF (0 << 3) 136*4882a593Smuzhiyun #define DACR_REFV_ON BIT(3) 137*4882a593Smuzhiyun #define DACR_REFV_MASK BIT(3) 138*4882a593Smuzhiyun #define DACR_CLK_OFF (0 << 2) 139*4882a593Smuzhiyun #define DACR_CLK_ON BIT(2) 140*4882a593Smuzhiyun #define DACR_CLK_MASK BIT(2) 141*4882a593Smuzhiyun #define DACR_OFF (0 << 1) 142*4882a593Smuzhiyun #define DACR_ON BIT(1) 143*4882a593Smuzhiyun #define DACR_MASK BIT(1) 144*4882a593Smuzhiyun #define DACR_INIT_OFF (0 << 0) 145*4882a593Smuzhiyun #define DACR_INIT_ON BIT(0) 146*4882a593Smuzhiyun #define DACR_INIT_MASK BIT(0) 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* REG25: HPMIX_CTRL*/ 149*4882a593Smuzhiyun #define HPMIXL_DIS (0 << 6) 150*4882a593Smuzhiyun #define HPMIXL_EN BIT(6) 151*4882a593Smuzhiyun #define HPMIXL_MASK BIT(6) 152*4882a593Smuzhiyun #define HPMIXL_INIT_DIS (0 << 5) 153*4882a593Smuzhiyun #define HPMIXL_INIT_EN BIT(5) 154*4882a593Smuzhiyun #define HPMIXL_INIT_MASK BIT(5) 155*4882a593Smuzhiyun #define HPMIXL_INIT2_DIS (0 << 4) 156*4882a593Smuzhiyun #define HPMIXL_INIT2_EN BIT(4) 157*4882a593Smuzhiyun #define HPMIXL_INIT2_MASK BIT(4) 158*4882a593Smuzhiyun #define HPMIXR_DIS (0 << 2) 159*4882a593Smuzhiyun #define HPMIXR_EN BIT(2) 160*4882a593Smuzhiyun #define HPMIXR_MASK BIT(2) 161*4882a593Smuzhiyun #define HPMIXR_INIT_DIS (0 << 1) 162*4882a593Smuzhiyun #define HPMIXR_INIT_EN BIT(1) 163*4882a593Smuzhiyun #define HPMIXR_INIT_MASK BIT(1) 164*4882a593Smuzhiyun #define HPMIXR_INIT2_DIS (0 << 0) 165*4882a593Smuzhiyun #define HPMIXR_INIT2_EN BIT(0) 166*4882a593Smuzhiyun #define HPMIXR_INIT2_MASK BIT(0) 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* REG26: DAC_SELECT */ 169*4882a593Smuzhiyun #define DACL_SELECT BIT(4) 170*4882a593Smuzhiyun #define DACL_SELECT_MASK BIT(4) 171*4882a593Smuzhiyun #define DACL_DESELECT (0 << 4) 172*4882a593Smuzhiyun #define DACR_SELECT BIT(0) 173*4882a593Smuzhiyun #define DACR_SELECT_MASK BIT(0) 174*4882a593Smuzhiyun #define DACR_DESELECT (0 << 0) 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* REG27: HPOUT_CTRL */ 177*4882a593Smuzhiyun #define HPOUTL_DIS (0 << 7) 178*4882a593Smuzhiyun #define HPOUTL_EN BIT(7) 179*4882a593Smuzhiyun #define HPOUTL_MASK BIT(7) 180*4882a593Smuzhiyun #define HPOUTL_INIT_DIS (0 << 6) 181*4882a593Smuzhiyun #define HPOUTL_INIT_EN BIT(6) 182*4882a593Smuzhiyun #define HPOUTL_INIT_MASK BIT(6) 183*4882a593Smuzhiyun #define HPOUTL_MUTE (0 << 5) 184*4882a593Smuzhiyun #define HPOUTL_UNMUTE BIT(5) 185*4882a593Smuzhiyun #define HPOUTL_MUTE_MASK BIT(5) 186*4882a593Smuzhiyun #define HPOUTR_DIS (0 << 4) 187*4882a593Smuzhiyun #define HPOUTR_EN BIT(4) 188*4882a593Smuzhiyun #define HPOUTR_MASK BIT(4) 189*4882a593Smuzhiyun #define HPOUTR_INIT_DIS (0 << 3) 190*4882a593Smuzhiyun #define HPOUTR_INIT_EN BIT(3) 191*4882a593Smuzhiyun #define HPOUTR_INIT_MASK BIT(3) 192*4882a593Smuzhiyun #define HPOUTR_MUTE (0 << 2) 193*4882a593Smuzhiyun #define HPOUTR_UNMUTE BIT(2) 194*4882a593Smuzhiyun #define HPOUTR_MUTE_MASK BIT(2) 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun /* REG28: HPOUTL_GAIN_CTRL */ 197*4882a593Smuzhiyun #define HPOUTL_GAIN_MASK (0X1f << 0) 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* REG29: HPOUTR_GAIN_CTRL */ 200*4882a593Smuzhiyun #define HPOUTR_GAIN_MASK (0X1f << 0) 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* REG2a: HPOUT_POP_CTRL */ 203*4882a593Smuzhiyun #define HPOUTR_POP_XCHARGE BIT(4) 204*4882a593Smuzhiyun #define HPOUTR_POP_WORK (2 << 4) 205*4882a593Smuzhiyun #define HPOUTR_POP_MASK (3 << 4) 206*4882a593Smuzhiyun #define HPOUTL_POP_XCHARGE BIT(0) 207*4882a593Smuzhiyun #define HPOUTL_POP_WORK (2 << 0) 208*4882a593Smuzhiyun #define HPOUTL_POP_MASK (3 << 0) 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun #define RK3228_HIFI (0) 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun struct rk3228_reg_msk_val { 213*4882a593Smuzhiyun unsigned int reg; 214*4882a593Smuzhiyun unsigned int msk; 215*4882a593Smuzhiyun unsigned int val; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun #endif 219