Lines Matching +full:4 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/platform_data/dma-imx.h>
17 #define REG_EASRC_WRFIFO(ctx) (0x000 + 4 * (ctx))
19 #define REG_EASRC_RDFIFO(ctx) (0x010 + 4 * (ctx))
21 #define REG_EASRC_CC(ctx) (0x020 + 4 * (ctx))
23 #define REG_EASRC_CCE1(ctx) (0x030 + 4 * (ctx))
25 #define REG_EASRC_CCE2(ctx) (0x040 + 4 * (ctx))
27 #define REG_EASRC_CIA(ctx) (0x050 + 4 * (ctx))
29 #define REG_EASRC_DPCS0R0(ctx) (0x060 + 4 * (ctx))
30 #define REG_EASRC_DPCS0R1(ctx) (0x070 + 4 * (ctx))
31 #define REG_EASRC_DPCS0R2(ctx) (0x080 + 4 * (ctx))
32 #define REG_EASRC_DPCS0R3(ctx) (0x090 + 4 * (ctx))
34 #define REG_EASRC_DPCS1R0(ctx) (0x0A0 + 4 * (ctx))
35 #define REG_EASRC_DPCS1R1(ctx) (0x0B0 + 4 * (ctx))
36 #define REG_EASRC_DPCS1R2(ctx) (0x0C0 + 4 * (ctx))
37 #define REG_EASRC_DPCS1R3(ctx) (0x0D0 + 4 * (ctx))
39 #define REG_EASRC_COC(ctx) (0x0E0 + 4 * (ctx))
41 #define REG_EASRC_COA(ctx) (0x0F0 + 4 * (ctx))
43 #define REG_EASRC_SFS(ctx) (0x100 + 4 * (ctx))
49 #define REG_EASRC_RUC(ctx) (0x130 + 4 * (ctx))
51 #define REG_EASRC_RUR(ctx) (0x140 + 4 * (ctx))
57 #define REG_EASRC_PCF(ctx) (0x160 + 4 * (ctx))
67 #define REG_EASRC_CS0(ctx) (0x180 + 4 * (ctx))
69 #define REG_EASRC_CS1(ctx) (0x190 + 4 * (ctx))
71 #define REG_EASRC_CS2(ctx) (0x1A0 + 4 * (ctx))
73 #define REG_EASRC_CS3(ctx) (0x1B0 + 4 * (ctx))
74 /* ASRC Channel Status 4 */
75 #define REG_EASRC_CS4(ctx) (0x1C0 + 4 * (ctx))
77 #define REG_EASRC_CS5(ctx) (0x1D0 + 4 * (ctx))
88 #define EASRC_CC_EN_MASK BIT(EASRC_CC_EN_SHIFT)
89 #define EASRC_CC_EN BIT(EASRC_CC_EN_SHIFT)
91 #define EASRC_CC_STOP_MASK BIT(EASRC_CC_STOP_SHIFT)
92 #define EASRC_CC_STOP BIT(EASRC_CC_STOP_SHIFT)
94 #define EASRC_CC_FWMDE_MASK BIT(EASRC_CC_FWMDE_SHIFT)
95 #define EASRC_CC_FWMDE BIT(EASRC_CC_FWMDE_SHIFT)
98 #define EASRC_CC_FIFO_WTMK_MASK ((BIT(EASRC_CC_FIFO_WTMK_WIDTH) - 1) \
104 #define EASRC_CC_SAMPLE_POS_MASK ((BIT(EASRC_CC_SAMPLE_POS_WIDTH) - 1) \
109 #define EASRC_CC_ENDIANNESS_MASK BIT(EASRC_CC_ENDIANNESS_SHIFT)
110 #define EASRC_CC_ENDIANNESS BIT(EASRC_CC_ENDIANNESS_SHIFT)
113 #define EASRC_CC_BPS_MASK ((BIT(EASRC_CC_BPS_WIDTH) - 1) \
118 #define EASRC_CC_FMT_MASK BIT(EASRC_CC_FMT_SHIFT)
119 #define EASRC_CC_FMT BIT(EASRC_CC_FMT_SHIFT)
121 #define EASRC_CC_INSIGN_MASK BIT(EASRC_CC_INSIGN_SHIFT)
122 #define EASRC_CC_INSIGN BIT(EASRC_CC_INSIGN_SHIFT)
125 #define EASRC_CC_CHEN_MASK ((BIT(EASRC_CC_CHEN_WIDTH) - 1) \
132 #define EASRC_CCE1_COEF_WS_MASK BIT(EASRC_CCE1_COEF_WS_SHIFT)
133 #define EASRC_CCE1_COEF_WS BIT(EASRC_CCE1_COEF_WS_SHIFT)
135 #define EASRC_CCE1_COEF_MEM_RST_MASK BIT(EASRC_CCE1_COEF_MEM_RST_SHIFT)
136 #define EASRC_CCE1_COEF_MEM_RST BIT(EASRC_CCE1_COEF_MEM_RST_SHIFT)
139 #define EASRC_CCE1_PF_EXP_MASK ((BIT(EASRC_CCE1_PF_EXP_WIDTH) - 1) \
144 #define EASRC_CCE1_PF_ST1_WBFP_MASK BIT(EASRC_CCE1_PF_ST1_WBFP_SHIFT)
145 #define EASRC_CCE1_PF_ST1_WBFP BIT(EASRC_CCE1_PF_ST1_WBFP_SHIFT)
147 #define EASRC_CCE1_PF_TSEN_MASK BIT(EASRC_CCE1_PF_TSEN_SHIFT)
148 #define EASRC_CCE1_PF_TSEN BIT(EASRC_CCE1_PF_TSEN_SHIFT)
150 #define EASRC_CCE1_RS_BYPASS_MASK BIT(EASRC_CCE1_RS_BYPASS_SHIFT)
151 #define EASRC_CCE1_RS_BYPASS BIT(EASRC_CCE1_RS_BYPASS_SHIFT)
153 #define EASRC_CCE1_PF_BYPASS_MASK BIT(EASRC_CCE1_PF_BYPASS_SHIFT)
154 #define EASRC_CCE1_PF_BYPASS BIT(EASRC_CCE1_PF_BYPASS_SHIFT)
156 #define EASRC_CCE1_RS_STOP_MASK BIT(EASRC_CCE1_RS_STOP_SHIFT)
157 #define EASRC_CCE1_RS_STOP BIT(EASRC_CCE1_RS_STOP_SHIFT)
158 #define EASRC_CCE1_PF_STOP_SHIFT 4
159 #define EASRC_CCE1_PF_STOP_MASK BIT(EASRC_CCE1_PF_STOP_SHIFT)
160 #define EASRC_CCE1_PF_STOP BIT(EASRC_CCE1_PF_STOP_SHIFT)
163 #define EASRC_CCE1_RS_INIT_MASK ((BIT(EASRC_CCE1_RS_INIT_WIDTH) - 1) \
169 #define EASRC_CCE1_PF_INIT_MASK ((BIT(EASRC_CCE1_PF_INIT_WIDTH) - 1) \
177 #define EASRC_CCE2_ST2_TAPS_MASK ((BIT(EASRC_CCE2_ST2_TAPS_WIDTH) - 1) \
183 #define EASRC_CCE2_ST1_TAPS_MASK ((BIT(EASRC_CCE2_ST1_TAPS_WIDTH) - 1) \
191 #define EASRC_CIA_ITER_MASK ((BIT(EASRC_CIA_ITER_WIDTH) - 1) \
197 #define EASRC_CIA_GRLEN_MASK ((BIT(EASRC_CIA_GRLEN_WIDTH) - 1) \
203 #define EASRC_CIA_ACCLEN_MASK ((BIT(EASRC_CIA_ACCLEN_WIDTH) - 1) \
211 #define EASRC_DPCS0R0_MAXCH_MASK ((BIT(EASRC_DPCS0R0_MAXCH_WIDTH) - 1) \
217 #define EASRC_DPCS0R0_MINCH_MASK ((BIT(EASRC_DPCS0R0_MINCH_WIDTH) - 1) \
223 #define EASRC_DPCS0R0_NUMCH_MASK ((BIT(EASRC_DPCS0R0_NUMCH_WIDTH) - 1) \
229 #define EASRC_DPCS0R0_CTXNUM_MASK ((BIT(EASRC_DPCS0R0_CTXNUM_WIDTH) - 1) \
234 #define EASRC_DPCS0R0_EN_MASK BIT(EASRC_DPCS0R0_EN_SHIFT)
235 #define EASRC_DPCS0R0_EN BIT(EASRC_DPCS0R0_EN_SHIFT)
240 #define EASRC_DPCS0R1_ST1_EXP_MASK ((BIT(EASRC_DPCS0R1_ST1_EXP_WIDTH) - 1) \
248 #define EASRC_DPCS0R2_ST1_MA_MASK ((BIT(EASRC_DPCS0R2_ST1_MA_WIDTH) - 1) \
254 #define EASRC_DPCS0R2_ST1_SA_MASK ((BIT(EASRC_DPCS0R2_ST1_SA_WIDTH) - 1) \
262 #define EASRC_DPCS0R3_ST2_MA_MASK ((BIT(EASRC_DPCS0R3_ST2_MA_WIDTH) - 1) \
268 #define EASRC_DPCS0R3_ST2_SA_MASK ((BIT(EASRC_DPCS0R3_ST2_SA_WIDTH) - 1) \
275 #define EASRC_COC_FWMDE_MASK BIT(EASRC_COC_FWMDE_SHIFT)
276 #define EASRC_COC_FWMDE BIT(EASRC_COC_FWMDE_SHIFT)
279 #define EASRC_COC_FIFO_WTMK_MASK ((BIT(EASRC_COC_FIFO_WTMK_WIDTH) - 1) \
285 #define EASRC_COC_SAMPLE_POS_MASK ((BIT(EASRC_COC_SAMPLE_POS_WIDTH) - 1) \
290 #define EASRC_COC_ENDIANNESS_MASK BIT(EASRC_COC_ENDIANNESS_SHIFT)
291 #define EASRC_COC_ENDIANNESS BIT(EASRC_COC_ENDIANNESS_SHIFT)
294 #define EASRC_COC_BPS_MASK ((BIT(EASRC_COC_BPS_WIDTH) - 1) \
299 #define EASRC_COC_FMT_MASK BIT(EASRC_COC_FMT_SHIFT)
300 #define EASRC_COC_FMT BIT(EASRC_COC_FMT_SHIFT)
302 #define EASRC_COC_OUTSIGN_MASK BIT(EASRC_COC_OUTSIGN_SHIFT)
303 #define EASRC_COC_OUTSIGN_OUT BIT(EASRC_COC_OUTSIGN_SHIFT)
305 #define EASRC_COC_IEC_VDATA_MASK BIT(EASRC_COC_IEC_VDATA_SHIFT)
306 #define EASRC_COC_IEC_VDATA BIT(EASRC_COC_IEC_VDATA_SHIFT)
308 #define EASRC_COC_IEC_EN_MASK BIT(EASRC_COC_IEC_EN_SHIFT)
309 #define EASRC_COC_IEC_EN BIT(EASRC_COC_IEC_EN_SHIFT)
311 #define EASRC_COC_DITHER_EN_MASK BIT(EASRC_COC_DITHER_EN_SHIFT)
312 #define EASRC_COC_DITHER_EN BIT(EASRC_COC_DITHER_EN_SHIFT)
317 #define EASRC_COA_ITER_MASK ((BIT(EASRC_COA_ITER_WIDTH) - 1) \
323 #define EASRC_COA_GRLEN_MASK ((BIT(EASRC_COA_GRLEN_WIDTH) - 1) \
329 #define EASRC_COA_ACCLEN_MASK ((BIT(EASRC_COA_ACCLEN_WIDTH) - 1) \
336 #define EASRC_SFS_IWTMK_MASK BIT(EASRC_SFS_IWTMK_SHIFT)
337 #define EASRC_SFS_IWTMK BIT(EASRC_SFS_IWTMK_SHIFT)
340 #define EASRC_SFS_NSGI_MASK ((BIT(EASRC_SFS_NSGI_WIDTH) - 1) \
345 #define EASRC_SFS_OWTMK_MASK BIT(EASRC_SFS_OWTMK_SHIFT)
346 #define EASRC_SFS_OWTMK BIT(EASRC_SFS_OWTMK_SHIFT)
349 #define EASRC_SFS_NSGO_MASK ((BIT(EASRC_SFS_NSGO_WIDTH) - 1) \
361 #define EASRC_RRH_RS_VLD_MASK BIT(EASRC_RRH_RS_VLD_SHIFT)
362 #define EASRC_RRH_RS_VLD BIT(EASRC_RRH_RS_VLD_SHIFT)
365 #define EASRC_RRH_RS_RH_MASK ((BIT(EASRC_RRH_RS_RH_WIDTH) - 1) \
378 #define EASRC_RRUR_RRR_MASK ((BIT(EASRC_RRUR_RRR_WIDTH) - 1) \
406 #define EASRC_CRCC_RS_CA_MASK ((BIT(EASRC_CRCC_RS_CA_WIDTH) - 1) \
412 #define EASRC_CRCC_RS_TAPS_MASK ((BIT(EASRC_CRCC_RS_TAPS_WIDTH) - 1) \
417 #define EASRC_CRCC_RS_CPR_MASK BIT(EASRC_CRCC_RS_CPR_SHIFT)
418 #define EASRC_CRCC_RS_CPR BIT(EASRC_CRCC_RS_CPR_SHIFT)
422 #define EASRC_IRQC_RSDM_WIDTH 4
423 #define EASRC_IRQC_RSDM_MASK ((BIT(EASRC_IRQC_RSDM_WIDTH) - 1) \
427 #define EASRC_IRQC_OERM_SHIFT 4
428 #define EASRC_IRQC_OERM_WIDTH 4
429 #define EASRC_IRQC_OERM_MASK ((BIT(EASRC_IRQC_OERM_WIDTH) - 1) \
434 #define EASRC_IRQC_IOM_WIDTH 4
435 #define EASRC_IRQC_IOM_MASK ((BIT(EASRC_IRQC_IOM_WIDTH) - 1) \
442 #define EASRC_IRQF_RSD_WIDTH 4
443 #define EASRC_IRQF_RSD_MASK ((BIT(EASRC_IRQF_RSD_WIDTH) - 1) \
447 #define EASRC_IRQF_OER_SHIFT 4
448 #define EASRC_IRQF_OER_WIDTH 4
449 #define EASRC_IRQF_OER_MASK ((BIT(EASRC_IRQF_OER_WIDTH) - 1) \
454 #define EASRC_IRQF_IFO_WIDTH 4
455 #define EASRC_IRQF_IFO_MASK ((BIT(EASRC_IRQF_IFO_WIDTH) - 1) \
468 #define EASRC_DBGC_DMS_MASK ((BIT(EASRC_DBGC_DMS_WIDTH) - 1) \
479 #define EASRC_CTX_MAX_NUM 4