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/OK3568_Linux_fs/kernel/drivers/phy/marvell/
H A Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
19 /* Relative to priv->base */
36 #define MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY BIT(2)
84 #define MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN BIT(2)
107 /* Relative to priv->regmap */
110 #define MVEBU_COMPHY_CONF1_USB_PCIE BIT(2) /* 0: Ethernet/SATA */
128 * A lane is described by the following bitfields:
129 * [ 1- 0]: COMPHY polarity invertion
[all …]
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
9 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
13 #include <linux/arm-smccc.h>
23 #define MVEBU_A3700_COMPHY_PORTS 2
43 #define COMPHY_FW_SPEED_3_125G 2 /* SGMII 2.5G */
53 ((speed) << 2))
58 unsigned int lane; member
67 .lane = _lane, \
81 /* lane 0 */
88 /* lane 1 */
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
20 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
62 unsigned int lpd; /* RCW lane powerdown bit */
67 { 2, 154, FSL_SRDS_BANK_1 },
96 int serdes_get_lane_idx(int lane) in serdes_get_lane_idx() argument
98 return lanes[lane].idx; in serdes_get_lane_idx()
101 int serdes_get_bank_by_lane(int lane) in serdes_get_bank_by_lane() argument
103 return lanes[lane].bank; in serdes_get_bank_by_lane()
106 int serdes_lane_enabled(int lane) in serdes_lane_enabled() argument
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H A Dmpc8536_serdes.c5 * SPDX-License-Identifier: GPL-2.0+
54 #define SRDS2_MAX_LANES 2
97 int lane; in fsl_serdes_init() local
114 case 1: /* Lane A - SATA1, Lane E - SATA2 */ in fsl_serdes_init()
127 /* CR 2 */ in fsl_serdes_init()
142 case 3: /* Lane A - SATA1, Lane E - disabled */ in fsl_serdes_init()
153 /* CR 2 */ in fsl_serdes_init()
164 case 4: /* Lane A - eTSEC1 SGMII, Lane E - eTSEC3 SGMII */ in fsl_serdes_init()
177 /* CR 2 */ in fsl_serdes_init()
192 case 6: /* Lane A - eTSEC1 SGMII, Lane E - disabled */ in fsl_serdes_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_spec.h4 * SPDX-License-Identifier: GPL-2.0
29 PEX_BUS_MODE_X4 = 2,
56 * Bus speed - one bit per SERDES line:
69 {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
70 {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
71 {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
72 {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
73 {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
74 {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
75 {0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Danalogix_dp.c2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch-rockchip/clock.h>
32 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
98 int lane, lane_count, retval; in analogix_dp_link_start() local
100 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
102 dp->link_train.lt_state = CLOCK_RECOVERY; in analogix_dp_link_start()
103 dp->link_train.eq_loop = 0; in analogix_dp_link_start()
105 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
106 dp->link_train.cr_loop[lane] = 0; in analogix_dp_link_start()
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/OK3568_Linux_fs/u-boot/board/highbank/
H A Dahci.c4 * SPDX-License-Identifier: GPL-2.0+
12 #define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2))
82 static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val) in cphy_spread_spectrum_override() argument
85 tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in cphy_spread_spectrum_override()
87 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
90 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
94 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
97 static void cphy_tx_attenuation_override(u8 phy, u8 lane) in cphy_tx_attenuation_override() argument
103 shift = ((phy == 5) ? 4 : lane) * 4; in cphy_tx_attenuation_override()
110 tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE); in cphy_tx_attenuation_override()
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/OK3568_Linux_fs/u-boot/board/freescale/p2041rdb/
H A Deth.c5 * SPDX-License-Identifier: GPL-2.0+
9 * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
10 * are provided by the three on-board PHY or by the standard Freescale
11 * four-port SGMII riser card. We need to change the phy-handle in the
30 * that the mapping must be determined dynamically, or that the lane maps to
34 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
54 lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2; in initialize_lane_to_slot()
55 lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2; in initialize_lane_to_slot()
56 lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2; in initialize_lane_to_slot()
65 * 2) An Fman port
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/OK3568_Linux_fs/u-boot/board/freescale/corenet_ds/
H A Deth_superhydra.c2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
11 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
12 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
13 * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans
34 * 2) The phy-handle property of each active Ethernet MAC node is set to the
39 * values, so those values are hard-coded in the DTS. On the HYDRA board,
46 * 2) An alias for each real and virtual MDIO node that is disabled by default
47 * and might need to be enabled, and also might need to have its mux-value
99 * that the mapping must be determined dynamically, or that the lane maps to
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/ls1043aqds/
H A Deth.c4 * SPDX-License-Identifier: GPL-2.0+
25 #define EMI1_SLOT1 2
44 static u8 lane_to_slot[] = {1, 2, 3, 4};
96 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_read()
98 ls1043aqds_mux_mdio(priv->muxval); in ls1043aqds_mdio_read()
100 return priv->realbus->read(priv->realbus, addr, devad, regnum); in ls1043aqds_mdio_read()
106 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_write()
108 ls1043aqds_mux_mdio(priv->muxval); in ls1043aqds_mdio_write()
110 return priv->realbus->write(priv->realbus, addr, devad, in ls1043aqds_mdio_write()
116 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_reset()
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/t1040qds/
H A Deth.c4 * SPDX-License-Identifier: GPL-2.0+
8 * The RGMII PHYs are provided by the two on-board PHY connected to
9 * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
10 * PHY or by the standard four-port SGMII riser card (VSC).
29 /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
30 * Bank 1 -> Lanes A, B, C, D
31 * Bank 2 -> Lanes E, F, G, H
35 * means that the mapping must be determined dynamically, or that the lane
56 #define EMI1_SLOT1 2
121 struct t1040_qds_mdio *priv = bus->priv; in t1040_qds_mdio_read()
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/OK3568_Linux_fs/kernel/drivers/phy/tegra/
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
86 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL2(x) ((x) < 2 ? 0x078 + (x) * 4 : \
92 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL5(x) ((x) < 2 ? 0x090 + (x) * 4 : \
96 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(x) ((x) < 2 ? 0x098 + (x) * 4 : \
128 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
134 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 2
158 #define XUSB_PADCTL_HSIC_PAD_CTL1_PD_TX (1 << 2)
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
[all …]
H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
33 #define USB2_PORT_SHIFT(x) ((x) * 2)
58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
65 #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
80 #define USB2_OTG_PD_DR BIT(2)
159 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
161 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/i2c/
H A Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
29 * Lane Registers
32 /* TX De-emphasis parameters */
46 #define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2)
137 #define PROT_BUS_WIDTH_SHIFT(n) ((n) * 2)
138 #define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)
152 #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_link_dp.c19 link->ctx->logger
38 /* to avoid infinite loop where-in the receiver
78 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_eq_training_aux_rd_interval()
79 /* DP 1.2 or later - retrieve delay through in get_eq_training_aux_rd_interval()
133 struct encoder_feature_support *features = &link->link_enc->features; in decide_eq_training_pattern()
134 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; in decide_eq_training_pattern()
136 if (features->flags.bits.IS_TPS3_CAPABLE) in decide_eq_training_pattern()
139 if (features->flags.bits.IS_TPS4_CAPABLE) in decide_eq_training_pattern()
142 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED && in decide_eq_training_pattern()
146 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED && in decide_eq_training_pattern()
[all …]
/OK3568_Linux_fs/u-boot/drivers/phy/marvell/
H A Dcomphy_cp110.c2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
20 #define SD_ADDR(base, lane) (base + 0x1000 * lane) argument
21 #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) argument
22 #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) argument
32 * For CP-110 we have 2 Selector registers "PHY Selectors",
40 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
42 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
44 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
47 {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-samsung-hdptx.c1 // SPDX-License-Identifier: GPL-2.0
28 #define PHY_CLK_RDY BIT(2)
49 #define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0)
81 #define ROPLL_SDC_FRACTIONAL_EN_HBR BIT(2)
94 #define ROPLL_SDM_NUMERATOR_SIGN_HBR BIT(2)
102 #define ROPLL_SDC_N_RBR GENMASK(2, 0)
106 #define ROPLL_SDC_N_HBR2 GENMASK(2, 0)
119 #define ROPLL_SDC_NDIV_RSTN BIT(2)
127 #define ANA_ROPLL_SSC_FM_FREQ GENMASK(6, 2)
150 #define ANA_PLL_TX_HS_CLK_EN BIT(2)
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3588-usbdp-phy
23 - description: phy ref clock.
24 - description: phy pcs immortal clock.
25 - description: phy peripheral clock.
[all …]
/OK3568_Linux_fs/u-boot/drivers/phy/
H A Dphy-rockchip-samsung-hdptx.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <generic-phy.h>
28 #define PHY_CLK_RDY BIT(2)
49 #define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0)
81 #define ROPLL_SDC_FRACTIONAL_EN_HBR BIT(2)
94 #define ROPLL_SDM_NUMERATOR_SIGN_HBR BIT(2)
102 #define ROPLL_SDC_N_RBR GENMASK(2, 0)
106 #define ROPLL_SDC_N_HBR2 GENMASK(2, 0)
119 #define ROPLL_SDC_NDIV_RSTN BIT(2)
127 #define ANA_ROPLL_SSC_FM_FREQ GENMASK(6, 2)
[all …]
H A Dphy-rockchip-typec.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on drivers/phy/rockchip/phy-rockchip-typec.c in Linux Kernel.
12 #include <generic-phy.h>
17 #include <asm-generic/io.h>
22 #define CMN_PLL0_VCOCAL_OVRD (0x83 << 2)
23 #define CMN_PLL0_VCOCAL_INIT (0x84 << 2)
24 #define CMN_PLL0_VCOCAL_ITER (0x85 << 2)
25 #define CMN_PLL0_LOCK_REFCNT_START (0x90 << 2)
26 #define CMN_PLL0_LOCK_PLLCNT_START (0x92 << 2)
27 #define CMN_PLL0_LOCK_PLLCNT_THR (0x93 << 2)
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/t4qds/
H A Deth.c4 * SPDX-License-Identifier: GPL-2.0+
35 #define EMI1_SLOT2 2
57 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
61 {0, 1, 2, 3},
112 struct t4240qds_mdio *priv = bus->priv; in t4240qds_mdio_read()
114 t4240qds_mux_mdio(priv->muxval); in t4240qds_mdio_read()
116 return priv->realbus->read(priv->realbus, addr, devad, regnum); in t4240qds_mdio_read()
122 struct t4240qds_mdio *priv = bus->priv; in t4240qds_mdio_write()
124 t4240qds_mux_mdio(priv->muxval); in t4240qds_mdio_write()
126 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); in t4240qds_mdio_write()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c1 // SPDX-License-Identifier: GPL-2.0
7 * WingMan Kwok <w-kwok2@ti.com>
17 /* PCS-R registers */
26 #define MASK_WID_SH(w, s) (((1 << w) - 1) << s)
146 /* lane is 0 based */
148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
152 /* lane setup */ in netcp_xgbe_serdes_lane_config()
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/extcon-provider.h>
66 if (dp->plat_data->skip_connector) in analogix_dp_bandwidth_ok()
69 info = &dp->connector.display_info; in analogix_dp_bandwidth_ok()
70 if (info->bpc) in analogix_dp_bandwidth_ok()
71 bpp = 3 * info->bpc; in analogix_dp_bandwidth_ok()
73 req_bw = mode->clock * bpp / 8; in analogix_dp_bandwidth_ok()
109 mutex_lock(&dp->panel_lock); in analogix_dp_panel_prepare()
111 if (dp->panel_is_prepared) in analogix_dp_panel_prepare()
114 ret = drm_panel_prepare(dp->plat_data->panel); in analogix_dp_panel_prepare()
[all …]

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