Lines Matching +full:2 +full:- +full:lane
2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
20 #define SD_ADDR(base, lane) (base + 0x1000 * lane) argument
21 #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) argument
22 #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) argument
32 * For CP-110 we have 2 Selector registers "PHY Selectors",
40 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
42 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
44 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
47 {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
49 {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
52 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */
57 {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */
58 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */
61 {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */
63 {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */
65 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */
68 {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */
79 } while (data != val && --usec_timout > 0); in polling_with_timeout()
87 static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, in comphy_pcie_power_up() argument
92 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); in comphy_pcie_power_up()
93 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); in comphy_pcie_power_up()
101 * Add SAR (Sample-At-Reset) configuration for the PCIe clock in comphy_pcie_power_up()
103 * U-Boot to mainline version. in comphy_pcie_power_up()
105 * SerDes Lane 4/5 got the PCIe ref-clock #1, in comphy_pcie_power_up()
106 * and SerDes Lane 0 got PCIe ref-clock #0 in comphy_pcie_power_up()
113 if (lane == 0) { in comphy_pcie_power_up()
118 } else if (pcie_width == 2) { in comphy_pcie_power_up()
126 * If PCIe clock is output and clock source from SerDes lane 5, in comphy_pcie_power_up()
127 * we need to configure the clock-source MUX. in comphy_pcie_power_up()
128 * By default, the clock source is from lane 4 in comphy_pcie_power_up()
130 if (pcie_clk && clk_src && (lane == 5)) { in comphy_pcie_power_up()
136 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_pcie_power_up()
137 /* RFU configurations - hard reset comphy */ in comphy_pcie_power_up()
157 /* Wait 1ms - until band gap and ref clock ready */ in comphy_pcie_power_up()
185 /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */ in comphy_pcie_power_up()
192 if (lane == 0) { in comphy_pcie_power_up()
195 } else if (lane == (pcie_width - 1)) { in comphy_pcie_power_up()
208 /* TODO: check if pcie clock is output/input - for bringup use input*/ in comphy_pcie_power_up()
212 /* Only if clock is output, configure the clock-source mux */ in comphy_pcie_power_up()
231 /* Set reference clock comes from group 2 */ in comphy_pcie_power_up()
239 /* Set reference frequcency select - 0x2 for 25MHz*/ in comphy_pcie_power_up()
243 /* Set reference frequcency select - 0x0 for 100MHz*/ in comphy_pcie_power_up()
260 * Set the amount of time spent in the LoZ state - set for 0x7 only if in comphy_pcie_power_up()
407 /* Genration 2 setting 1*/ in comphy_pcie_power_up()
431 /* Set PLL Charge-pump Current Control */ in comphy_pcie_power_up()
436 /* Set lane rqualization remote setting */ in comphy_pcie_power_up()
455 * For PCIe by4 or by2 - release from reset only after finish to in comphy_pcie_power_up()
458 if ((pcie_width == 1) || (lane == (pcie_width - 1))) { in comphy_pcie_power_up()
472 * for PCIe by4 or by2 - release from soft reset in comphy_pcie_power_up()
473 * all lanes - can't use read modify write in comphy_pcie_power_up()
478 start_lane = lane; in comphy_pcie_power_up()
479 end_lane = lane + 1; in comphy_pcie_power_up()
483 * for PCIe by4 or by2 - release from soft reset in comphy_pcie_power_up()
501 /* Read lane status */ in comphy_pcie_power_up()
509 debug("Read from reg = %p - value = 0x%x\n", in comphy_pcie_power_up()
522 static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, in comphy_usb3_power_up() argument
526 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); in comphy_usb3_power_up()
527 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); in comphy_usb3_power_up()
531 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_usb3_power_up()
532 /* RFU configurations - hard reset comphy */ in comphy_usb3_power_up()
552 /* Wait 1ms - until band gap and ref clock ready */ in comphy_usb3_power_up()
574 /* Set reference clock to come from group 1 - 25Mhz */ in comphy_usb3_power_up()
578 /* Set reference frequcency select - 0x2 */ in comphy_usb3_power_up()
581 /* Set PHY mode to USB - 0x5 */ in comphy_usb3_power_up()
585 /* Set the amount of time spent in the LoZ state - set for 0x7 */ in comphy_usb3_power_up()
589 /* Set max PHY generation setting - 5Gbps */ in comphy_usb3_power_up()
593 /* Set select data width 20Bit (SEL_BITS[2:0]) */ in comphy_usb3_power_up()
597 /* select de-emphasize 3.5db */ in comphy_usb3_power_up()
608 /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ in comphy_usb3_power_up()
626 /* wait 15ms - for comphy calibration done */ in comphy_usb3_power_up()
628 /* Read lane status */ in comphy_usb3_power_up()
634 debug("Read from reg = %p - value = 0x%x\n", in comphy_usb3_power_up()
644 static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, in comphy_sata_power_up() argument
648 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); in comphy_sata_power_up()
649 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); in comphy_sata_power_up()
650 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); in comphy_sata_power_up()
653 int sata_node = -1; /* Set to -1 in order to read the first sata node */ in comphy_sata_power_up()
658 * Assumption - each CP has only one SATA controller in comphy_sata_power_up()
659 * Calling fdt_node_offset_by_compatible first time (with sata_node = -1 in comphy_sata_power_up()
666 gd->fdt_blob, sata_node, "marvell,armada-8k-ahci"); in comphy_sata_power_up()
674 gd->fdt_blob, sata_node, "reg", 0, NULL, true); in comphy_sata_power_up()
682 debug("stage: MAC configuration - power down comphy\n"); in comphy_sata_power_up()
704 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_sata_power_up()
705 /* RFU configurations - hard reset comphy */ in comphy_sata_power_up()
716 /* Set select data width 40Bit - SATA mode only */ in comphy_sata_power_up()
728 /* Wait 1ms - until band gap and ref clock ready */ in comphy_sata_power_up()
733 /* Set reference clock to comes from group 1 - choose 25Mhz */ in comphy_sata_power_up()
744 /* Set max PHY generation setting - 6Gbps */ in comphy_sata_power_up()
748 /* Set select data width 40Bit (SEL_BITS[2:0]) */ in comphy_sata_power_up()
844 /* DFE F3-F5 Coefficient Control */ in comphy_sata_power_up()
919 /* SERDES External Configuration 2 register */ in comphy_sata_power_up()
941 * MAC configuration power up comphy - power up PLL/TX/RX in comphy_sata_power_up()
977 debug("Read from reg = %p - value = 0x%x\n", in comphy_sata_power_up()
989 static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed, in comphy_sgmii_power_up() argument
994 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); in comphy_sgmii_power_up()
995 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); in comphy_sgmii_power_up()
996 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); in comphy_sgmii_power_up()
1000 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_sgmii_power_up()
1001 /* RFU configurations - hard reset comphy */ in comphy_sgmii_power_up()
1046 /* Wait 1ms - until band gap and ref clock ready */ in comphy_sgmii_power_up()
1076 /* Set analog paramters from ETP(HW) - for now use the default datas */ in comphy_sgmii_power_up()
1083 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); in comphy_sgmii_power_up()
1100 debug("Read from reg = %p - value = 0x%x\n", in comphy_sgmii_power_up()
1119 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sgmii_power_up()
1136 static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, in comphy_sfi_power_up() argument
1140 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); in comphy_sfi_power_up()
1141 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); in comphy_sfi_power_up()
1142 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); in comphy_sfi_power_up()
1146 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_sfi_power_up()
1147 /* RFU configurations - hard reset comphy */ in comphy_sfi_power_up()
1185 /* Wait 1ms - until band gap and ref clock ready */ in comphy_sfi_power_up()
1237 /* SERDES External Configuration 2 */ in comphy_sfi_power_up()
1241 /* 0x7-DFE Resolution control */ in comphy_sfi_power_up()
1245 /* 0xd-G1_Setting_0 */ in comphy_sfi_power_up()
1256 /* Genration 1 setting 2 (G1_Setting_2) */ in comphy_sfi_power_up()
1278 /* 0xE-G1_Setting_1 */ in comphy_sfi_power_up()
1300 /* 0xA-DFE_Reg3 */ in comphy_sfi_power_up()
1307 /* 0x111-G1_Setting_4 */ in comphy_sfi_power_up()
1382 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); in comphy_sfi_power_up()
1400 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sfi_power_up()
1419 debug("Read from reg = %p - value = 0x%x\n", in comphy_sfi_power_up()
1437 static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base, in comphy_rxauii_power_up() argument
1441 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); in comphy_rxauii_power_up()
1442 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); in comphy_rxauii_power_up()
1443 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); in comphy_rxauii_power_up()
1447 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_rxauii_power_up()
1448 /* RFU configurations - hard reset comphy */ in comphy_rxauii_power_up()
1455 if (lane == 2) { in comphy_rxauii_power_up()
1460 if (lane == 4) { in comphy_rxauii_power_up()
1498 /* Wait 1ms - until band gap and ref clock ready */ in comphy_rxauii_power_up()
1529 /* SERDES External Configuration 2 */ in comphy_rxauii_power_up()
1533 /* 0x7-DFE Resolution control */ in comphy_rxauii_power_up()
1536 /* 0xd-G1_Setting_0 */ in comphy_rxauii_power_up()
1540 /* 0xE-G1_Setting_1 */ in comphy_rxauii_power_up()
1548 /* 0xA-DFE_Reg3 */ in comphy_rxauii_power_up()
1555 /* 0x111-G1_Setting_4 */ in comphy_rxauii_power_up()
1560 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); in comphy_rxauii_power_up()
1578 debug("Read from reg = %p - value = 0x%x\n", in comphy_rxauii_power_up()
1597 debug("Read from reg = %p - value = 0x%x\n", in comphy_rxauii_power_up()
1623 debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n", in comphy_utmi_power_down()
1634 debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n", in comphy_utmi_power_down()
1672 /* Feedback Clock Divider Select - 90 for 25Mhz*/ in comphy_utmi_phy_config()
1675 /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/ in comphy_utmi_phy_config()
1709 /* Set Control VDAT Reference Voltage - 0.325V */ in comphy_utmi_phy_config()
1712 /* Set Control VSRC Reference Voltage - 0.6V */ in comphy_utmi_phy_config()
1729 debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n", in comphy_utmi_power_up()
1746 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()
1755 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()
1765 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()
1782 * 2. UTMI PHY configure
1784 * Note: - Power down/up should be once for both UTMI PHYs
1785 * - comphy_dedicated_phys_init call this function if at least there is
1845 * - not muxed SerDes lanes e.g. UTMI PHY
1857 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, in comphy_dedicated_phys_init()
1858 "marvell,mvebu-utmi-2.6.0"); in comphy_dedicated_phys_init()
1865 gd->fdt_blob, node, "reg", 0, NULL, true); in comphy_dedicated_phys_init()
1875 gd->fdt_blob, node, "reg", 1, NULL, true); in comphy_dedicated_phys_init()
1885 gd->fdt_blob, node, "reg", 2, NULL, true); in comphy_dedicated_phys_init()
1897 gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID); in comphy_dedicated_phys_init()
1905 gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0"); in comphy_dedicated_phys_init()
1921 u32 lane, comphy_max_count; in comphy_mux_cp110_init() local
1923 comphy_max_count = ptr_chip_cfg->comphy_lanes_count; in comphy_mux_cp110_init()
1924 comphy_base_addr = ptr_chip_cfg->comphy_base_addr; in comphy_mux_cp110_init()
1928 * the comphy_mux_init modify the type of the lane if the type in comphy_mux_cp110_init()
1929 * is not valid because we have 2 selectores run the in comphy_mux_cp110_init()
1933 for (lane = 0; lane < comphy_max_count; lane++) { in comphy_mux_cp110_init()
1934 comphy_map_pipe_data[lane].type = serdes_map[lane].type; in comphy_mux_cp110_init()
1935 comphy_map_pipe_data[lane].speed = serdes_map[lane].speed; in comphy_mux_cp110_init()
1936 comphy_map_phy_data[lane].type = serdes_map[lane].type; in comphy_mux_cp110_init()
1937 comphy_map_phy_data[lane].speed = serdes_map[lane].speed; in comphy_mux_cp110_init()
1939 ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data; in comphy_mux_cp110_init()
1943 ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data; in comphy_mux_cp110_init()
1947 for (lane = 0; lane < comphy_max_count; lane++) { in comphy_mux_cp110_init()
1948 if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) && in comphy_mux_cp110_init()
1949 (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED)) in comphy_mux_cp110_init()
1950 serdes_map[lane].type = PHY_TYPE_UNCONNECTED; in comphy_mux_cp110_init()
1959 u32 comphy_max_count, lane, ret = 0; in comphy_cp110_init() local
1964 comphy_max_count = ptr_chip_cfg->comphy_lanes_count; in comphy_cp110_init()
1965 comphy_base_addr = ptr_chip_cfg->comphy_base_addr; in comphy_cp110_init()
1966 hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; in comphy_cp110_init()
1971 /* Check if the first 4 lanes configured as By-4 */ in comphy_cp110_init()
1972 for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; in comphy_cp110_init()
1973 lane++, ptr_comphy_map++) { in comphy_cp110_init()
1974 if (ptr_comphy_map->type != PHY_TYPE_PEX0) in comphy_cp110_init()
1979 for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count; in comphy_cp110_init()
1980 lane++, ptr_comphy_map++) { in comphy_cp110_init()
1981 debug("Initialize serdes number %d\n", lane); in comphy_cp110_init()
1982 debug("Serdes type = 0x%x\n", ptr_comphy_map->type); in comphy_cp110_init()
1983 if (lane == 4) { in comphy_cp110_init()
1990 switch (ptr_comphy_map->type) { in comphy_cp110_init()
2000 lane, pcie_width, ptr_comphy_map->clk_src, in comphy_cp110_init()
2001 serdes_map->end_point, in comphy_cp110_init()
2009 lane, hpipe_base_addr, comphy_base_addr, in comphy_cp110_init()
2010 ptr_chip_cfg->cp_index); in comphy_cp110_init()
2015 ret = comphy_usb3_power_up(lane, hpipe_base_addr, in comphy_cp110_init()
2022 if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { in comphy_cp110_init()
2023 debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", in comphy_cp110_init()
2024 lane); in comphy_cp110_init()
2025 ptr_comphy_map->speed = PHY_SPEED_1_25G; in comphy_cp110_init()
2028 lane, ptr_comphy_map->speed, hpipe_base_addr, in comphy_cp110_init()
2032 ret = comphy_sfi_power_up(lane, hpipe_base_addr, in comphy_cp110_init()
2034 ptr_comphy_map->speed); in comphy_cp110_init()
2038 ret = comphy_rxauii_power_up(lane, hpipe_base_addr, in comphy_cp110_init()
2043 lane); in comphy_cp110_init()
2048 * If interface wans't initialized, set the lane to in comphy_cp110_init()
2051 ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; in comphy_cp110_init()
2052 pr_err("PLL is not locked - Failed to initialize lane %d\n", in comphy_cp110_init()
2053 lane); in comphy_cp110_init()