5  * SPDX-License-Identifier:	GPL-2.0+
9  * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
10  * are provided by the three on-board PHY or by the standard Freescale
11  * four-port SGMII riser card. We need to change the phy-handle in the
30  * that the mapping must be determined dynamically, or that the lane maps to
34 	0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
54 	lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2;  in initialize_lane_to_slot()
55 	lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2;  in initialize_lane_to_slot()
56 	lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2;  in initialize_lane_to_slot()
65  * 2) An Fman port
67  * ... update the phy-handle property of the Ethernet node to point to the
75  * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
93 		int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);  in board_ft_fman_fixup_port()  local
95 		if (lane < 0)  in board_ft_fman_fixup_port()
97 		slot = lane_to_slot[lane];  in board_ft_fman_fixup_port()
101 					+ (port - FM1_DTSEC1));  in board_ft_fman_fixup_port()
106 					+ (port - FM1_DTSEC1));  in board_ft_fman_fixup_port()
113 		int lane = serdes_get_first_lane(XAUI_FM1);  in board_ft_fman_fixup_port()  local
114 		if (lane >= 0) {  in board_ft_fman_fixup_port()
116 			sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);  in board_ft_fman_fixup_port()
129 	int lane;  in board_eth_init()  local
150 	 * Program the three on-board SGMII PHY addresses. If the SGMII Riser  in board_eth_init()
160 		int idx = i - FM1_DTSEC1;  in board_eth_init()
164 			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);  in board_eth_init()
165 			if (lane < 0)  in board_eth_init()
167 			slot = lane_to_slot[lane];  in board_eth_init()
187 	lane = serdes_get_first_lane(XAUI_FM1);  in board_eth_init()
188 	if (lane >= 0) {  in board_eth_init()
189 		slot = lane_to_slot[lane];  in board_eth_init()