| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3358-linux.dtsi | 11 …bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 roo…
17 rockchip,wake-irq = <0>;
19 rockchip,irq-mode-enable = <0>;
23 pinctrl-0 = <&uart2m0_xfer>;
34 reg = <0x0 0x0 0x0 0x0>;
39 reg = <0x0 0x110000 0x0 0xf0000>;
40 record-size = <0x20000>;
41 console-size = <0x80000>;
42 ftrace-size = <0x00000>;
43 pmsg-size = <0x50000>;
|
| H A D | rk3326-linux.dtsi | 17 …bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 roo…
23 rockchip,wake-irq = <0>;
29 pinctrl-0 = <&uart2m0_xfer>;
40 reg = <0x0 0x0 0x0 0x0>;
45 reg = <0x0 0x110000 0x0 0xf0000>;
46 record-size = <0x20000>;
47 console-size = <0x80000>;
48 ftrace-size = <0x00000>;
49 pmsg-size = <0x50000>;
|
| H A D | px30-android.dtsi | 9 bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 init=/init kpti=0";
15 rockchip,wake-irq = <0>;
21 pinctrl-0 = <&uart2m0_xfer>;
41 reg = <0x0 0x0 0x0 0x0>;
46 reg = <0x0 0x110000 0x0 0xf0000>;
47 record-size = <0x20000>;
48 console-size = <0x80000>;
49 ftrace-size = <0x00000>;
50 pmsg-size = <0x50000>;
55 reg = <0x0 0x0 0x0 0x0>;
[all …]
|
| H A D | rk3326-evb-lp3-v10-linux.dts | 16 …bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 roo…
28 vsync-active = <0>;
39 pinctrl-0 = <&i2c2_xfer &cif_clkout_m0>;
47 reg = <0x3c>;
49 pinctrl-0 = <&cif_pin_m0>;
70 reg = <0x36>;
82 rockchip,camera-module-index = <0>;
101 #size-cells = <0>;
103 port@0 {
104 reg = <0>;
[all …]
|
| H A D | rk3368.dtsi | 43 #address-cells = <0x2>;
44 #size-cells = <0x0>;
78 cpu_l0: cpu@0 {
81 reg = <0x0 0x0>;
89 reg = <0x0 0x1>;
97 reg = <0x0 0x2>;
105 reg = <0x0 0x3>;
113 reg = <0x0 0x100>;
121 reg = <0x0 0x101>;
129 reg = <0x0 0x102>;
[all …]
|
| H A D | rk3328.dtsi | 40 #size-cells = <0>;
42 cpu0: cpu@0 {
45 reg = <0x0 0x0>;
58 reg = <0x0 0x1>;
71 reg = <0x0 0x2>;
84 reg = <0x0 0x3>;
100 arm,psci-suspend-param = <0x0010000>;
157 reg = <0x0 0xff1f0000 0x0 0x4000>;
158 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
228 #clock-cells = <0>;
[all …]
|
| /OK3568_Linux_fs/u-boot/configs/ |
| H A D | rk3326-aarch32_defconfig | 3 CONFIG_SYS_MALLOC_F_LEN=0x2000
7 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
17 CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
20 CONFIG_BOOTDELAY=0
25 CONFIG_FASTBOOT_BUF_ADDR=0x800800
26 CONFIG_FASTBOOT_BUF_SIZE=0x04000000
28 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
52 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock…
87 CONFIG_DEBUG_UART_BASE=0xFF160000
100 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
[all …]
|
| H A D | evb-rk3326_defconfig | 5 CONFIG_SYS_MALLOC_F_LEN=0x2000
9 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
17 CONFIG_SPL_STACK_R_ADDR=0x600000
20 CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
24 CONFIG_BOOTDELAY=0
31 CONFIG_FASTBOOT_BUF_ADDR=0x800800
32 CONFIG_FASTBOOT_BUF_SIZE=0x04000000
34 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
62 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock…
95 CONFIG_DEBUG_UART_BASE=0xFF160000
[all …]
|
| H A D | evb-px30_defconfig | 5 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
15 CONFIG_SPL_STACK_R_ADDR=0x600000
18 CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
22 CONFIG_BOOTDELAY=0
29 CONFIG_FASTBOOT_BUF_ADDR=0x800800
30 CONFIG_FASTBOOT_BUF_SIZE=0x04000000
32 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
58 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock…
95 CONFIG_DEBUG_UART_BASE=0xFF160000
[all …]
|
| H A D | px30_defconfig | 5 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
15 CONFIG_SPL_STACK_R_ADDR=0x600000
18 CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
22 CONFIG_BOOTDELAY=0
30 CONFIG_FASTBOOT_BUF_ADDR=0x800800
31 CONFIG_FASTBOOT_BUF_SIZE=0x04000000
33 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
60 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock…
103 CONFIG_DEBUG_UART_BASE=0xFF160000
[all …]
|
| H A D | rk3326_defconfig | 5 CONFIG_SYS_MALLOC_F_LEN=0x2000
9 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
17 CONFIG_SPL_STACK_R_ADDR=0x600000
20 CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
24 CONFIG_BOOTDELAY=0
34 CONFIG_FASTBOOT_BUF_ADDR=0x800800
35 CONFIG_FASTBOOT_BUF_SIZE=0x04000000
37 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
65 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock…
106 CONFIG_DEBUG_UART_BASE=0xFF160000
[all …]
|
| H A D | px30-tb_defconfig | 5 CONFIG_SYS_MALLOC_F_LEN=0x80000
8 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
14 CONFIG_SPL_STACK_R_ADDR=0x600000
18 CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
25 CONFIG_BOOTDELAY=0
35 CONFIG_FASTBOOT_BUF_ADDR=0x800800
36 CONFIG_FASTBOOT_BUF_SIZE=0x04000000
38 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
66 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock…
111 CONFIG_DEBUG_UART_BASE=0xFF160000
[all …]
|
| /OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 20 #define PMU_PWRDN_CON 0xff000018
21 #define GRF_CPU_CON1 0xff140504
23 #define USBPHY_GRF_BASE 0xff2c0000
24 #define VIDEO_PHY_BASE 0xff2e0000
25 #define FW_DDR_CON_REG 0xff534040
26 #define SERVICE_CORE_ADDR 0xff508000
27 #define QOS_PRIORITY 0x08
36 .virt = 0x0UL,
37 .phys = 0x0UL,
38 .size = 0xff000000UL,
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/ |
| H A D | arasan,sdhci.yaml | 129 enum: [0, 1]
150 enum: [0, 2]
151 default: 0
172 reg = <0xe0100000 0x1000>;
176 interrupts = <0 24 4>;
182 reg = <0xe2800000 0x1000>;
186 interrupts = <0 24 4>;
197 reg = <0xfe330000 0x10000>;
207 #clock-cells = <0>;
214 interrupts = <0 48 4>;
[all …]
|
| /OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rv1106/ |
| H A D | rv1106.c | 20 #define PERI_GRF_BASE 0xff000000
21 #define PERI_GRF_PERI_CON1 0x0004
23 #define CORE_GRF_BASE 0xff040000
24 #define CORE_GRF_CACHE_PERI_ADDR_START 0x0024
25 #define CORE_GRF_CACHE_PERI_ADDR_END 0x0028
26 #define CORE_GRF_MCU_CACHE_MISC 0x002c
28 #define PERI_GRF_BASE 0xff000000
29 #define PERI_GRF_USBPHY_CON0 0x0050
31 #define PERI_SGRF_BASE 0xff070000
32 #define PERI_SGRF_FIREWALL_CON0 0x0020
[all …]
|
| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/xilinx/ |
| H A D | zynqmp.dtsi | 25 #size-cells = <0>;
27 cpu0: cpu@0 {
32 reg = <0x0>;
40 reg = <0x1>;
49 reg = <0x2>;
58 reg = <0x3>;
66 CPU_SLEEP_0: cpu-sleep-0 {
68 arm,psci-suspend-param = <0x40000000>;
110 interrupts = <0 143 4>,
111 <0 144 4>,
[all …]
|
| /OK3568_Linux_fs/u-boot/arch/arm/dts/ |
| H A D | zynqmp.dtsi | 18 #size-cells = <0>;
20 cpu@0 {
24 reg = <0x0>;
32 reg = <0x1>;
40 reg = <0x2>;
48 reg = <0x3>;
55 CPU_SLEEP_0: cpu-sleep-0 {
57 arm,psci-suspend-param = <0x40000000>;
76 #power-domain-cells = <0x0>;
77 pd-id = <0x16>;
[all …]
|
| H A D | rk3368.dtsi | 76 #address-cells = <0x2>;
77 #size-cells = <0x0>;
114 cpu_sleep: cpu-sleep-0 {
116 arm,psci-suspend-param = <0x1010000>;
117 entry-latency-us = <0x3fffffff>;
118 exit-latency-us = <0x40000000>;
119 min-residency-us = <0xffffffff>;
123 cpu_l0: cpu@0 {
126 reg = <0x0 0x0>;
136 reg = <0x0 0x1>;
[all …]
|
| H A D | .rk3368-sheep.dtb.dts.tmp | |
| H A D | .rk3368-geekbox.dtb.dts.tmp | |
| H A D | .rk3368-lion.dtb.dts.tmp | |
| H A D | .rk3368-px5-evb.dtb.dts.tmp | |
| H A D | rk3328.dtsi | 35 #size-cells = <0>;
37 cpu0: cpu@0 {
40 reg = <0x0 0x0>;
48 reg = <0x0 0x1>;
54 reg = <0x0 0x2>;
60 reg = <0x0 0x3>;
126 #clock-cells = <0>;
133 reg = <0x0 0xff000000 0x0 0x1000>;
145 reg = <0x0 0xff010000 0x0 0x1000>;
157 reg = <0x0 0xff020000 0x0 0x1000>;
[all …]
|
| H A D | rk3288.dtsi | 55 #size-cells = <0>;
62 reg = <0x500>;
87 reg = <0x501>;
93 reg = <0x502>;
99 reg = <0x503>;
113 reg = <0xff250000 0x4000>;
124 reg = <0xff600000 0x4000>;
125 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
136 reg = <0xffb20000 0x4000>;
137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
|
| H A D | .rk3328-evb.dtb.dts.tmp | |